Datasheet

 2011-2012 Microchip Technology Inc. Preliminary DS41579D-page 245

PIC16(L)F1782/3

(1)

R/W-0/0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

PxPRSIN

— — — PxPRSC3 PxPRSC2 PxPRSC1 PxPRST

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7

PxPRSIN: PSMCx Period Event occurs on PSMCxIN pin

1 = Period event will occur and PSMCxTMR will reset when PSMCxIN pin goes true

0 = PSMCxIN pin will not cause period event

bit 6-4

Unimplemented: Read as ‘0’

bit 3

PxPRSC3: PSMCx Period Event occurs on sync_C3OUT output

1 = Period event will occur and PSMCxTMR will reset when sync_C3OUT output goes true

0 = sync_C3OUT will not cause period event

bit 2 PxPRSC2: PSMCx Period Event occurs on sync_C2OUT output

1 = Period event will occur and PSMCxTMR will reset when sync_C2OUT output goes true

0 = sync_C2OUT will not cause period event

bit 1

PxPRSC1: PSMCx Period Event occurs on sync_C1OUT output

1 = Period event will occur and PSMCxTMR will reset when sync_C1OUT output goes true

0 = sync_C1OUT will not cause period event

bit 0

PxPRST: PSMCx Period Event occurs on Time Base match

1 = Period event will occur and PSMCxTMR will reset when PSMCxTMR = PSMCxPR

0 = Time base will not cause period event

Note 1: Sources are not mutually exclusive: more than one source can force the period event and reset the

PSMCxTMR.