Datasheet

PIC16(L)F1782/3
DS41579D-page 236 Preliminary  2011-2012 Microchip Technology Inc.
24.10 Register Updates
There are 10 double-buffered registers that can be
updated “on the fly”. However, due to the
asynchronous nature of the potential updates, a
special hardware system is used for the updates.
There are two operating cases for the PSMC:
• module is enabled
• module is disabled
24.10.1 DOUBLE BUFFERED REGISTERS
The double-buffered registers that are affected by the
special hardware update system are:
• PSMCxPRL
• PSMCxPRH
• PSMCxDCL
• PSMCxDCH
• PSMCxPHL
• PSMCxPHH
• PSMCxDBR
• PSMCxDBF
• PSMCxBLKR
• PSMCxBLKF
• PSMCxSTR0 (when the PxSSYNC bit is set)
24.10.2 MODULE DISABLED UPDATES
When the PSMC module is disabled (PSMCxEN = 0),
any write to one of the buffered registers will also write
directly to the buffer. This means that all buffers are
loaded and ready for use when the module is enabled.
24.10.3 MODULE ENABLED UPDATES
When the PSMC module is enabled (PSMCxEN = 1),
the PSMCxLD bit of the PSMC Control (PSMCxCON)
register (Register 24-1) must be used.
When the PSMCxLD bit is set, the transfer from the
register to the buffer occurs on the next period event.
The PSMCxLD bit is automatically cleared by hardware
after the transfer to the buffers is complete.
The reason that the PSMCxLD bit is required is that
depending on the customer application and operation
conditions, all 10 registers may not be updated in one
PSMC period. If the buffers are loaded at different
times (i.e., DCL gets updated, but DCH does not OR
DCL and DCL are updated by PRH and PRL are not),
then unintended operation may occur.
The sequence for loading the buffer registers when the
PSMC module is enabled is as follows:
1. Software updates all registers.
2. Software sets the PSMCxLD bit.
3. Hardware updates all buffers on the next period
event.
4. Hardware clears PSMCxLD bit.
24.11 Operation During Sleep
The PSMC continues to operate in Sleep with the
following clock sources:
• Internal 64 MHz
• External clock