Datasheet

 2011-2012 Microchip Technology Inc. Preliminary DS41579D-page 233
PIC16(L)F1782/3
24.8 PSMC Synchronization
It is possible to synchronize the periods of two or more
PSMC modules together, provided that all modules
are on the same device.
Synchronization is achieved by sending a sync signal
from the master PSMC module to the desired slave
modules. This sync signal generates a period event in
each slave module, thereby aligning all slaves with the
master. This is useful when an application requires
different PWM signal generation from each module but
the waveforms must be consistent within a PWM
period.
24.8.1 SYNCHRONIZATION SOURCES
The synchronization source can be any PSMC module
on the same device. For example, in a device with two
PSMC modules, the possible sources for each device
is as shown below:
• Sources for PSMC1
- PSMC2
• Sources for PSMC2
- PSMC1
FIGURE 24-21: PSMC SYNCHRONIZATION - SYNC OUTPUT TO PIN
24.8.1.1 PSMC Internal Connections
The sync signal from the master PSMC module is
essentially that module’s period event trigger. The
slave PSMC modules receive and process the sync
signal as an additional period event input.
Enabling a module as a slave recipient is done with
the PxSYNC bits of the PSMC Synchronization
Control (PSMCxSYNC) registers; registers 24-3
and 24-4.
24.8.1.2 Phase Offset Synchronization
The synchronization output signal from the PSMC
module is selectable. The sync_out source may be
either:
• Period Event
• Rising Event
Source selection is made with the PxPOFST bit of the
PSMCxSYNC registers, registers 24-3, 24-4 and 24-5.
When the PxPOFST bit is set, the sync_out signal
comes from the rising event and the period event
replaces the rising event as the start of the active drive
period. When PxPOFST is set, duty cycles of up to
100% are achievable in both the slave and master.
When PXPOFST is clear, the sync_out signal comes
from the period event. When PxPOFST is clear, rising
events that start after the period event remove the
equivalent start delay percentage from the maximum
100% duty cycle.
24.8.1.3 Synchronization Skid
When the sync_out source is the Period Event, the
slave synchronous rising and falling events will lag by
one psmc_clk period. When the sync_out source is the
Rising Event, the synchronous events will lag by two
clock periods. To compensate for this, the values in
PHH:PHL and DCH:DCL registers can be reduced by
the number of lag cycles.
1 2 3
Caution must be used so that glitches on the period event are not missed
psmc_clk
Period Event
Rising Edge Event
Falling Edge Event
PSMCx Output