Datasheet

 2011-2012 Microchip Technology Inc. Preliminary DS41579D-page 229
PIC16(L)F1782/3
24.5.4 SYNCHRONIZED PWM STEERING
In Single, Complementary and 3-phase PWM modes,
it is possible to synchronize changes to steering
selections with the period event. This is so that PWM
outputs do not change in the middle of a cycle and
therefore, disrupt operation of the application.
Steering synchronization is enabled by setting the
PxSSYNC bit of the PSMC Steering Control 1
(PSMCxSTR1) register (Register 24-31).
When synchronized steering is enabled while the
PSMC module is enabled, steering changes do not
take effect until the first period event after the
PSMCxLD bit is set.
Examples of synchronized steering are shown in
Figure 24-18.
24.5.5 INITIALIZING SYNCHRONIZED
STEERING
If synchronized steering is to be used, special care
should be taken to initialize the PSMC Steering
Control 0 (PSMCxSTR0) register (Register 24-30) in a
safe configuration before setting either the PSMCxEN
or PSMCxLD bits. When either of those bits are set,
the PSMCxSTR0 value at that time is loaded into the
synchronized steering output buffer. The buffer load
occurs even if the PxSSYNC bit is low. When the
PxSSYNC bit is set, the outputs will immediately go to
the drive states in the preloaded buffer.
FIGURE 24-18: PWM STEERING WITH SYNCHRONIZATION WAVEFORM
1 2 3 4 5 6 7
PWM Signal
PxSTRA
Synchronized PxSTRA
PSMCxA
Period Number
PxSTRB
Synchronized PxSTRB
PSMCxB