Datasheet

PIC16(L)F1782/3
DS41579D-page 208 Preliminary  2011-2012 Microchip Technology Inc.
24.2.1.4 16-bit Duty Cycle Register
The PSMCxDC Duty Cycle register is used to
determine a synchronous falling edge event
referenced to the 16-bit PSMCxTMR digital counter. A
match between the PSMCxTMR and PSMCxDC
register values will generate a falling edge event.
The match will generate a duty cycle match interrupt,
thereby setting the PxTDCIF bit of the PSMC Time
Base Interrupt Control (PSMCxINT) register
(Register 24-32).
The 16-bit duty cycle value is accessible to software
as two 8-bit registers:
• PSMC Duty Cycle Count Low Byte (PSMCxDCL)
register (Register 24-21)
• PSMC Duty Cycle Count High Byte (PSMCxDCH)
register (Register 24-22)
The 16-bit duty cycle value is double-buffered before it
is presented to the 16-bit time base for comparison.
The buffered registers are updated on the first period
event Reset after the PSMCxLD bit of the PSMCxCON
register is set.
When the period, phase, and duty cycle are all deter-
mined from the time base, the effective PWM duty
cycle can be expressed as shown in Equation 24-2.
EQUATION 24-2: PWM DUTY CYCLE
24.2.2 0% DUTY CYCLE OPERATION
USING TIME BASE
To configure the PWM for 0% duty cycle set
PSMCxDC<15:0> = PSMCxPH<15:0>. This will trigger
a falling edge event simultaneous with the rising edge
event and prevent the PWM from being asserted.
24.2.3 100% DUTY CYCLE OPERATION
USING TIME BASE
To configure the PWM for 100% duty cycle set
PSMCxDC<15:0> > PSMCxPR<15:0>.
This will prevent a falling edge event from occurring as
the PSMCxDC<15:0> value and the time base value
PSMCxTMR<15:0> will never be equal.
24.2.4 TIME BASE INTERRUPT
GENERATION
The Time Base section can generate four unique
interrupts:
• Time Base Counter Overflow Interrupt
• Time Base Phase Register Match Interrupt
• Time Base Duty Cycle Register Match Interrupt
• Time Base Period Register Match Interrupt
Each interrupt has an interrupt flag bit and an interrupt
enable bit. The interrupt flag bit is set anytime a given
event occurs, regardless of the status of the enable
bit.
Time base interrupt enables and flags are located in the
PSMC Time Base Interrupt Control (PSMCxINT)
register (Register 24-32).
PSMC time base interrupts also require that the
PSMCxTIE bit in the PIE4 register and the PEIE and
GIE bits in the INTCON register be set in order to
generate an interrupt. The PSMCxTIF interrupt flag in
the PIR4 register will only be set by a time base
interrupt when one or more of the enable bits in the
PSMCxINT register is set.
The interrupt flag bits need to be cleared in software.
However, all PMSCx time base interrupt flags, except
PSMCxTIF, are cleared when the PSMCxEN bit is
cleared.
Interrupt bits that are set by software will generate an
interrupt provided that the corresponding interrupt is
enabled.
24.2.5 PSMC TIME BASE CLOCK
SOURCES
There are three clock sources available to the module:
• Internal 64 MHz clock
• Fosc system clock
• External clock input pin
The clock source is selected with the PxCSRC<1:0>
bits of the PSMCx Clock Control (PSMCxCLK) register
(Register 24-5).
When the Internal 64 MHz clock is selected as the
source, the HFINTOSC continues to operate and clock
the PSMC circuitry in Sleep. However, the system
clock to other peripherals and the CPU is suppressed.
The Internal 64 MHz clock utilizes the system clock
4x PLL. When the system clock source is external and
the PSMC is using the Internal 64 MHz clock, the
4x PLL should not be used for the system clock.
24.2.6 CLOCK PRESCALER
There are four prescaler choices available to be
applied to the selected clock:
• Divide by 1
• Divide by 2
• Divide by 4
• Divide by 8
The clock source is selected with the PxCPRE<1:0>
bits of the PSMCx Clock Control (PSMCxCLK) register
(Register 24-5).
The prescaler output is psmc_clk, which is the clock
used by all of the other portions of the PSMC module.
DUTYCYCLE
PSMCxDC[15:0] PSMCxPH[15:0]–
PSMCxPR[15:0] 1+
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