Datasheet

 2011-2012 Microchip Technology Inc. Preliminary DS41579D-page 207
PIC16(L)F1782/3
24.2 Event Sources
There are two main sources for the period, rising edge
and falling edge events:
• Synchronous input
- Time base
• Asynchronous Inputs
- Digital Inputs
- Analog inputs
24.2.1 TIME BASE
The Time Base section consists of several smaller
pieces.
• 16-bit time base counter
• 16-bit Period register
• 16-bit Phase register (rising edge event)
• 16-bit Duty Cycle register (falling edge event)
• Clock control
• Interrupt Generator
An example of a fully synchronous PWM waveform
generated with the time base is shown in Figure 24-2.
The PSMCxLD bit of the PSMCxCON register is
provided to synchronize changes to the event Count
registers. Changes are withheld from taking action until
the first period event Reset after the PSMCxLD bit is
set. For example, to change the PWM frequency, while
maintaining the same effective duty cycle, the Period
and Duty Cycle registers need to be changed. The
changes to all four registers take effect simultaneously
on the period event Reset after the PSMCxLD bit is set.
24.2.1.1 16-bit Counter (Time Base)
The PSMCxTMR is the counter used as a timing
reference for each synchronous PWM period. The
counter starts at 0000h and increments to FFFFh on
the rising edge of the psmc_clk signal.
When the counter rolls over from FFFFh to 0000h
without a period event occurring, the overflow interrupt
will be generated, thereby setting the PxTOVIF bit of
the PSMC Time Base Interrupt Control (PSMCxINT)
register (Register 24-32).
The PSMCxTMR counter is reset on both synchronous
and asynchronous period events.
The PSMCxTMR is accessible to software as two 8-bit
registers:
• PSMC Time Base Counter Low (PSMCxTMRL)
register (Register 24-17)
• PSMC PSMC Time Base Counter High
(PSMCxTMRH) register (Register 24-18)
PSMCxTMR is reset to the default POR value when the
PSMCxEN bit is cleared.
24.2.1.2 16-bit Period Register
The PSMCxPR Period register is used to determine a
synchronous period event referenced to the 16-bit
PSMCxTMR digital counter. A match between the
PSMCxTMR and PSMCxPR register values will
generate a period event.
The match will generate a period match interrupt,
thereby setting the PxTPRIF bit of the PSMC Time Base
Interrupt Control (PSMCxINT) register (Register 24-32).
The 16-bit period value is accessible to software as
two 8-bit registers:
• PSMC Period Count Low Byte (PSMCxPRL)
register (Register 24-23)
• PSMC Period Count High Byte (PSMCxPRH)
register (Register 24-24)
The 16-bit period value is double-buffered before it is
presented to the 16-bit time base for comparison. The
buffered registers are updated on the first period event
Reset after the PSMCxLD bit of the PSMCxCON
register is set.
The synchronous PWM period time can be determined
from Equation 24-1.
EQUATION 24-1: PWM PERIOD
24.2.1.3 16-bit Phase Register
The PSMCxPH Phase register is used to determine a
synchronous rising edge event referenced to the 16-bit
PSMCxTMR digital counter. A match between the
PSMCxTMR and the PSMCxPH register values will
generate a rising edge event.
The match will generate a phase match interrupt,
thereby setting the PxTPHIF bit of the PSMC Time
Base Interrupt Control (PSMCxINT) register
(Register 24-32).
The 16-bit phase value is accessible to software as
two 8-bit registers:
• PSMC Phase Count Low Byte (PSMCxPHL)
register (Register 24-32)
• PSMC Phase Count High Byte (PSMCxPHH)
register (Register 24-32)
The 16-bit phase value is double-buffered before it is
presented to the 16-bit PSMCxTMR for comparison.
The buffered registers are updated on the first period
event Reset after the PSMCxLD bit of the PSMCxCON
register is set.
Period
PSMCxPR[15:0] 1+
F
psmc_clk
--------------------------------------------------=