Datasheet

 2011-2012 Microchip Technology Inc. Preliminary DS41579D-page 167
PIC16(L)F1782/3
18.4 Register Definitions: Op Amp Control
TABLE 18-1: SUMMARY OF REGISTERS ASSOCIATED WITH OP AMPS
REGISTER 18-1: OPAxCON: OPERATIONAL AMPLIFIERS (OPAx) CONTROL REGISTERS
R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0
OPAxEN OPAxSP — — — — OPAxCH<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 7
OPAxEN: Op Amp Enable bit
1 = Op amp is enabled
0 = Op amp is disabled and consumes no active power
bit 6
OPAxSP: Op Amp Speed/Power Select bit
1 = Comparator operates in high GBWP mode
0 = Comparator operates in low GBWP mode
bit 5-2
Unimplemented: Read as ‘0’
bit 1-0 OPAxCH<1:0>: Non-inverting Channel Selection bits
11 = Non-inverting input connects to FVR Buffer 2 output
10 = Non-inverting input connects to DAC_output
0x = Non-inverting input connects to OPAxIN+ pin
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
ANSELA ANSA7 — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 123
ANSELB
— — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 129
DACCON0 DACEN
— DACOE1 DACOE2 DACPSS<1:0> — DACNSS 172
DACCON1 DACR<7:0> 172
OPA1CON OPA1EN OPA1SP
— — — — OPA1PCH<1:0> 167
OPA2CON OPA2EN OPA2SP
— — — — OPA2PCH<1:0> 167
TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 122
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 128
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 133
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by op amps.