Datasheet

PIC16(L)F1782/3
DS41579D-page 142 Preliminary  2011-2012 Microchip Technology Inc.
TABLE 14-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE
REGISTER 14-3: IOCxF: INTERRUPT-ON-CHANGE FLAG REGISTER
R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
IOCxF7 IOCxF6 IOCxF5 IOCxF4 IOCxF3 IOCxF2 IOCxF1 IOCxF0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware
bit 7-0
IOCxF<7:0>: Interrupt-on-Change Flag bits
(1)
1 = An enabled change was detected on the associated pin.
Set when IOCxPx = 1 and a rising edge was detected RBx, or when IOCxNx = 1 and a falling edge
was detected on RBx.
0 = No change was detected, or the user cleared the detected change.
Note 1: For IOCEF register, bit 3 (IOCEF3) is the only implemented bit in the register.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 129
INTCON GIE PEIE
TMR0IE INTE IOCIE TMR0IF INTF IOCIF
84
IOCAF IOCAF7 IOCAF6 IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0
142
IOCAN IOCAN7 IOCAN6 IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0
141
IOCAP IOCAP7 IOCAP6 IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0
141
IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0
142
IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0
141
IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0
141
IOCCF IOCCF7 IOCCF6 IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0
142
IOCCN IOCCN7 IOCCN6 IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0
141
IOCCP IOCCP7 IOCCP6 IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0
141
IOCEF
— — — —IOCEF3— — —
142
IOCEN
— — — —IOCEN3— — —
141
IOCEP
— — — — IOCEP3 — — —
141
TRISB
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
128
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupt-on-change.