PIC16(L)F1782/3 28-Pin 8-Bit Advanced Analog Flash Microcontroller High-Performance RISC CPU: • Only 49 Instructions • Operating Speed: - DC – 32 MHz clock input - DC – 125 ns instruction cycle • Interrupt Capability with Automatic Context Saving • 16-Level Deep Hardware Stack with optional Overflow/Underflow Reset • Direct, Indirect and Relative Addressing modes: • Two full 16-bit File Select Registers (FSRs) - FSRs can read program and data memory Memory Features: • Up to 4 KW Flash Program Memory: - Sel
PIC16(L)F1782/3 Digital Peripheral Features: General Microcontroller Features: • Timer0: 8-Bit Timer/Counter with 8-Bit Programmable Prescaler • Enhanced Timer1: - 16-bit timer/counter with prescaler - External Gate Input mode - Dedicated low-power 32 kHz oscillator driver • Timer2: 8-Bit Timer/Counter with 8-Bit Period Register, Prescaler and Postscaler • Two Capture/Compare/PWM modules (CCP): - 16-bit capture, maximum resolution 12.5 ns - 16-bit compare, max resolution 31.
PIC16(L)F1782/3 PIC16(L)F1782 (1) 2048 256 256 25 11 3 2 1/0 2/1 2 2 1 1 I PIC16(L)F1783 (1) 4096 256 512 25 11 3 2 1/0 2/1 2 2 1 1 I PIC16(L)F1784 (2) 4096 256 512 36 14 4 3 1/0 2/1 3 3 1 1 I PIC16(L)F1786 (2) 8192 256 1024 25 11 4 2 1/0 2/1 3 3 1 1 I PIC16(L)F1787 (2) 8192 256 1024 36 14 4 3 1/0 2/1 3 3 1 1 I PIC16(L)F1788 (3) 16384 256 2048 25 11 4 2 1/3 2/1 4 3 1 1 I PIC16(L)F1789 (3) 16384 256 2048 36 14 4 3 1/3 2/1 4 3 1 1 I Note 1: I - Debugging, Integrated on Chip; H - Debugging, available using De
PIC16(L)F1782/3 FIGURE 1: 28-PIN DIAGRAM FOR PIC16(L)F1782/3 SPDIP, SOIC, SSOP 1 28 RB7/ICSPDAT RA0 RA1 2 27 3 RB6/ICSPCLK RB5 RA2 4 RA3 RA4 RA5 VSS RA7 5 26 25 24 23 RA6 RC0 RC1 RC2 RC3 Note: 6 7 8 9 10 11 PIC16(L)F1782/3 VPP/MCLR/RE3 RB4 RB3 RB2 RB1 RB0 VDD 22 21 20 19 12 18 17 13 16 VSS RC7 RC6 RC5 14 15 RC4 See Table 1 for the location of all peripheral functions.
PIC16(L)F1782/3 28-Pin QFN, UQFN ADC ADC Reference Operation Amplifiers 8-bit DAC Timers PSMC CCP EUSART MSSP Interrupt Pull-up Basic RA0 2 27 AN0 — C1IN0C2IN0C3IN0- — — — — — — — IOC Y — RA1 3 28 AN1 — C1IN1C2IN1C3IN1- OPA1OUT — — — — — — IOC Y — RA2 4 1 AN2 VREF- C1IN0+ C2IN0+ C3IN0+ — DACOUT1 DACVREF- — — — — — IOC Y — RA3 5 2 AN3 VREF+ C1IN1+ — DACVREF+ — — — — — IOC Y — RA4 6 3 — — C1OUT OPA1IN+ — T0CKI — — — — I
PIC16(L)F1782/3 Table of Contents 1.0 Device Overview ......................................................................................................................................................................... 9 2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 15 3.0 Memory Organization ...............................................................................
PIC16(L)F1782/3 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@mail.
PIC16(L)F1782/3 NOTES: DS41579D-page 8 Preliminary 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 DEVICE OVERVIEW Reference Table 1-1 for peripherals available per device. TABLE 1-1: DEVICE PERIPHERAL SUMMARY Peripheral PIC16(L)F1783 The PIC16(L)F1782/3 are described within this data sheet. They are available in 28-pin packages. Figure 1-1 shows a block diagram of the PIC16(L)F1782/3 devices. Table 1-2 shows the pinout descriptions. PIC16(L)F1782 1.
PIC16(L)F1782/3 FIGURE 1-1: PIC16(L)F1782/3 BLOCK DIAGRAM Program Flash Memory RAM PORTA PORTB CLKOUT Timing Generation HFINTOSC/ LFINTOSC Oscillator CLKIN CPU PORTC Figure 2-2 PORTE MCLR Op Amps PSMCs Temp. Indicator Note DS41579D-page 10 1: Timer0 ADC 12-Bit Timer1 FVR Timer2 DAC MSSP CCPs Comparators EUSART See applicable chapters for more information on peripherals. Preliminary 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 TABLE 1-2: PIC16(L)F1782/3 PINOUT DESCRIPTION Name Function RA0/AN0/C1IN0-/C2IN0-/C3IN0- RA0 RA1/AN1/C1IN1-/C2IN1-/ C3IN1-/OPA1OUT RA4/C1OUT/OPA1IN+/T0CKI RA5/AN4/C2OUT(1)/OP1INA-/ SS RA6/C2OUT/OSC2/CLKOUT Description TTL/ST CMOS General purpose I/O. AN — A/D Channel 0 input. C1IN0- AN — Comparator C1 negative input. C2IN0- AN — Comparator C2 negative input. C3IN0- AN — Comparator C3 negative input. RA1 TTL/ST CMOS General purpose I/O.
PIC16(L)F1782/3 TABLE 1-2: PIC16(L)F1782/3 PINOUT DESCRIPTION (CONTINUED) Name RA7/VREF+(1)/PSMC1CLK/ PSMC2CLK/OSC1/CLKIN RB0/AN12/C2IN1+/PSMC1IN/ PSMC2IN/CCP1(1)/INT RB1/AN10/C1IN3-/C2IN3-/ C3IN3-/OPA2OUT RB2/AN8/OPA2IN-/CLKR RB3/AN9/C1IN2-/C2IN2-/ C3IN2-/OPA2IN+/CCP2(1) Function RA7 RB5/AN13/C3OUT/T1G/SDO(1) Output Type Description TTL/ST CMOS General purpose I/O. VREF+ AN — A/D Voltage Reference input. PSMC1CLK ST — PSMC1 clock input. PSMC2CLK ST — PSMC2 clock input.
PIC16(L)F1782/3 TABLE 1-2: PIC16(L)F1782/3 PINOUT DESCRIPTION (CONTINUED) Name RB6/TX(1)/CK(1)/SDI(1)/SDA(1)/ ICSPCLK Function RB6 RC0/T1OSO/T1CKI/PSMC1A RC1/T1OSI/PSMC1B/CCP2(1) RC2/PSMC1C/CCP1(1) RC3/PSMC1D/SCK(1)/SCL(1) RC4/PSMC1E/SDI(1)/SDA(1) RC5/PSMC1F/SDO(1) RC6/PSMC2A/TX(1)/CK(1) Description TTL/ST CMOS General purpose I/O. TX — CMOS USART asynchronous transmit. ST CMOS USART synchronous clock. SDI ST — SPI data input. SDA I2C OD I2C™ data input/output.
PIC16(L)F1782/3 TABLE 1-2: PIC16(L)F1782/3 PINOUT DESCRIPTION (CONTINUED) Name RE3/MCLR/VPP Function Input Type Output Type RE3 TTL/ST — Description General purpose input. MCLR ST — Master Clear with internal pull-up. VPP HV — Programming voltage. VDD VDD Power — Positive supply. VSS VSS Power — Ground reference.
PIC16(L)F1782/3 2.0 ENHANCED MID-RANGE CPU Relative addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory. This family of devices contain an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability.
PIC16(L)F1782/3 2.1 Automatic Interrupt Context Saving During interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. This saves stack space and user code. See 8.5 “Automatic Context Saving”, for more information. 2.2 16-level Stack with Overflow and Underflow These devices have an external stack memory 15 bits wide and 16 words deep.
PIC16(L)F1782/3 FIGURE 2-2: CORE BLOCK DIAGRAM 15 Configuration 15 MUX Flash Program Memory Program Bus 16-Level 8 Level Stack Stack (13-bit) (15-bit) 14 Instruction Instruction Reg reg 8 Data Bus Program Counter RAM Program Memory Read (PMR) 12 RAM Addr Addr MUX Direct Addr 7 5 Indirect Addr 12 12 BSR FSR Reg reg 15 FSR0reg Reg FSR FSR1 Reg FSR reg 15 STATUS Reg reg STATUS 8 3 Power-up Timer OSC1/CLKIN OSC2/CLKOUT Instruction Decodeand & Decode Control Timing Generation Oscilla
PIC16(L)F1782/3 NOTES: DS41579D-page 18 Preliminary 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 3.0 MEMORY ORGANIZATION These devices contain the following types of memory: • Program Memory - Configuration Words - Device ID - User ID - Flash Program Memory • Data Memory - Core Registers - Special Function Registers - General Purpose RAM - Common RAM • Data EEPROM memory(1) The following features are associated with access and control of program memory and data memory: • PCL and PCLATH • Stack • Indirect Addressing 3.
PIC16(L)F1782/3 FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR PIC16(L)F1782 FIGURE 3-2: PC<14:0> CALL, CALLW RETURN, RETLW Interrupt, RETFIE On-chip Program Memory PROGRAM MEMORY MAP AND STACK FOR PIC16(L)F1783 PC<14:0> CALL, CALLW RETURN, RETLW Interrupt, RETFIE 15 15 Stack Level 0 Stack Level 1 Stack Level 0 Stack Level 1 Stack Level 15 Stack Level 15 Reset Vector 0000h Reset Vector 0000h Interrupt Vector 0004h 0005h Interrupt Vector 0004h 0005h Page 0 Rollover to Page 0 Wraps to Page
PIC16(L)F1782/3 3.1.1 READING PROGRAM MEMORY AS DATA There are two methods of accessing constants in program memory. The first method is to use tables of RETLW instructions. The second method is to set an FSR to point to the program memory. 3.1.1.1 RETLW Instruction The RETLW instruction can be used to provide access to tables of constants. The recommended way to create such a table is shown in Example 3-1.
PIC16(L)F1782/3 3.2 Data Memory Organization 3.2.1 The data memory is partitioned in 32 memory banks with 128 bytes in a bank. Each bank consists of (Figure 3-3): • • • • 12 core registers 20 Special Function Registers (SFR) Up to 80 bytes of General Purpose RAM (GPR) 16 bytes of common RAM The core registers contain the registers that directly affect the basic operation. The core registers occupy the first 12 addresses of every data memory bank (addresses x00h/x08h through x0Bh/x8Bh).
PIC16(L)F1782/3 3.2.1.1 STATUS Register The STATUS register, shown in Register 3-1, contains: • the arithmetic status of the ALU • the Reset status The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable.
PIC16(L)F1782/3 3.3.1 SPECIAL FUNCTION REGISTER FIGURE 3-3: The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). The registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet. 3.3.
2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 MEMORY MAP (BANKS 8-31) BANK 8 400h 40Bh 40Ch Core Registers (Table 3-2) BANK 9 480h 48Bh 48Ch Unimplemented Read as ‘0’ Core Registers (Table 3-2) Unimplemented Read as ‘0’ BANK 10 500h 50Bh 50Ch 510h 511h 512h 513h 514h 519h 51Ah 51Bh 46Fh 470h Preliminary 47Fh Common RAM (Accesses 70h – 7Fh) 4EFh 4F0h 4FFh BANK 16 800h 80Bh 80Ch Core Registers (Table 3-2) 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 TABLE 3-5: PIC16(L)F1782/3 MEMORY MAP (BANK 16 DETAILS) BANK 16 811h 812h 813h 814h 815h 816h 817h 818h 819h 81Ah 81Bh 81Ch 81Dh 81Eh 81Fh 820h 821h 822h 823h 824h 825h 826h 827h 828h 829h 82Ah 82Bh 82Ch 82Dh 82Eh 82Fh 830h PSMC1CON PSMC1MDL PSMC1SYNC PSMC1CLK PSMC1OEN PSMC1POL PSMC1BLNK PSMC1REBS PSMC1FEBS PSMC1PHS PSMC1DCS PSMC1PRS PSMC1ASDC PSMC1ASDD PSMC1ASDS PSMC1INT PSMC1PHL PSMC1PHH PSMC1DCL PSMC1DCH PSMC1PRL PSMC1PRH PSMC1TMRL PSMC1TMRH PSMC1DBR PSMC1DBF PSMC1BLKR PSMC1BLKF PSMC1F
PIC16(L)F1782/3 3.3.5 CORE FUNCTION REGISTERS SUMMARY The Core Function registers listed in Table 3-7 can be addressed from any Bank.
PIC16(L)F1782/3 TABLE 3-8: Addr Name SPECIAL FUNCTION REGISTER SUMMARY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 0 00Ch PORTA PORTA Data Latch when written: PORTA pins when read xxxx xxxx uuuu uuuu 00Dh PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 00Eh PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu 00Fh — Unimplemented 010h PORTE 011h PIR1 012h PIR2 013h — — — —
PIC16(L)F1782/3 TABLE 3-8: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 2 10Ch LATA PORTA Data Latch xxxx xxxx uuuu uuuu 10Dh LATB PORTB Data Latch xxxx xxxx uuuu uuuu 10Eh LATC PORTC Data Latch xxxx xxxx uuuu uuuu 10Fh — Unimplemented — — 110h — Unimplemented — — 111h CM1CON0 C1ON C1OUT 112h CM1CON1 C1INTP C1INTN 113h CM2CON0 C2ON C2OUT 114h CM2CON1 C2INTP
PIC16(L)F1782/3 TABLE 3-8: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 4 20Ch WPUA WPUA7 WPUA6 WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 1111 1111 1111 1111 20Dh WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 1111 20Eh WPUC WPUC7 WPUC6 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 1111 1111 1111 1111 — — — WPUE3 — — — ---- 1--- ---- 1--- 20Fh —
PIC16(L)F1782/3 TABLE 3-8: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 7 38Ch INLVLA Input Type Control for PORTA 0000 0000 0000 0000 38Dh INLVLB Input Type Control for PORTB 0000 0000 0000 0000 38Eh INLVLC Input Type Control for PORTC 1111 1111 1111 1111 38Fh — Unimplemented 390h INLVLE — — — — — INLVLE3 — — — — ---- 1--- ---- 1--- 391h IOCAP IOCAP<7:0> 0000 0000
PIC16(L)F1782/3 TABLE 3-8: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets — — Bank 16 80Ch — — 810h 811h Unimplemented PSMC1CON PSMC1EN PSMC1LD PSMC1DBFE PSMC1DBRE P1MODE<3:0> 0000 0000 0000 0000 812h PSMC1MDL P1MDLEN P1MDLPOL P1MDLBIT — P1MSRC<3:0> 000- 0000 000- 0000 813h PSMC1SYNC — — — — 814h PSMC1CLK — — 815h PSMC1OEN — — P1OEF 816h PSMC1POL — P1INPOL P1POLF 8
PIC16(L)F1782/3 TABLE 3-8: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 16 (Continued) 831h PSMC2CON PSMC2EN PSMC2LD PSMC2DBFE PSMC2DBRE P2MODE<3:0> 0000 0000 0000 0000 832h PSMC2MDL P2MDLEN P2MDLPOL P2MDLBIT — P2MSRC<3:0> 000- 0000 000- 0000 833h PSMC2SYNC — — — — 834h PSMC2CLK — — 835h PSMC2OEN — — — 836h PSMC2POL — P2INPOL — 837h PSMC2BLNK — — 838h PSMC2RE
PIC16(L)F1782/3 TABLE 3-8: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets — — Bank 31 F8Ch to — FE3h Unimplemented FE4h STATUS_ SHAD — — — — — Z DC FE5h WREG_SHAD Working Register Shadow FE6h BSR_SHAD — FE7h PCLATH_ SHAD — — C ---- -xxx ---- -uuu xxxx xxxx uuuu uuuu — Bank Select Register Shadow Program Counter Latch High Register Shadow ---x xxxx ---u uuuu -xxx xxxx uuuu uu
PIC16(L)F1782/3 3.4 PCL and PCLATH 3.4.3 COMPUTED FUNCTION CALLS The Program Counter (PC) is 15 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<14:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 3-4 shows the five situations for the loading of the PC.
PIC16(L)F1782/3 3.5 Stack 3.5.1 The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack. Both registers are read/writable. TOS is split into TOSH and TOSL due to the 15-bit size of the PC. To access the stack, adjust the value of STKPTR, which will position TOSH:TOSL, then read/write to TOSH:TOSL. STKPTR is 5 bits to allow detection of overflow and underflow.
PIC16(L)F1782/3 FIGURE 3-6: ACCESSING THE STACK EXAMPLE 2 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 This figure shows the stack configuration after the first CALL or a single interrupt. If a RETURN instruction is executed, the return address will be placed in the Program Counter and the Stack Pointer decremented to the empty state (0x1F).
PIC16(L)F1782/3 FIGURE 3-8: ACCESSING THE STACK EXAMPLE 4 TOSH:TOSL 3.5.
PIC16(L)F1782/3 FIGURE 3-9: INDIRECT ADDRESSING 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory 0x29AF 0x29B0 FSR Address Range Reserved 0x7FFF 0x8000 0x0000 Program Flash Memory 0xFFFF Note: 0x7FFF Not all memory regions are completely implemented. Consult device memory tables for memory limits. DS41579D-page 40 Preliminary 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 3.6.1 TRADITIONAL DATA MEMORY The traditional data memory is a region from FSR address 0x000 to FSR address 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers.
PIC16(L)F1782/3 3.6.2 3.6.3 LINEAR DATA MEMORY The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the banks. Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the FSR beyond one bank will go directly to the GPR memory of the next bank.
PIC16(L)F1782/3 4.0 DEVICE CONFIGURATION Device configuration consists of Configuration Words, Code Protection and Device ID. 4.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h. Note: The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers and programmers.
PIC16(L)F1782/3 4.
PIC16(L)F1782/3 REGISTER 4-1: bit 2-0 Note 1: CONFIG1: CONFIGURATION WORD 1 (CONTINUED) FOSC<2:0>: Oscillator Selection bits 111 = ECH: External Clock, High-Power mode (4-20 MHz): device clock supplied to CLKIN pin 110 = ECM: External Clock, Medium-Power mode (0.5-4 MHz): device clock supplied to CLKIN pin 101 = ECL: External Clock, Low-Power mode (0-0.
PIC16(L)F1782/3 REGISTER 4-2: CONFIG2: CONFIGURATION WORD 2 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 LVP DEBUG LPBOR BORV STVREN PLLEN bit 13 bit 8 U-1 U-1 R/P-1 U-1 U-1 U-1 — — VCAPEN — — — R/P-1 R/P-1 WRT<1:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase bit 13 LVP: Low-Voltage Programming Enable bit(1) 1 = Low-voltage programming enabled 0 = Hig
PIC16(L)F1782/3 4.3 Code Protection Code protection allows the device to be protected from unauthorized access. Program memory protection and data EEPROM protection are controlled independently. Internal access to the program memory and data EEPROM are unaffected by any code protection setting. 4.3.1 PROGRAM MEMORY PROTECTION The entire program memory space is protected from external reads and writes by the CP bit in Configuration Words.
PIC16(L)F1782/3 4.6 Device ID and Revision ID The memory location 8006h is where the Device ID and Revision ID are stored. The upper nine bits hold the Device ID. The lower five bits hold the Revision ID. See Section 12.5 “User ID, Device ID and Configuration Word Access” for more information on accessing these memory locations. Development tools, such as device programmers and debuggers, may be used to read the Device ID and Revision ID. 4.
PIC16(L)F1782/3 5.0 RESETS A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 5-1. There are multiple ways to reset this device: • • • • • • • • • Power-On Reset (POR) Brown-Out Reset (BOR) Low-Power Brown-Out Reset (LPBOR) MCLR Reset WDT Reset RESET instruction Stack Overflow Stack Underflow Programming mode exit To allow VDD to stabilize, an optional Power-up Timer can be enabled to extend the Reset time after a BOR or POR event.
PIC16(L)F1782/3 5.1 Power-On Reset (POR) 5.2 Brown-Out Reset (BOR) The POR circuit holds the device in Reset until VDD has reached an acceptable level for minimum operation. Slow rising VDD, fast operating speeds or analog performance may require greater than minimum VDD. The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met. The BOR circuit holds the device in Reset when VDD reaches a selectable minimum level.
PIC16(L)F1782/3 FIGURE 5-2: BROWN-OUT SITUATIONS VDD VBOR Internal Reset TPWRT(1) VDD VBOR Internal Reset < TPWRT TPWRT(1) VDD VBOR Internal Reset Note 1: 5.3 TPWRT(1) TPWRT delay only if PWRTE bit is programmed to ‘0’.
PIC16(L)F1782/3 5.4 Low-Power Brown-Out Reset (LPBOR) 5.6 The Low-Power Brown-Out Reset (LPBOR) is an essential part of the Reset subsystem. Refer to Figure 5-1 to see how the BOR interacts with other modules. The LPBOR is used to monitor the external VDD pin. When too low of a voltage is detected, the device is held in Reset. When this occurs, a register bit (BOR) is changed to indicate that a BOR Reset has occurred. The same bit is set for both the BOR and the LPBOR. Refer to Register 5-2. 5.4.
PIC16(L)F1782/3 FIGURE 5-3: RESET START-UP SEQUENCE VDD Internal POR TPWRT Power-up Timer MCLR TMCLR Internal RESET Oscillator Modes External Crystal TOST Oscillator Start-up Timer Oscillator FOSC Internal Oscillator Oscillator FOSC External Clock (EC) CLKIN FOSC 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 5.12 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON register are updated to indicate the cause of the Reset. Table 5-3 and Table 5-4 show the Reset conditions of these registers.
PIC16(L)F1782/3 5.13 Power Control (PCON) Register The PCON register bits are shown in Register 5-2. The Power Control (PCON) register contains flag bits to differentiate between a: • • • • • • • Power-on Reset (POR) Brown-out Reset (BOR) Reset Instruction Reset (RI) MCLR Reset (RMCLR) Watchdog Timer Reset (RWDT) Stack Underflow Reset (STKUNF) Stack Overflow Reset (STKOVF) 5.
PIC16(L)F1782/3 TABLE 5-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BORCON SBOREN BORFS — — — — — BORRDY 51 PCON STKOVF STKUNF — RWDT RMCLR RI POR BOR 55 STATUS — — — TO PD Z DC C 23 WDTCON — — SWDTEN 101 WDTPS<4:0> Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets. DS41579D-page 56 Preliminary 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 6.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR) 6.1 Overview The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 6-1 illustrates a block diagram of the oscillator module. Clock sources can be supplied from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits.
PIC16(L)F1782/3 SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM FIGURE 6-1: Oscillator Timer1 Timer1 Clock Source Option for other modules T1OSO T1OSCEN Enable Oscillator T1OSI T1OSC 01 External Oscillator LP, XT, HS, RC, EC OSC2 0 Sleep PRIMUX OSC1 PSMCMUX 0 ÷2 4 x PLL 1 500 kHz Source 16 MHz (HFINTOSC) Postscaler Internal Oscillator Block 500 kHz (MFINTOSC) 31 kHz Source 31 kHz FOSC<2:0> =100 =00 ≠100 ≠00 XXX 1X SCS<1:0> PSMC 64 MHz 0000 WDT, PWRT, Fail-Safe Clock Monitor Two
PIC16(L)F1782/3 6.2 Clock Source Types Clock sources can be classified as external or internal. External clock sources rely on external circuitry for the clock source to function. Examples are: oscillator modules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC) mode circuits. Internal clock sources are contained within the oscillator module.
PIC16(L)F1782/3 FIGURE 6-3: QUARTZ CRYSTAL OPERATION (LP, XT OR HS MODE) FIGURE 6-4: CERAMIC RESONATOR OPERATION (XT OR HS MODE) PIC® MCU PIC® MCU OSC1/CLKIN C1 C1 To Internal Logic Quartz Crystal C2 OSC1/CLKIN RS(1) RF(2) Sleep RP(3) OSC2/CLKOUT C2 Ceramic RS(1) Resonator Note 1: A series resistor (RS) may be required for quartz crystals with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M.
PIC16(L)F1782/3 6.2.1.4 4x PLL The oscillator module contains a 4x PLL that can be used with both external and internal clock sources to provide a system clock source. The input frequency for the 4x PLL must fall within specifications. See the PLL Clock Timing Specifications in Section 30.0 “Electrical Specifications”. Note 1: Quartz crystal characteristics vary according to type, package and manufacturer.
PIC16(L)F1782/3 6.2.1.6 External RC Mode 6.2.2 The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. The RC circuit connects to OSC1. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. The function of the OSC2/CLKOUT pin is determined by the CLKOUTEN bit in Configuration Words. Figure 6-6 shows the external RC mode connections.
PIC16(L)F1782/3 6.2.2.1 HFINTOSC 6.2.2.3 The High-Frequency Internal Oscillator (HFINTOSC) is a factory calibrated 16 MHz internal clock source. The frequency of the HFINTOSC can be altered via software using the OSCTUNE register (Register 6-3). The output of the HFINTOSC connects to a postscaler and multiplexer (see Figure 6-1). One of multiple frequencies derived from the HFINTOSC can be selected via software using the IRCF<3:0> bits of the OSCCON register. See Section 6.2.2.
PIC16(L)F1782/3 6.2.2.5 Internal Oscillator Frequency Selection 6.2.2.6 The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register. The output of the 16 MHz HFINTOSC, 500 kHz MFINTOSC, and 31 kHz LFINTOSC connects to a postscaler and multiplexer (see Figure 6-1). The Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register select the frequency output of the internal oscillators.
PIC16(L)F1782/3 6.2.2.7 Internal Oscillator Clock Switch Timing When switching between the HFINTOSC, MFINTOSC and the LFINTOSC, the new oscillator may already be shut down to save power (see Figure 6-7). If this is the case, there is a delay after the IRCF<3:0> bits of the OSCCON register are modified before the frequency selection takes place. The OSCSTAT register will reflect the current active status of the HFINTOSC, MFINTOSC and LFINTOSC oscillators.
PIC16(L)F1782/3 FIGURE 6-7: HFINTOSC/ MFINTOSC INTERNAL OSCILLATOR SWITCH TIMING LFINTOSC (FSCM and WDT disabled) HFINTOSC/ MFINTOSC Start-up Time 2-cycle Sync Running LFINTOSC IRCF <3:0> 0 0 System Clock HFINTOSC/ MFINTOSC LFINTOSC (Either FSCM or WDT enabled) HFINTOSC/ MFINTOSC 2-cycle Sync Running LFINTOSC 0 IRCF <3:0> 0 System Clock LFINTOSC HFINTOSC/MFINTOSC LFINTOSC turns off unless WDT or FSCM is enabled LFINTOSC Start-up Time 2-cycle Sync Running HFINTOSC/ MFINTOS
PIC16(L)F1782/3 6.3 Clock Switching 6.3.3 TIMER1 OSCILLATOR The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bits of the OSCCON register. The following clock sources can be selected using the SCS bits: The Timer1 oscillator is a separate crystal oscillator associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the T1OSO and T1OSI device pins.
PIC16(L)F1782/3 6.4 Two-Speed Clock Start-up Mode 6.4.1 Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device.
PIC16(L)F1782/3 6.4.2 1. 2. 3. 4. 5. 6. 7. TWO-SPEED START-UP SEQUENCE 6.4.3 Wake-up from Power-on Reset or Sleep. Instructions begin execution by the internal oscillator at the frequency set in the IRCF<3:0> bits of the OSCCON register. OST enabled to count 1024 clock cycles. OST timed out, wait for falling edge of the internal oscillator. OSTS is set. System clock held low until the next falling edge of new clock (LP, XT or HS mode). System clock is switched to external clock source.
PIC16(L)F1782/3 6.5 Fail-Safe Clock Monitor 6.5.3 The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the Configuration Words. The FSCM is applicable to all external Oscillator modes (LP, XT, HS, EC, Timer1 Oscillator and RC).
PIC16(L)F1782/3 FIGURE 6-10: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure System Clock Output Clock Monitor Output (Q) Failure Detected OSCFIF Test Note: Test Test The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 6.
PIC16(L)F1782/3 REGISTER 6-2: OSCSTAT: OSCILLATOR STATUS REGISTER R-1/q R-0/q R-q/q R-0/q R-0/q R-q/q R-0/0 R-0/q T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Conditional bit 7 T1OSCR: Timer1 Oscillator Ready bit If T1OSCEN = 1: 1 = Timer1 oscillator
PIC16(L)F1782/3 REGISTER 6-3: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 U-0 — — R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TUN<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: Frequency Tuning bits 100000 = Minimum frequency • • • 111111 = 000000 = Osci
PIC16(L)F1782/3 7.0 REFERENCE CLOCK MODULE The reference clock module provides the ability to send a divided clock to the clock output pin of the device (CLKR). This module is available in all oscillator configurations and allows the user to select a greater range of clock submultiples to drive external devices in the application.
PIC16(L)F1782/3 7.
PIC16(L)F1782/3 TABLE 7-1: SUMMARY OF REGISTERS ASSOCIATED WITH REFERENCE CLOCK SOURCES Name CLKRCON Legend: Bit 7 Bit 6 Bit 5 CLKREN CLKROE CLKRSLR CONFIG1 Legend: Bit 3 CLKRDC<1:0> Bit 2 Bit 1 Bit 0 CLKRDIV<2:0> Register on Page 76 — = unimplemented locations read as ‘0’. Shaded cells are not used by reference clock sources.
PIC16(L)F1782/3 NOTES: DS41579D-page 78 Preliminary 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 8.0 INTERRUPTS The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode. This chapter contains the following information for Interrupts: • • • • • Operation Interrupt Latency Interrupts During Sleep INT Pin Automatic Context Saving Many peripherals produce interrupts. Refer to the corresponding chapters for details.
PIC16(L)F1782/3 8.1 Operation 8.2 Interrupts are disabled upon any device Reset.
PIC16(L)F1782/3 FIGURE 8-2: INTERRUPT LATENCY OSC1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKR Interrupt Sampled during Q1 Interrupt GIE PC Execute PC-1 PC 1 Cycle Instruction at PC PC+1 0004h 0005h NOP NOP Inst(0004h) PC+1/FSR ADDR New PC/ PC+1 0004h 0005h Inst(PC) NOP NOP Inst(0004h) FSR ADDR PC+1 PC+2 0004h 0005h INST(PC) NOP NOP NOP Inst(0004h) Inst(0005h) FSR ADDR PC+1 0004h 0005h INST(PC) NOP NOP Inst(00
PIC16(L)F1782/3 FIGURE 8-3: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT (3) (4) INT pin (1) (1) INTF Interrupt Latency (2) (5) GIE INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: PC Inst (PC) Inst (PC – 1) PC + 1 Inst (PC + 1) PC + 1 — Forced NOP Inst (PC) 0004h Inst (0004h) Forced NOP 0005h Inst (0005h) Inst (0004h) INTF flag is sampled here (every Q1).
PIC16(L)F1782/3 8.3 Interrupts During Sleep Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction.
PIC16(L)F1782/3 8.
PIC16(L)F1782/3 REGISTER 8-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit 1 = Enables the Timer1 ga
PIC16(L)F1782/3 REGISTER 8-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 OSFIE C2IE C1IE EEIE BCLIE — C3IE CCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSFIE: Oscillator Fail Interrupt Enable bit 1 = Enables the Oscillator Fail inte
PIC16(L)F1782/3 REGISTER 8-4: PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4 U-0 U-0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 — — PSMC2TIE PSMC1TIE — — PSMC2SIE PSMC1SIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5 PSMC2TIE: PSMC2 Time Base Interrupt Enable bit 1 = E
PIC16(L)F1782/3 REGISTER 8-5: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit 1 = Interrupt is pending 0 = I
PIC16(L)F1782/3 REGISTER 8-6: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 OSFIF C2IF C1IF EEIF BCLIF — C3IF CCP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSFIF: Oscillator Fail Interrupt Flag bit 1 = Interrupt is pending 0 = Interrup
PIC16(L)F1782/3 REGISTER 8-7: PIR4: PERIPHERAL INTERRUPT REQUEST REGISTER42 U-0 U-0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 — — PSMC2TIF PSMC1TIF — — PSMC2SIF PSMC1SIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5 PSMC2TIF: PSMC2 Time Base Interrupt Flag bit 1 = In
PIC16(L)F1782/3 TABLE 8-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Bit 7 INTCON Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 TMR0IF Bit 1 Bit 0 INTF IOCIF Register on Page GIE PEIE TMR0IE INTE IOCIE WPUEN INTEDG TMR0CS TMR0SE PSA PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IFE TMR1IE 85 PIE2 OSFIE C2IE C1IE EEIE BCL1IE — C3IE CCP2IE 86 PIE4 — — — — PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 88 PIR2 OSFIF C2IF C1IF EEIF BCL1IF — C
PIC16(L)F1782/3 NOTES: DS41579D-page 92 Preliminary 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 9.0 POWER-DOWN MODE (SLEEP) 9.1 Wake-up from Sleep The Power-down mode is entered by executing a SLEEP instruction. The device can wake-up from Sleep through one of the following events: Upon entering Sleep mode, the following conditions exist: 1. 2. 3. 4. 5. 6. 1. 2. 3. 4. 5. 6. 7. 8. 9. WDT will be cleared but keeps running, if enabled for operation during Sleep. PD bit of the STATUS register is cleared. TO bit of the STATUS register is set. CPU clock is disabled.
PIC16(L)F1782/3 9.1.1 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: • If the interrupt occurs before the execution of a SLEEP instruction - SLEEP instruction will execute as a NOP. - WDT and WDT prescaler will not be cleared - TO bit of the STATUS register will not be set - PD bit of the STATUS register will not be cleared.
PIC16(L)F1782/3 9.2 Low-Power Sleep Mode 9.2.2 The PIC16(L)F1783 device contains an internal Low Dropout (LDO) voltage regulator, which allows the device I/O pins to operate at voltages up to 5.5V while the internal device logic operates at a lower voltage. The LDO and its associated reference circuitry must remain active when the device is in Sleep mode. The PIC16(L)F1783 allows the user to optimize the operating current in Sleep, depending on the application requirements.
PIC16(L)F1782/3 9.
PIC16(L)F1782/3 10.0 LOW DROPOUT (LDO) VOLTAGE REGULATOR On power-up, the external capacitor will load the LDO voltage regulator. To prevent erroneous operation, the device is held in Reset while a constant current source charges the external capacitor. After the cap is fully charged, the device is released from Reset. For more information on the constant current rate, refer to the LDO Regulator Characteristics Table in Section 30.0 “Electrical Specifications”.
PIC16(L)F1782/3 NOTES: DS41579D-page 98 Preliminary 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 11.0 WATCHDOG TIMER (WDT) The Watchdog Timer is a system timer that generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The Watchdog Timer is typically used to recover the system from unexpected events.
PIC16(L)F1782/3 11.1 Independent Clock Source 11.3 The WDT derives its time base from the 31 kHz LFINTOSC internal oscillator. Time intervals in this chapter are based on a nominal interval of 1 ms. See Section 30.0 “Electrical Specifications” for the LFINTOSC tolerances. 11.2 The Watchdog Timer module has four operating modes controlled by the WDTE<1:0> bits in Configuration Words. See Table 11-1. 11.2.
PIC16(L)F1782/3 11.
PIC16(L)F1782/3 TABLE 11-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER Bit 7 Bit 6 OSCCON SPLLEN STATUS — — WDTCON — — Bit 5 Bit 4 Bit 3 IRCF<3:0> — Bit 2 Bit 1 — TO PD Bit 0 SCS<1:0> Z DC WDTPS<4:0> Register on Page 72 C 23 SWDTEN 101 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Watchdog Timer.
PIC16(L)F1782/3 12.0 DATA EEPROM AND FLASH PROGRAM MEMORY CONTROL 12.1 The data EEPROM and Flash program memory are readable and writable during normal operation (full VDD range). These memories are not directly mapped in the register file space. Instead, they are indirectly addressed through the Special Function Registers (SFRs).
PIC16(L)F1782/3 12.2 Using the Data EEPROM 12.2.2 The data EEPROM is a high-endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). When variables in one section change frequently, while variables in another section do not change, it is possible to exceed the total number of write cycles to the EEPROM without exceeding the total number of write cycles to a single byte. Refer to Section 30.
PIC16(L)F1782/3 Required Sequence EXAMPLE 12-2: DATA EEPROM WRITE BANKSEL MOVLW MOVWF MOVLW MOVWF BCF BCF BSF EEADRL DATA_EE_ADDR EEADRL DATA_EE_DATA EEDATL EECON1, CFGS EECON1, EEPGD EECON1, WREN ; ; ;Data Memory Address to write ; ;Data Memory Value to write ;Deselect Configuration space ;Point to DATA memory ;Enable writes BCF MOVLW MOVWF MOVLW MOVWF BSF BSF BCF BTFSC GOTO INTCON, 55h EECON2 0AAh EECON2 EECON1, INTCON, EECON1, EECON1, $-2 ;Disable INTs.
PIC16(L)F1782/3 12.3 Flash Program Memory Overview It is important to understand the Flash program memory structure for erase and programming operations. Flash program memory is arranged in rows. A row consists of a fixed number of 14-bit program memory words. A row is the minimum block size that can be erased by user software.
PIC16(L)F1782/3 EXAMPLE 12-3: FLASH PROGRAM MEMORY READ * This code block will read 1 word of program * memory at the memory address: PROG_ADDR_HI : PROG_ADDR_LO * data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL MOVLW MOVWF MOVLW MOVWL EEADRL PROG_ADDR_LO EEADRL PROG_ADDR_HI EEADRH ; Select Bank for EEPROM registers ; ; Store LSB of address ; ; Store MSB of address BCF BSF BCF BSF NOP NOP BSF EECON1,CFGS EECON1,EEPGD INTCON,GIE EECON1,RD INTCON,GIE ; ; ; ; ; ; ; Do not
PIC16(L)F1782/3 12.3.2 ERASING FLASH PROGRAM MEMORY While executing code, program memory can only be erased by rows. To erase a row: 1. 2. 3. 4. 5. 6. Load the EEADRH:EEADRL register pair with the address of new row to be erased. Clear the CFGS bit of the EECON1 register. Set the EEPGD, FREE, and WREN bits of the EECON1 register. Write 55h, then AAh, to EECON2 (Flash programming unlock sequence). Set control bit WR of the EECON1 register to begin the erase operation.
PIC16(L)F1782/3 FIGURE 12-2: BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES 7 5 0 0 7 EEDATH EEDATA 8 6 Last word of block to be written First word of block to be written 14 EEADRL<4:0> = 00000 14 EEADRL<4:0> = 00001 14 EEADRL<4:0> = 00010 Buffer Register Buffer Register 14 EEADRL<4:0> = 11111 Buffer Register Buffer Register Program Memory EXAMPLE 12-4: ERASING ONE ROW OF PROGRAM MEMORY Required Sequence ; This row erase routine assumes the following: ; 1.
PIC16(L)F1782/3 EXAMPLE 12-5: ; ; ; ; ; ; ; WRITING TO FLASH PROGRAM MEMORY This write routine assumes the following: 1. The 16 bytes of data are loaded, starting at the address in DATA_ADDR 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR, stored in little endian format 3. A valid starting address (the least significant bits = 000) is loaded in ADDRH:ADDRL 4.
PIC16(L)F1782/3 12.4 Modifying Flash Program Memory When modifying existing data in a program memory row, and data within that row must be preserved, it must first be read and saved in a RAM image. Program memory is modified using the following steps: 1. 2. 3. 4. 5. 6. 7. 8. Load the starting address of the row to be modified. Read the existing data from the row into a RAM image. Modify the RAM image to contain the new data to be written into program memory.
PIC16(L)F1782/3 12.6 Write Verify Depending on the application, good programming practice may dictate that the value written to the data EEPROM or program memory should be verified (see Example 12-6) to the desired value to be written. Example 12-6 shows how to verify a write to EEPROM.
PIC16(L)F1782/3 12.
PIC16(L)F1782/3 REGISTER 12-5: EECON1: EEPROM CONTROL 1 REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W/HC-0/0 R/W-x/q R/W-0/0 R/S/HC-0/0 R/S/HC-0/0 EEPGD CFGS LWLO FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 EEPGD: Flash Program/Data EEPROM Memory Sele
PIC16(L)F1782/3 REGISTER 12-6: W-0/0 EECON2: EEPROM CONTROL 2 REGISTER W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 EEPROM Control Register 2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Data EEPROM Unlock Pattern bits To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR b
PIC16(L)F1782/3 NOTES: DS41579D-page 116 Preliminary 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 13.0 I/O PORTS FIGURE 13-1: GENERIC I/O PORT OPERATION Each port has three standard registers for its operation. These registers are: • TRISx registers (data direction) • PORTx registers (reads the levels on the pins of the device) • LATx registers (output latch) Read LATx D Some ports may have one or more of the following additional registers.
PIC16(L)F1782/3 13.1 Alternate Pin Function The Alternate Pin Function Control (APFCON) register is used to steer specific peripheral input and output functions between different pins. The APFCON register is shown in Register 13-1. For this device family, the following functions can be moved between different pins. • • • • • • • C2OUT output CCP1 output SDO output SCL/SCK output SDA/SDI output TX/RX output CCP2 output These bits have no effect on the values of any TRIS register.
PIC16(L)F1782/3 13.
PIC16(L)F1782/3 13.3 13.3.1 PORTA Registers 13.3.5 DATA REGISTER PORTA is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 13-3). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin).
PIC16(L)F1782/3 13.3.7 PORTA FUNCTIONS AND OUTPUT PRIORITIES Each PORTA pin is multiplexed with other functions. The pins, their combined functions and their output priorities are shown in Table 13-2. When multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. Analog input functions, such as ADC, and comparator inputs, are not shown in the priority lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELx registers.
PIC16(L)F1782/3 13.
PIC16(L)F1782/3 REGISTER 13-5: ANSELA: PORTA ANALOG SELECT REGISTER R/W-1/1 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 ANSA7 — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 5 ANSA7: Analog Select between Analog or Digital Function on pins RA7, respectively 0
PIC16(L)F1782/3 REGISTER 13-7: ODCONA: PORTA OPEN DRAIN CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ODA7 ODA6 ODA5 ODA4 ODA3 ODA2 ODA1 ODA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ODA<7:0>: PORTA Open Drain Enable bits For RA<7:0> pins, respectively 1 = Por
PIC16(L)F1782/3 TABLE 13-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA ANSA7 — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 123 INLVLA INLVLA7 INLVLA6 INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 124 LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 122 ODA2 ODA1 ODA0 Name LATA ODCONA OPTION_REG PORTA SLRCONA ODA7 ODA6 ODA5 ODA4 ODA3 WPUEN INTEDG TMR0CS TMR0SE PSA 124 PS<2:0> 185 RA7 RA6
PIC16(L)F1782/3 13.5 PORTB Registers 13.5.4 PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB (Register 13-11). Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin).
PIC16(L)F1782/3 13.5.6 PORTB FUNCTIONS AND OUTPUT PRIORITIES Each PORTB pin is multiplexed with other functions. The pins, their combined functions and their output priorities are shown in Table 13-5. When multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. Analog input and some digital input functions are not included in the list below. These input functions can remain active when the pin is configured as an output.
PIC16(L)F1782/3 13.
PIC16(L)F1782/3 REGISTER 13-13: ANSELB: PORTB ANALOG SELECT REGISTER U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 ANSB<5:0>: Analog Select between Analog or Digital Fun
PIC16(L)F1782/3 REGISTER 13-15: ODCONB: PORTB OPEN DRAIN CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ODB7 ODB6 ODB5 ODB4 ODB3 ODB2 ODB1 ODB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ODB<7:0>: PORTB Open Drain Enable bits For RB<7:0> pins, respectively 1 = Port
PIC16(L)F1782/3 TABLE 13-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 129 INLVLB7 INLVLB6 INLVLB5 INLVLB4 INLVLB3 INLVLB2 INLVLB1 INLVLB0 130 LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 128 ODCONB ODB7 ODB6 ODB5 ODB4 ODB3 ODB2 ODB1 ODB0 130 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 128 SLRB7 SLRB6 SLRB5 SLRB4 SLRB3 SLRB2 SLRB1 SLRB0 130 Na
PIC16(L)F1782/3 13.7 13.7.1 PORTC Registers feature is enabled. See Section 30.1 “DC Characteristics: PIC16(L)F1782/3-I/E (Industrial, Extended)” for more information on threshold levels. DATA REGISTER PORTC is an 8-bit wide bidirectional port. The corresponding data direction register is TRISC (Register 13-19). Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode).
PIC16(L)F1782/3 13.
PIC16(L)F1782/3 REGISTER 13-21: WPUC: WEAK PULL-UP PORTC REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUC7 WPUC6 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: 2: WPUC<7:0>: Weak Pull-up Register bits 1 = Pull-up enabled 0 = Pull
PIC16(L)F1782/3 REGISTER 13-24: INLVLC: PORTC INPUT LEVEL CONTROL REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 INLVLC7 INLVLC6 INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 INLVLC<7:0>: PORTC Input Level Select bits For RC<7:0
PIC16(L)F1782/3 13.9 PORTE Registers 13.9.2 RE3 is input only, and also functions as MCLR. The MCLR feature can be disabled via a configuration fuse. RE3 also supplies the programming voltage. The TRIS bit for RE3 (TRISE3) always reads ‘1’. 13.9.1 PORTE FUNCTIONS AND OUTPUT PRIORITIES No output priorities, RE3 is an input only pin. INPUT THRESHOLD CONTROL The INLVLE register (Register 13-28) controls the input voltage threshold for each of the available PORTE input pins.
PIC16(L)F1782/3 13.
PIC16(L)F1782/3 REGISTER 13-28: INLVLE: PORTE INPUT LEVEL CONTROL REGISTER U-0 U-0 U-0 U-0 R/W-1/1 U-0 U-0 U-0 — — — — INLVLE3 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 INLVLE3: PORTE Input Level Select bit 1 = ST input used for PORT reads and interrupt-on-
PIC16(L)F1782/3 14.0 INTERRUPT-ON-CHANGE 14.3 All pins on all ports can be configured to operate as Interrupt-On-Change (IOC) pins. An interrupt can be generated by detecting a signal that has either a rising edge or a falling edge. Any individual pin, or combination of pins, can be configured to generate an interrupt.
PIC16(L)F1782/3 FIGURE 14-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM IOCBNx D Q4Q1 Q CK edge detect R RBx IOCBPx D data bus = 0 or 1 Q write IOCBFx CK D S Q to data bus IOCBFx CK IOCIE R Q2 from all other IOCBFx individual pin detectors Q1 Q3 Q4 Q4Q1 DS41579D-page 140 Q1 Q1 Q2 Q2 Q2 Q3 Q4 Q4Q1 IOC interrupt to CPU core Q3 Q4 Q4 Q4Q1 Preliminary Q4Q1 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 14.
PIC16(L)F1782/3 REGISTER 14-3: IOCxF: INTERRUPT-ON-CHANGE FLAG REGISTER R/W/HS-0/0 R/W/HS-0/0 IOCxF7 IOCxF6 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 IOCxF5 IOCxF4 IOCxF3 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 IOCxF2 IOCxF1 IOCxF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware IOCxF<7:0>: Interrup
PIC16(L)F1782/3 15.0 FIXED VOLTAGE REFERENCE (FVR) The Fixed Voltage Reference, or FVR, is a stable voltage reference, independent of VDD, with 1.024V, 2.048V or 4.096V selectable output levels. The output of the FVR can be configured to supply a reference voltage to the following: • • • • ADC input channel ADC positive reference Comparator positive input Digital-to-Analog Converter (DAC) The FVR can be enabled by setting the FVREN bit of the FVRCON register. 15.
PIC16(L)F1782/3 FIGURE 15-1: VOLTAGE REFERENCE BLOCK DIAGRAM ADFVR<1:0> CDAFVR<1:0> 2 X1 X2 X4 FVR BUFFER1 (To ADC Module) X1 X2 X4 FVR BUFFER2 (To Comparators, DAC) 2 HFINTOSC Enable HFINTOSC To BOR, LDO FVREN + FVRRDY _ Any peripheral requiring the Fixed Reference (See Table 15-1) TABLE 15-1: PERIPHERALS REQUIRING THE FIXED VOLTAGE REFERENCE (FVR) Peripheral HFINTOSC Conditions Description FOSC<2:0> = 100 and IRCF<3:0> 000x INTOSC is active and device is not in Sleep BOREN<1:0> = 1
PIC16(L)F1782/3 15.
PIC16(L)F1782/3 NOTES: DS41579D-page 146 Preliminary 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 16.0 TEMPERATURE INDICATOR MODULE FIGURE 16-1: This family of devices is equipped with a temperature circuit designed to measure the operating temperature of the silicon die. The circuit’s range of operating temperature falls between -40°C and +85°C. The output is a voltage that is proportional to the device temperature. The output of the temperature indicator is internally connected to the device ADC.
PIC16(L)F1782/3 TABLE 16-2: Name FVRCON Legend: SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 FVREN FVRRDY TSEN TSRNG — — Bit 1 Bit 0 ADFVR<1:0> Register on page 144 Shaded cells are unused by the temperature indicator module. DS41579D-page 148 Preliminary 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 17.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The ADC voltage reference is software selectable to be either internally generated or externally supplied. The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. The Analog-to-Digital Converter (ADC) allows conversion of a single-ended and differential analog input signals to a 12-bit binary representation of that signal.
PIC16(L)F1782/3 17.1 ADC Configuration 17.1.3 When configuring and using the ADC the following functions must be considered: • Port configuration • Channel selection - Single-ended - Differential • ADC voltage reference selection • ADC conversion clock source • Interrupt control • Result formatting 17.1.1 17.1.2 The ADNREF bits of the ADCON1 register provide control of the negative voltage reference.
PIC16(L)F1782/3 TABLE 17-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES ADC Clock Period (TAD) Device Frequency (FOSC) ADC Clock Source ADCS<2:0> 32 MHz 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz FOSC/2 000 62.5ns(2) 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s FOSC/4 100 125 ns (2) (2) (2) (2) FOSC/8 001 0.5 s(2) 400 ns(2) 0.5 s(2) FOSC/16 101 800 ns 800 ns 1.0 s FOSC/32 200 ns 1.0 s 010 1.6 s 250 ns 2.0 s FOSC/64 110 2.0 s 3.2 s 4.
PIC16(L)F1782/3 17.1.5 INTERRUPTS 17.1.6 The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. RESULT FORMATTING The 10-bit and 12-bit ADC conversion results can be supplied in two formats: 2’s complement or sign-magnitude.
PIC16(L)F1782/3 TABLE 17-2: ADC OUTPUT RESULTS FORMAT Absolute ADC Value (decimal) Sign and Magnitude Result ADFM = 0, ADRMD = 0 ADRESH (ADRES<15:8>) ADRESL (ADRES<7:0>) 2’s Compliment Result ADFM = 1, ADRMD = 0 ADRESH (ADRES<15:8>) ADRESL (ADRES<7:0>) + 4095 1111 1111 1111 0000 0000 1111 1111 1111 0000 1001 0011 0011 + 2355 1001 0011 0011 0000 + 0001 0000 0000 0001 0000 0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 - 0001 0000 0000 0001 0001 - 4095 1111 1111 11
PIC16(L)F1782/3 17.2 17.2.1 ADC Operation 17.2.4 STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a ‘1’. Setting the GO/DONE bit of the ADCON0 register to a ‘1’ will clear the ADRESH and ADRESL registers and start the Analog-to-Digital conversion. Note: The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 17.2.6 “A/D Conversion Procedure”. ADC OPERATION DURING SLEEP The ADC module can operate during Sleep.
PIC16(L)F1782/3 17.2.6 A/D CONVERSION PROCEDURE EXAMPLE 17-1: This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. 2. 3. 4. 5. 6. 7. 8.
PIC16(L)F1782/3 17.
PIC16(L)F1782/3 REGISTER 17-2: R/W-0/0 ADCON1: ADC CONTROL REGISTER 1 R/W-0/0 ADFM R/W-0/0 R/W-0/0 ADCS<2:0> U-0 R/W-0/0 — ADNREF R/W-0/0 bit 7 R/W-0/0 ADPREF<1:0> bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: ADC Result Format Select bit (see Figure 17-3) 1 = 2’s complement format.
PIC16(L)F1782/3 REGISTER 17-3: R/W-0/0 ADCON2: ADC CONTROL REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TRIGSEL<3:0> R/W-0/0 R/W-0/0 R/W-0/0 CHSN<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 TRIGSEL<3:0>: ADC Auto-conversion Trigger Source Selection bits 1111 = Reserved.
PIC16(L)F1782/3 REGISTER 17-4: R/W-x/u ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u AD<11:4> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 AD<11:4>: ADC Result Register bits Upper 8 bits of 12-bit conversion result REGISTER 17-5: R/W-x/u ADRESL
PIC16(L)F1782/3 REGISTER 17-6: R/W-x/u ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADSIGN R/W-x/u R/W-x/u R/W-x/u AD<11:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 ADSIGN: Extended AD Result Sign bit bit 3-0 AD<11:8>: ADC Result Register bits Most significant
PIC16(L)F1782/3 17.4 ADC Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 17-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), refer to Figure 17-4.
PIC16(L)F1782/3 FIGURE 17-4: ANALOG INPUT MODEL Rs VA VDD Analog Input pin VT 0.6V CPIN 5 pF VT 0.
PIC16(L)F1782/3 TABLE 17-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH ADC Bit 7 ADCON0 ADRMD ADCON1 ADFM ADCON2 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 — ADNREF CHS<4:0> ADCS<2:0> TRIGSEL<3:0> ADRESH A/D Result Register High ADRESL A/D Result Register Low Bit 1 Bit 0 Register on Page GO/DONE ADON 156 ADPREF<1:0> CHSN<3:0> 157 158 159, 160 159, 160 ANSELA ANSA7 — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 123 ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 129 INTCON GIE PEIE
PIC16(L)F1782/3 NOTES: DS41579D-page 164 Preliminary 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 18.0 OPERATIONAL AMPLIFIER (OPA) MODULES The Operational Amplifier (OPA) is a standard three-terminal device requiring external feedback to operate.
PIC16(L)F1782/3 18.1 Effects of Reset 18.3 A device Reset forces all registers to their Reset state. This disables the OPA module. 18.2 OPA Module Performance Common AC and DC performance specifications for the OPA module: • • • • • Common Mode Voltage Range Leakage Current Input Offset Voltage Open Loop Gain Gain Bandwidth Product OPAxCON Control Register The OPAxCON register, shown in Register 18-1, controls the OPA module.
PIC16(L)F1782/3 18.
PIC16(L)F1782/3 NOTES: DS41579D-page 168 Preliminary 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 19.0 DIGITAL-TO-ANALOG CONVERTER (DAC) MODULE The Digital-to-Analog Converter supplies a variable voltage reference, ratiometric with the input source, with 256 selectable output levels. 19.1 Output Voltage Selection The DAC has 256 voltage level ranges. The 256 levels are set with the DACR<7:0> bits of the DACCON1 register.
PIC16(L)F1782/3 FIGURE 19-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM Digital-to-Analog Converter (DAC) FVR BUFFER2 VSOURCE+ VDD 8 VREF+ DACPSS<1:0> DACR<7:0> R R 2 R DACEN R 256 Steps R 32-to-1 MUX R DAC_Output R (To Comparator and ADC Modules) DACOUT1 R DACOE1 DACNSS DACOUT2 VREF- DACOE2 VSOURCE- VSS FIGURE 19-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC® MCU DAC Module R Voltage Reference Output Impedance DS41579D-page 170 DACOUTX Preliminary + – Buffered DAC Output
PIC16(L)F1782/3 19.4 Operation During Sleep When the device wakes up from Sleep through an interrupt or a Watchdog Timer time-out, the contents of the DACCON0 register are not affected. To minimize current consumption in Sleep mode, the voltage reference should be disabled. 19.5 Effects of a Reset A device Reset affects the following: • DAC is disabled. • DAC output voltage is removed from the DACOUT pin. • The DACR<7:0> range select bits are cleared. 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 19.
PIC16(L)F1782/3 20.0 COMPARATOR MODULE FIGURE 20-1: Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. Comparators are very useful mixed signal building blocks because they provide analog functionality independent of program execution.
PIC16(L)F1782/3 FIGURE 20-2: COMPARATOR MODULE SIMPLIFIED BLOCK DIAGRAM CxNCH<2:0> CxON(1) 3 CxINTP Interrupt det CXIN0- 0 CXIN1- 1 CXIN2- 2MUX Set CxIF CXIN3- det 3 Reserved 4 Reserved 5 Reserved 6 CxINTN Interrupt (2) CXPOL CxVN - 0 D Cx CxVP ZLF + 1 EN Q1 7 CxHYS AGND CxSP to CMXCON0 (CXOUT) and CM2CON1 (MCXOUT) Q CxZLF async_CxOUT CXSYNC CXOE TRIS bit CXOUT 0 CXIN0+ 0 CXIN1+ 1 Reserved 2 Reserved 3 Reserved 4 DAC_Output 5 FVR Buffer2 6 D From T
PIC16(L)F1782/3 20.2 Comparator Control 20.2.3 Each comparator has two control registers: CMxCON0 and CMxCON1. The CMxCON0 registers (see Register 20-1) contain Control and Status bits for the following: • • • • • • Enable Output selection Output polarity Speed/Power selection Hysteresis enable Output synchronization Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs.
PIC16(L)F1782/3 20.3 Comparator Hysteresis 20.5 A selectable amount of separation voltage can be added to the input pins of each comparator to provide a hysteresis function to the overall operation. Hysteresis is enabled by setting the CxHYS bit of the CMxCON0 register. Comparator Interrupt An interrupt can be generated upon a change in the output value of the comparator for each comparator, a rising edge detector and a falling edge detector are present. See Section 30.
PIC16(L)F1782/3 20.7 Comparator Negative Input Selection Therefore, both of these times must be considered when determining the total response time to a comparator input change. See the Comparator and Voltage Reference Specifications in Section 30.0 “Electrical Specifications” for more details. The CxNCH<2:0> bits of the CMxCON0 register direct an analog input pin or analog ground to the inverting input of the comparator: 20.
PIC16(L)F1782/3 20.10 Analog Input Connection Considerations 20.10.1 A simplified circuit for an analog input is shown in Figure 20-4. Since the analog input pins share their connection with a digital input, they have reverse biased ESD protection diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur.
PIC16(L)F1782/3 20.
PIC16(L)F1782/3 REGISTER 20-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1 R/W-0/0 R/W-0/0 CxINTP CxINTN R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 CxPCH<2:0> R/W-0/0 R/W-0/0 CxNCH<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CxINTP: Comparator Interrupt on Positive Going Edge Enable bits 1 = The CxIF interrupt
PIC16(L)F1782/3 TABLE 20-3: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA ANSA7 — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 123 ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 129 CM1CON0 C1ON C1OUT C1OE C1POL C1ZLF C1SP C1HYS C1SYNC 179 CM2CON0 C2ON C2OUT C2OE C2POL C2ZLF C2SP C2HYS C2SYNC 179 CM1CON1 C1NTP C1INTN C1PCH<2:0> C1NCH<2:0> CM2CON1 C2NTP C2INTN C2PCH<2:0> C2NCH<2:
PIC16(L)F1782/3 NOTES: DS41579D-page 182 Preliminary 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 21.0 TIMER0 MODULE 21.1.2 8-BIT COUNTER MODE The Timer0 module is an 8-bit timer/counter with the following features: In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin. • • • • • • 8-Bit Counter mode using the T0CKI pin is selected by setting the TMR0CS bit in the OPTION_REG register to ‘1’.
PIC16(L)F1782/3 21.1.3 SOFTWARE PROGRAMMABLE PRESCALER A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION_REG register. Note: The Watchdog Timer (WDT) uses its own independent prescaler. There are eight prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION_REG register.
PIC16(L)F1782/3 21.
PIC16(L)F1782/3 NOTES: DS41579D-page 186 Preliminary 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 22.0 TIMER1 MODULE WITH GATE CONTROL • • • • The Timer1 module is a 16-bit timer/counter with the following features: Figure 22-1 is a block diagram of the Timer1 module.
PIC16(L)F1782/3 22.1 Timer1 Operation 22.2 The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and increments on every selected edge of the external source.
PIC16(L)F1782/3 22.3 Timer1 Prescaler 22.5.1 Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L. 22.
PIC16(L)F1782/3 22.6.2 TIMER1 GATE SOURCE SELECTION Timer1 gate source selections are shown in Table 22-4. Source selection is controlled by the T1GSS bits of the T1GCON register. The polarity for each available source is also selectable. Polarity selection is controlled by the T1GPOL bit of the T1GCON register.
PIC16(L)F1782/3 22.7 Timer1 Interrupt 22.9 The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: • • • • TMR1ON bit of the T1CON register TMR1IE bit of the PIE1 register PEIE bit of the INTCON register GIE bit of the INTCON register The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine.
PIC16(L)F1782/3 FIGURE 22-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL t1g_in T1CKI T1GVAL Timer1 N FIGURE 22-4: N+1 N+2 N+3 N+4 TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM t1g_in T1CKI T1GVAL Timer1 DS41579D-page 192 N N+1 N+2 N+3 N+4 Preliminary N+5 N+6 N+7 N+8 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 FIGURE 22-5: TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G t1g_in T1CKI T1GVAL Timer1 TMR1GIF N N+1 Set by hardware on falling edge of T1GVAL Cleared by software 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 FIGURE 22-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G t1g_in T1CKI T1GVAL Timer1 TMR1GIF DS41579D-page 194 N Cleared by software N+1 N+2 N+3 N+4 Set by hardware on falling edge of T1GVAL Preliminary Cleared by software 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 22.
PIC16(L)F1782/3 REGISTER 22-2: T1GCON: TIMER1 GATE CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ DONE T1GVAL R/W-0/u R/W-0/u T1GSS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 TMR1GE: Timer1 Gate Enable bit If
PIC16(L)F1782/3 TABLE 22-5: Name ANSELB SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 129 CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> CCP2CON P2M<1:0> DC2B<1:0> CCP2M<3:0> INTCON PIE1 PIR1 PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 84 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 85 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF Holding Register for the
PIC16(L)F1782/3 NOTES: DS41579D-page 198 Preliminary 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 23.0 TIMER2 MODULE The Timer2 module incorporates the following features: • 8-bit Timer and Period registers (TMR2 and PR2, respectively) • Readable and writable (both registers) • Software programmable prescaler (1:1, 1:4, 1:16, and 1:64) • Software programmable postscaler (1:1 to 1:16) • Interrupt on TMR2 match with PR2, respectively • Optional use as the shift clock for the MSSP module See Figure 23-1 for a block diagram of Timer2.
PIC16(L)F1782/3 23.1 Timer2 Operation 23.3 The clock input to the Timer2 modules is the system instruction clock (FOSC/4). TMR2 increments from 00h on each clock edge. A 4-bit counter/prescaler on the clock input allows direct input, divide-by-4 and divide-by-16 prescale options. These options are selected by the prescaler control bits, T2CKPS<1:0> of the T2CON register. The value of TMR2 is compared to that of the Period register, PR2, on each clock cycle.
PIC16(L)F1782/3 23.
PIC16(L)F1782/3 TABLE 23-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2 Bit 7 CCP2CON Bit 6 P2M<1:0> Bit 5 Bit 4 Bit 3 DC2B<1:0> Bit 2 Bit 1 Bit 0 CCP2M<3:0> Register on Page 266 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 84 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 85 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF PR2 Timer2 Module Period Register INTCON PIE1 T2CON TMR2 — 88 199* T2OUTPS<3:0> TMR2ON T2CKPS<1:0> Holding Register for
PIC16(L)F1782/3 24.0 PROGRAMMABLE SWITCH MODE CONTROL (PSMC) Modes of operation include: The Programmable Switch Mode Controller (PSMC) is a high-performance Pulse Width Modulator (PWM) that can be configured to operate in one of several modes to support single or multiple phase applications. A simplified block diagram indicating the relationship between inputs, outputs, and controls is shown in Figure 24-1. This section begins with the fundamental aspects of the PSMC operation.
PSMC SIMPLIFIED BLOCK DIAGRAM PIC16(L)F1782/3 PXCPRE<1:0> PXCSRC<1:0> PSMCXCLK 64 MHZ FOSC sync_in psmc_clk 1,2, 4, 8 PSMCXPR = FFA PSMCXTMR CLR Period Event DS41579D-page 204 FIGURE 24-1: sync_out PSMCXPOL PSMCXOEN 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 24.1 Fundamental Operation PSMC operation is based on the sequence of three events: The basic waveform generated from these events is shown in Figure 24-2. • Period Event – Determines the frequency of the active signal. • Rising Edge Event – Determines start of the active pulse. This is also referred to as the phase. • Falling Edge Event – Determines the end of the active pulse. This is also referred to as the duty cycle.
PIC16(L)F1782/3 24.1.1 PERIOD EVENT The period event determines the frequency of the active pulse. Period event sources include any combination of the following: • • • • • PSMCxTMR counter match PSMC input pin sync_C1OUT sync_C2OUT sync_C3OUT Period event sources are selected with the PSMC Period Source (PSMCxPRS) register (Register 24-13). Section 24.2.1.2 “16-bit Period Register” contains details on configuring the PSMCxTMR counter match for synchronous period events.
PIC16(L)F1782/3 24.2 Event Sources 24.2.1.2 There are two main sources for the period, rising edge and falling edge events: • Synchronous input - Time base • Asynchronous Inputs - Digital Inputs - Analog inputs 24.2.1 TIME BASE 16-bit time base counter 16-bit Period register 16-bit Phase register (rising edge event) 16-bit Duty Cycle register (falling edge event) Clock control Interrupt Generator An example of a fully synchronous PWM waveform generated with the time base is shown in Figure 24-2.
PIC16(L)F1782/3 24.2.1.4 16-bit Duty Cycle Register The PSMCxDC Duty Cycle register is used to determine a synchronous falling edge event referenced to the 16-bit PSMCxTMR digital counter. A match between the PSMCxTMR and PSMCxDC register values will generate a falling edge event. The match will generate a duty cycle match interrupt, thereby setting the PxTDCIF bit of the PSMC Time Base Interrupt Control (PSMCxINT) register (Register 24-32).
PIC16(L)F1782/3 FIGURE 24-3: TIME BASE WAVEFORM GENERATION 1 Period psmc_clk Counter 0030h 0000h 0001h 0002h 0003h 0027h PSMCxPH<15:0> 0002h PSMCxDC<15:0> 0028h PSMCxPR<15:0> 0030h 0028h 0029h 0030h 0000h Inputs Period Event Rising Edge Event Falling Edge Event Output PWM Output 24.2.7 ASYNCHRONOUS INPUTS 24.2.7.2 The PSMC module supports asynchronous inputs alone or in combination with the synchronous inputs.
PIC16(L)F1782/3 24.2.8 INPUT BLANKING Input blanking is a function whereby the inputs from any selected asynchronous input may be driven inactive for a short period of time. This is to prevent electrical transients from the turn-on/off of power components from generating a false event.
PIC16(L)F1782/3 Steering differs from output enable in the following manner: When the output is enabled but the PWM steering to the corresponding output is not enabled, then general purpose output to the pin is disabled and the pin level will remain constantly in the inactive PWM state. Output steering is controlled with the PSMCS Steering Control 0 (PSMCxSTR0) register (Register 24-30). Steering operates only in the following modes: • Single-phase • Complementary Single-phase • 3-phase 6-step PWM 24.2.10.
PIC16(L)F1782/3 24.3 Modes of Operation 24.3.1.2 Waveform Generation All modes of operation use the period, rising edge, and falling edge events to generate the various PWM output waveforms. Rising Edge Event The 3-phase 6-step PWM mode makes special use of the software controlled steering to generate the required waveform. Falling Edge Event Modes of operation are selected with the PSMC Control (PSMCxCON) register (Register 24-1). 24.3.
PIC16(L)F1782/3 24.3.2 COMPLEMENTARY PWM EXAMPLE 24-2: The complementary PWM uses the same events as the single PWM, but two waveforms are generated instead of only one. The two waveforms are opposite in polarity to each other. The two waveforms may also have dead-band control as well. 24.3.2.
PIC16(L)F1782/3 24.3.3 PUSH-PULL PWM The push-pull PWM is used to drive transistor bridge circuits. It uses at least two outputs and generates PWM signals that alternate between the two outputs in even and odd cycles. Variations of the push-pull waveform include four outputs with two outputs being complementary or two sets of two identical outputs. Refer to Sections 24.3.4 through 24.3.6 for the other Push-Pull modes. 24.3.3.
PIC16(L)F1782/3 24.3.4 PUSH-PULL PWM WITH COMPLEMENTARY OUTPUTS 24.3.4.2 The complementary push-pull PWM is used to drive transistor bridge circuits as well as synchronous switches on the secondary side of the bridge. The PWM waveform is output on four pins presented as two pairs of two-output signals with a normal and complementary output in each pair. Dead band can be inserted between the normal and complementary outputs at the transition times. 24.3.4.
PIC16(L)F1782/3 24.3.5 PUSH-PULL PWM WITH FOUR FULL-BRIDGE OUTPUTS The full-bridge push-pull PWM is used to drive transistor bridge circuits as well as synchronous switches on the secondary side of the bridge. 24.3.5.
PIC16(L)F1782/3 24.3.6 PUSH-PULL PWM WITH FOUR FULL-BRIDGE AND COMPLEMENTARY OUTPUTS 24.3.6.2 The push-pull PWM is used to drive transistor bridge circuits as well as synchronous switches on the secondary side of the bridge. It uses six outputs and generates PWM signals with dead band that alternate between the six outputs in even and odd cycles. 24.3.6.1 Mode Features and Controls Waveform Generation Push-pull waveforms generate alternating outputs on two sets of pin.
PIC16(L)F1782/3 FIGURE 24-9: PUSH-PULL 4 FULL-BRIDGE AND COMPLEMENTARY PWM 1 PWM Period Number 2 3 Period Event Rising Edge Event Falling Edge Event Rising Edge Dead Band Rising Edge Dead Band PSMCxA PSMCxC Falling Edge Dead Band Falling Edge Dead Band PSMCxE PSMCxB PSMCxD Falling Edge Dead Band Rising Edge Dead Band PSMCxF 24.3.7 PULSE-SKIPPING PWM 24.3.7.
PIC16(L)F1782/3 FIGURE 24-10: PULSE-SKIPPING PWM WAVEFORM PWM Period Number 1 2 3 4 5 6 7 8 9 10 11 12 period_event Asynchronous Rising Edge Event Synchronous Rising Edge Event Falling Edge Event PSMCxA 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 24.3.8 PULSE-SKIPPING PWM WITH COMPLEMENTARY OUTPUTS 24.3.8.2 Waveform Generation Rising Edge Event The pulse-skipping PWM is used to generate a series of fixed-length pulses that may or not be triggered at each period event. If any of the sources enabled to generate a rising edge event are high when a period event occurs, a pulse will be generated. If the rising edge sources are low at the period event, no pulse will be generated.
PIC16(L)F1782/3 24.3.9 ECCP COMPATIBLE FULL-BRIDGE PWM 24.3.9.2 In this mode of operation, three of the four pins are static. PSMCxA is the only output that changes based on rising edge and falling edge events. This mode of operation is designed to match the Full-Bridge mode from the ECCP module. It is called ECCP compatible as the term “full-bridge” alone has different connotations in regards to the output waveforms.
PIC16(L)F1782/3 24.3.10 VARIABLE FREQUENCY – FIXED DUTY CYCLE PWM 24.3.10.2 Waveform Generation Period Event This mode of operation is quite different from all of the other modes. It uses only the period event for waveform generation. At each period event, the PWM output is toggled. • Output of PSMCxA is toggled • FFA counter is incremented by the 4-bit value in PSMCxF FA The rising edge and falling edge events are unused in this mode. 24.3.10.
PIC16(L)F1782/3 24.3.11 VARIABLE FREQUENCY - FIXED DUTY CYCLE PWM WITH COMPLEMENTARY OUTPUTS 24.3.11.2 Period Event When output is going inactive to active: This mode is the same as the single output Fixed Duty Cycle mode except a complementary output with dead-band control is generated. • Complementary output is set inactive • FFA counter is incremented by the 4-bit value in PSMCFFA register.
PIC16(L)F1782/3 24.3.12 3-PHASE PWM 24.3.12.2 Waveform Generation The 3-Phase mode of operation is used in 3-phase power supply and motor drive applications configured as three half-bridges. A half-bridge configuration consists of two power driver devices in series, between the positive power rail (high side) and negative power rail (low side). The three outputs come from the junctions between the two drivers in each half-bridge.
2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 24.4 Dead-Band Control 24.4.3 The dead-band control provides non-overlapping PWM signals to prevent shoot-through current in series connected power switches. Dead-band control is available only in modes with complementary drive and when changing direction in the ECCP compatible Full-Bridge modes. The module contains independent 8-bit dead-band counters for rising edge and falling edge dead-band control. 24.4.
PIC16(L)F1782/3 24.5 Output Steering 24.5.1 Output steering allows for PWM signals generated by the PSMC module to be placed on different pins under software control. Synchronized steering will hold steering changes until the first period event after the PSMCxLD bit is set. Unsynchronized steering changes will take place immediately.
PIC16(L)F1782/3 24.5.3 COMPLEMENTARY PWM STEERING The complementary PWM signal can be steered to any of the following outputs: In Complementary PWM Steering mode, the primary PWM signal (non-complementary) and complementary signal can be steered according to their respective type. • PSMCxB • PSMCxD • PSMCxE Primary PWM signal can be steered to any of the following outputs: Examples of unsynchronized complementary steering are shown in Figure 24-17.
PIC16(L)F1782/3 24.5.4 SYNCHRONIZED PWM STEERING Examples of synchronized steering are shown in Figure 24-18. In Single, Complementary and 3-phase PWM modes, it is possible to synchronize changes to steering selections with the period event. This is so that PWM outputs do not change in the middle of a cycle and therefore, disrupt operation of the application. 24.5.
PIC16(L)F1782/3 24.6 PSMC Modulation (Burst Mode) 24.6.2.1 PSMC modulation is a method to stop/start PWM operation of the PSMC without having to disable the module. It also allows other modules to control the operational period of the PSMC. This is also referred to as Burst mode. This is a method to implement PWM dimming. 24.6.1 MODULATION ENABLE The modulation function is enabled by setting the PxMDLEN bit of PSMC Modulation Control (PSMCxMDL) register (Register 24-2).
PIC16(L)F1782/3 24.7 Auto-Shutdown 24.7.2 Auto-shutdown is a method to immediately override the PSMC output levels with specific overrides that allow for safe shutdown of the application. Auto-shutdown includes a mechanism to allow the application to restart under different conditions. Auto-shutdown is enabled with the PxASDEN bit of the PSMC Auto-shutdown Control (PSMCxASDC) register (Register 24-14). All auto-shutdown features are enabled when PxASDEN is set and disabled when cleared. 24.7.
PIC16(L)F1782/3 FIGURE 24-20: AUTO-SHUTDOWN AND RESTART WAVEFORM 1 2 3 4 5 Base PWM signal PxARSEN Next Period Event Auto-Shutdown Source cleared in software PSMCx Auto-shutdown int flag bit cleared in software Cleared in hardware Next Period Event PxASE Cleared in software PSMCxA PSMCxB Operating State Normal Output Autoshutdown Manual Restart DS41579D-page 232 Preliminary Normal Output Autoshutdown Normal Output Auto-restart 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 24.8 PSMC Synchronization 24.8.1 It is possible to synchronize the periods of two or more PSMC modules together, provided that all modules are on the same device. Synchronization is achieved by sending a sync signal from the master PSMC module to the desired slave modules. This sync signal generates a period event in each slave module, thereby aligning all slaves with the master.
PIC16(L)F1782/3 24.9 Fractional Frequency Adjust (FFA) FFA is a method by which PWM resolution can be improved on 50% fixed duty cycle signals. Higher resolution is achieved by altering the PWM period by a single count for calculated intervals. This increased resolution is based upon the PWM frequency averaged over a large number of PWM periods.
PIC16(L)F1782/3 TABLE 24-4: SAMPLE FFA OUTPUT PERIODS/FREQUENCIES FFA number Output Frequency (kHz) Step Size (Hz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 125.000 124.970 124.939 124.909 124.878 124.848 124.818 124.787 124.757 124.726 124.696 124.666 124.635 124.605 124.574 124.544 0 -30.4 -60.8 -91.2 -121.6 -152.0 -182.4 -212.8 -243.2 -273.6 -304.0 -334.4 -364.8 -395.2 -425.6 -456.0 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 24.10 Register Updates 24.11 Operation During Sleep There are 10 double-buffered registers that can be updated “on the fly”. However, due to the asynchronous nature of the potential updates, a special hardware system is used for the updates. The PSMC continues to operate in Sleep with the following clock sources: There are two operating cases for the PSMC: • Internal 64 MHz • External clock • module is enabled • module is disabled 24.10.
PIC16(L)F1782/3 24.
PIC16(L)F1782/3 REGISTER 24-2: PSMCxMDL: PSMC MODULATION CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 U-0 PxMDLEN PxMDLPOL PxMDLBIT — R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PxMSRC<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PxMDLEN: PSMC Periodic Modulation Mode Enable bit 1 = PSMCx is active when input sig
PIC16(L)F1782/3 REGISTER 24-3: PSMC1SYNC: PSMC1 SYNCHRONIZATION CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — R/W-0/0 R/W-0/0 P1SYNC<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1-0 P1SYNC<1:0>: PSMC1 Period Synchronization Mode bits 10 = PSMC1 is synchr
PIC16(L)F1782/3 REGISTER 24-5: PSMCxCLK: PSMC CLOCK CONTROL REGISTER U-0 U-0 — — R/W-0/0 R/W-0/0 PxCPRE<1:0> U-0 U-0 — — R/W-0/0 R/W-0/0 PxCSRC<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 PxCPRE<1:0>: PSMCx Clock Prescaler Selection bits 11 = PSMCx Clock fr
PIC16(L)F1782/3 REGISTER 24-7: U-0 PSMCxPOL: PSMC POLARITY CONTROL REGISTER R/W-0/0 — PxPOLIN R/W-0/0 PxPOLF (1) R/W-0/0 (1) PxPOLE R/W-0/0 (1) PxPOLD R/W-0/0 PxPOLC (1) R/W-0/0 R/W-0/0 PxPOLB PxPOLA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6 PxPOLIN: PSMCxIN Pola
PIC16(L)F1782/3 REGISTER 24-9: PSMCxREBS: PSMC RISING EDGE BLANKED SOURCE REGISTER R/W-0/0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 PxREBSIN — — — PxREBSC3 PxREBSC2 PxREBSC1 — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PxREBSIN: PSMCx Rising Edge Event Blanked from PSMCxIN pin 1 = PSMCxIN pin canno
PIC16(L)F1782/3 REGISTER 24-11: PSMCxPHS: PSMC PHASE SOURCE REGISTER(1) R/W-0/0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PxPHSIN — — — PxPHSC3 PxPHSC2 PxPHSC1 PxPHST bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PxPHSIN: PSMCx Rising Edge Event occurs on PSMCxIN pin 1 = Rising edge event will occur
PIC16(L)F1782/3 REGISTER 24-12: PSMCxDCS: PSMC DUTY CYCLE SOURCE REGISTER(1) R/W-0/0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PxDCSIN — — — PxDCSC3 PxDCSC2 PxDCSC1 PxDCST bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PxDCSIN: PSMCx Falling Edge Event occurs on PSMCxIN pin 1 = Falling edge event will
PIC16(L)F1782/3 REGISTER 24-13: PSMCxPRS: PSMC PERIOD SOURCE REGISTER(1) R/W-0/0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PxPRSIN — — — PxPRSC3 PxPRSC2 PxPRSC1 PxPRST bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PxPRSIN: PSMCx Period Event occurs on PSMCxIN pin 1 = Period event will occur and PSMCx
PIC16(L)F1782/3 REGISTER 24-14: PSMCxASDC: PSMC AUTO-SHUTDOWN CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 R/W-0/0 PxASE PxASDEN PxARSEN — — — — PxASDOV bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PxASE: PWM Auto-Shutdown Event Status bit(1) 1 = A shutdown event has occurred, PWM outputs
PIC16(L)F1782/3 REGISTER 24-15: PSMCxASDL: PSMC AUTO-SHUTDOWN OUTPUT LEVEL REGISTER U-0 U-0 — — R/W-0/0 PxASDLF (1) R/W-0/0 (1) PxASDLE R/W-0/0 (1) PxASDLD R/W-0/0 (1) PxASDLC R/W-0/0 R/W-0/0 PxASDLB PxASDLA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5 PxASDLF: PSM
PIC16(L)F1782/3 REGISTER 24-16: PSMCxASDS: PSMC AUTO-SHUTDOWN SOURCE REGISTER R/W-0/0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 PxASDSIN — — — PxASDSC3 PxASDSC2 PxASDSC1 — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PxASDSIN: Auto-shutdown occurs on PSMCxIN pin 1 = Auto-shutdown will occur when PSMCxIN
PIC16(L)F1782/3 REGISTER 24-19: PSMCxPHL: PSMC PHASE COUNT LOW BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PSMCxPHL<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PSMCxPHL<7:0>: 16-bit Phase Count Least Significant bits = PSMCxPH<7:0> REGISTER 24-20: PSMCxPHH: PSMC PHAS
PIC16(L)F1782/3 REGISTER 24-21: PSMCxDCL: PSMC DUTY CYCLE COUNT LOW BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PSMCxDCL<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PSMCxDCL<7:0>: 16-bit Duty Cycle Count Least Significant bits = PSMCxDC<7:0> REGISTER 24-22: PSMCxDCH:
PIC16(L)F1782/3 REGISTER 24-23: PSMCxPRL: PSMC PERIOD COUNT LOW BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PSMCxPRL<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PSMCxPRL<7:0>: 16-bit Period Time Least Significant bits = PSMCxPR<7:0> REGISTER 24-24: PSMCxPRH: PSMC PER
PIC16(L)F1782/3 REGISTER 24-25: PSMCxDBR: PSMC RISING EDGE DEAD-BAND TIME REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PSMCxDBR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PSMCxDBR<7:0>: Rising Edge Dead-Band Time bits = Unsigned number of PSMCx psmc_clk clock periods in ri
PIC16(L)F1782/3 REGISTER 24-28: PSMCxBLKR: PSMC RISING EDGE BLANKING TIME REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PSMCxBLKR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PSMCxBLKR<7:0>: Rising Edge Blanking Time bits = Unsigned number of PSMCx psmc_clk clock periods in r
PIC16(L)F1782/3 REGISTER 24-30: PSMCxSTR0: PSMC STEERING CONTROL REGISTER 0 U-0 U-0 — — R/W-0/0 PxSTRF (2) R/W-0/0 PxSTRE (2) R/W-0/0 (2) PxSTRD R/W-0/0 PxSTRC (2) R/W-0/0 R/W-1/1 PxSTRB PxSTRA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5 PxSTRF: PWM Steering PSMCx
PIC16(L)F1782/3 REGISTER 24-30: PSMCxSTR0: PSMC STEERING CONTROL REGISTER 0 bit 1 PxSTRB: PWM Steering PSMCxB Output Enable bit If PxMODE<3:0> = 0000 (Single-phase PWM): 1 = Single PWM output is active on pin PSMCxOUT1 0 = Single PWM output is not active on pin PSMCxOUT1. PWM drive is in inactive state If PxMODE<3:0> = 0001 (Complementary Single-phase PWM): 1 = Complementary PWM output is active on pin PSMCxB 0 = Complementary PWM output is not active on pin PSMCxB.
PIC16(L)F1782/3 REGISTER 24-31: PSMCxSTR1: PSMC STEERING CONTROL REGISTER 1 R/W-0/0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 PxSSYNC — — — — — PxLSMEN PxHSMEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PxSSYNC: PWM Steering Synchronization bit 1 = PWM outputs are updated on period boundary 0 = PWM output
PIC16(L)F1782/3 REGISTER 24-32: PSMCxINT: PSMC TIME BASE INTERRUPT CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PxTOVIE PxTPHIE PxTDCIE PxTPRIE PxTOVIF PxTPHIF PxTDCIF PxTPRIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PxTOVIE: PSMC Time Base Counter Overflow Inte
PIC16(L)F1782/3 TABLE 24-5: SUMMARY OF REGISTERS ASSOCIATED WITH PSMC Bit7 Bit6 Bit5 Bit4 BIt3 Bit2 Bit1 Bit0 Register on Page GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 84 ODC7 ODC6 ODC5 ODC4 ODC3 ODC2 ODC1 ODC0 134 PIE4 — — PSMC2TIE PSMC1TIE — — PSMC2SIE PSMC1SIE 87 PIR4 — — PSMC2TIF PSMC1TIF — — PSMC2SIF PSMC1SIF 90 PxASE PxASDEN PxARSEN — — — — PxASDOV 246 PxASDLE(1) PxASDLD(1) PxASDLC(1) PxASDLB PxASDLA 247 — PxASDSC3 PxASDSC2 PxASDSC1
PIC16(L)F1782/3 25.0 CAPTURE/COMPARE/PWM MODULES The Capture/Compare/PWM module is a peripheral which allows the user to time and control different events, and to generate Pulse-Width Modulation (PWM) signals. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate Pulse-Width Modulated signals of varying frequency and duty cycle.
PIC16(L)F1782/3 25.1 Capture Mode 25.1.2 The Capture mode function described in this section is available and identical for all CCP modules. Capture mode makes use of the 16-bit Timer1 resource. When an event occurs on the CCPx pin, the 16-bit CCPRxH:CCPRxL register pair captures and stores the 16-bit value of the TMR1H:TMR1L register pair, respectively.
PIC16(L)F1782/3 25.1.5 CAPTURE DURING SLEEP FIGURE 25-2: COMPARE MODE OPERATION BLOCK DIAGRAM Capture mode depends upon the Timer1 module for proper operation. There are two options for driving the Timer1 module in Capture mode. It can be driven by the instruction clock (FOSC/4), or by an external clock source. When Timer1 is clocked by FOSC/4, Timer1 will not increment during Sleep. When the device wakes from Sleep, Timer1 will continue from its previous state.
PIC16(L)F1782/3 25.2.4 AUTO-CONVERSION TRIGGER When Auto-conversion Trigger mode is chosen (CCPxM<3:0> = 1011), the CCPx module does the following: • Resets Timer1 • Starts an ADC conversion if ADC is enabled The CCPx module does not assert control of the CCPx pin in this mode. The Auto-conversion Trigger output of the CCP occurs immediately upon a match between the TMR1H, TMR1L register pair and the CCPRxH, CCPRxL register pair.
PIC16(L)F1782/3 FIGURE 25-4: SIMPLIFIED PWM BLOCK DIAGRAM Note: CCP1CON<5:4> Duty Cycle Registers CCPR1L To PSMC module CCPR1H(2) (Slave) CCP1 R Comparator (1) TMR2 Q PR2 Note 1: 2: 25.3.2 2. 3. 4. 5. 6. Clear Timer, toggle CCP1 pin and latch duty cycle EQUATION 25-1: PWM PERIOD PWM Period = PR2 + 1 4 T OSC The 8-bit timer TMR2 register is concatenated with the 2-bit internal system clock (FOSC), or 2 bits of the prescaler, to create the 10-bit time base.
PIC16(L)F1782/3 EQUATION 25-2: PULSE WIDTH When the 10-bit time base matches the CCPRxH and 2-bit latch, then the CCPx pin is cleared (see Figure 25-4). Pulse Width = CCPRxL:CCPxCON<5:4> T OSC (TMR2 Prescale Value) EQUATION 25-3: 25.3.6 PWM RESOLUTION The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles.
PIC16(L)F1782/3 25.3.7 OPERATION IN SLEEP MODE In Sleep mode, the TMR2 register will not increment and the state of the module will not change. If the CCPx pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state. 25.3.8 CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See Section 6.
PIC16(L)F1782/3 25.
PIC16(L)F1782/3 26.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE 26.1 Master SSP (MSSP) Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc.
PIC16(L)F1782/3 The I2C interface supports the following modes and features: • • • • • • • • • • • • • Master mode Slave mode Byte NACKing (Slave mode) Limited multi-master support 7-bit and 10-bit addressing Start and Stop interrupts Interrupt masking Clock stretching Bus collision detection General call address matching Address masking Address Hold and Data Hold modes Selectable SDA hold times Figure 26-2 is a block diagram of the I2C interface module in Master mode.
PIC16(L)F1782/3 FIGURE 26-3: MSSP BLOCK DIAGRAM (I2C™ SLAVE MODE) Internal Data Bus Read Write SSPBUF Reg SCL Shift Clock SSPSR Reg SDA MSb LSb SSPMSK Reg Match Detect Addr Match SSPADD Reg Start and Stop bit Detect 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 26.2 SPI Mode Overview The Serial Peripheral Interface (SPI) bus is a synchronous serial data communication bus that operates in Full-Duplex mode. Devices communicate in a master/slave environment where the master device initiates the communication. A slave device is controlled through a Chip Select known as Slave Select.
PIC16(L)F1782/3 FIGURE 26-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION SPI Master SCK SCK SDO SDI SDI SDO General I/O General I/O SS General I/O SCK SDI SDO SPI Slave #1 SPI Slave #2 SS SCK SDI SDO SPI Slave #3 SS 26.2.1 SPI MODE REGISTERS The MSSP module has five registers for SPI mode operation.
PIC16(L)F1782/3 26.2.2 SPI MODE OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON1<5:0> and SSPSTAT<7:6>).
PIC16(L)F1782/3 26.2.3 SPI MASTER MODE The master can initiate the data transfer at any time because it controls the SCK line. The master determines when the slave (Processor 2, Figure 26-5) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input).
PIC16(L)F1782/3 26.2.4 26.2.5 SPI SLAVE MODE In Slave mode, the data is transmitted and received as external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCK pin. The Idle state is determined by the CKP bit of the SSPCON1 register.
PIC16(L)F1782/3 FIGURE 26-7: SPI DAISY-CHAIN CONNECTION SPI Master SCK SCK SDO SDI SDI SPI Slave #1 SDO General I/O SS SCK SDI SPI Slave #2 SDO SS SCK SDI SPI Slave #3 SDO SS FIGURE 26-8: SLAVE SELECT SYNCHRONOUS WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF Shift register SSPSR and bit count are reset SSPBUF to SSPSR SDO bit 7 bit 6 bit 7 SDI bit 6 bit 0 bit 0 bit 7 bit 7 Input Sample SSPIF Interrupt Flag SSPSR to SSPBUF 2011-2012 Microchip Technolo
PIC16(L)F1782/3 FIGURE 26-9: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 0 bit 7 Input Sample SSPIF Interrupt Flag SSPSR to SSPBUF Write Collision detection active FIGURE 26-10: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b
PIC16(L)F1782/3 26.2.6 SPI OPERATION IN SLEEP MODE In SPI Master mode, module clocks may be operating at a different speed than when in Full-Power mode; in the case of the Sleep mode, all clocks are halted. Special care must be taken by the user when the MSSP clock is much faster than the system clock. In Slave mode, when MSSP interrupts are enabled, after the master completes sending data, an MSSP interrupt will wake the controller from Sleep.
PIC16(L)F1782/3 26.3 I2C MODE OVERVIEW The Inter-Integrated Circuit Bus (I2C) is a multi-master serial data communication bus. Devices communicate in a master/slave environment where the master devices initiate the communication. A Slave device is controlled through addressing. VDD SCL The I2C bus specifies two signal connections: • Serial Clock (SCL) • Serial Data (SDA) Both the SCL and SDA connections are bidirectional open-drain lines, each requiring pull-up resistors for the supply voltage.
PIC16(L)F1782/3 When one device is transmitting a logical one, or letting the line float, and a second device is transmitting a logical zero, or holding the line low, the first device can detect that the line is not a logical one. This detection, when used on the SCL line, is called clock stretching. Clock stretching gives slave devices a mechanism to control the flow of data. When this detection is used on the SDA line, it is called arbitration.
PIC16(L)F1782/3 26.4 I2C MODE OPERATION TABLE 26-2: All MSSP I2C communication is byte oriented and shifted out MSb first. Six SFR registers and two interrupt flags interface the module with the PIC® microcontroller and user software. Two pins, SDA and SCL, are exercised by the module to communicate with other external I2C devices. 26.4.1 BYTE FORMAT All communication in I2C is done in 9-bit segments. A byte is sent from a master to a slave or vice-versa, followed by an Acknowledge bit sent back.
PIC16(L)F1782/3 26.4.5 26.4.7 START CONDITION The I2C specification defines a Start condition as a transition of SDA from a high to a low state while SCL line is high. A Start condition is always generated by the master and signifies the transition of the bus from an Idle to an Active state. Figure 26-10 shows wave forms for Start and Stop conditions. A Restart is valid any time that a Stop would be valid. A master can issue a Restart if it wishes to hold the bus after terminating the current transfer.
PIC16(L)F1782/3 26.4.9 26.5 ACKNOWLEDGE SEQUENCE The 9th SCL pulse for any transferred byte in I2C is dedicated as an Acknowledge. It allows receiving devices to respond back to the transmitter by pulling the SDA line low. The transmitter must release control of the line during this time to shift in the response. The Acknowledge (ACK) is an active-low signal, pulling the SDA line low indicated to the transmitter that the device has received the transmitted data and is ready to receive more.
PIC16(L)F1782/3 26.5.2 26.5.2.2 SLAVE RECEPTION When the R/W bit of a matching received address byte is clear, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register and acknowledged. When the overflow condition exists for a received address, then not Acknowledge is given. An overflow condition is defined as either bit BF of the SSPSTAT register is set, or bit SSPOV of the SSPCON1 register is set.
DS41579D-page 284 Preliminary SSPOV BF SSPIF S 1 A7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 9 ACK 1 D7 2 D6 4 D4 5 D3 6 D2 7 D1 SSPBUF is read Cleared by software 3 D5 Receiving Data 8 9 2 D6 First byte of data is available in SSPBUF 1 D0 ACK D7 4 D4 5 D3 6 D2 7 D1 SSPOV set because SSPBUF is still full. ACK is not sent.
2011-2012 Microchip Technology Inc. Preliminary CKP SSPOV BF SSPIF 1 SCL S A7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 9 R/W=0 ACK SEN 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 CKP is written to ‘1’ in software, releasing SCL SSPBUF is read Cleared by software Clock is held low until CKP is set to ‘1’ 1 D7 Receive Data 9 ACK SEN 3 D5 4 D4 5 D3 First byte of data is available in SSPBUF 6 D2 7 D1 SSPOV set because SSPBUF is still full. ACK is not sent.
DS41579D-page 286 Preliminary P S ACKTIM CKP ACKDT BF SSPIF S Receiving Address 1 3 5 6 7 8 ACK the received byte Slave software clears ACKDT to Address is read from SSBUF If AHEN = 1: SSPIF is set 4 ACKTIM set by hardware on 8th falling edge of SCL When AHEN=1: CKP is cleared by hardware and SCL is stretched 2 A7 A6 A5 A4 A3 A2 A1 Receiving Data 9 2 3 4 5 6 7 ACKTIM cleared by hardware in 9th rising edge of SCL When DHEN=1: CKP is cleared by hardware on 8th falling edge of
2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 26.5.3 SLAVE TRANSMISSION 26.5.3.2 7-bit Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register, and an ACK pulse is sent by the slave on the ninth bit. A master device can transmit a read request to a slave, and then clock data out of the slave. The list below outlines what software for a slave will need to do to accomplish a standard transmission.
2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 26.5.3.3 7-bit Transmission with Address Hold Enabled Setting the AHEN bit of the SSPCON3 register enables additional clock stretching and interrupt generation after the 8th falling edge of a received matching address. Once a matching address has been clocked in, CKP is cleared and the SSPIF interrupt is set. Figure 26-18 displays a standard waveform of a 7-bit Address Slave Transmission with AHEN enabled. 1. 2. Bus starts Idle.
2011-2012 Microchip Technology Inc. Preliminary D/A R/W ACKTIM CKP ACKSTAT ACKDT BF SSPIF S Receiving Address 2 4 5 6 7 8 Slave clears ACKDT to ACK address ACKTIM is set on 8th falling edge of SCL 9 ACK When R/W = 1; CKP is always cleared after ACK R/W = 1 Received address is read from SSPBUF 3 When AHEN = 1; CKP is cleared by hardware after receiving matching address.
PIC16(L)F1782/3 26.5.4 26.5.5 SLAVE MODE 10-BIT ADDRESS RECEPTION This section describes a standard sequence of events for the MSSP module configured as an I2C slave in 10-bit Addressing mode. Figure 26-19 is used as a visual reference for this description. This is a step by step process of what must be done by slave software to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. Bus starts Idle.
2011-2012 Microchip Technology Inc.
DS41579D-page 294 Preliminary ACKTIM CKP UA ACKDT BF 2 1 5 0 6 A9 7 A8 Set by hardware on 9th falling edge 4 1 ACKTIM is set by hardware on 8th falling edge of SCL If when AHEN = 1; on the 8th falling edge of SCL of an address byte, CKP is cleared Slave software clears ACKDT to ACK the received byte 3 1 8 R/W = 0 9 ACK UA 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 Update to SSPADD is not allowed until 9th falling edge of SCL SSPBUF can be read anytime before the next received byt
2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 26.5.6 26.5.6.2 CLOCK STRETCHING Clock stretching occurs when a device on the bus holds the SCL line low effectively pausing communication. The slave may stretch the clock to allow more time to handle data or prepare a response for the master device. A master device is not concerned with stretching as anytime it is active on the bus and not transferring data it is stretching. Any stretching done by a slave is invisible to the master software and handled by the hardware that generates SCL.
PIC16(L)F1782/3 26.5.8 GENERAL CALL ADDRESS SUPPORT In 10-bit Address mode, the UA bit will not be set on the reception of the general call address. The slave will prepare to receive the second byte as data, just as it would in 7-bit mode. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master device. The exception is the general call address which can address all devices.
PIC16(L)F1782/3 26.6 I2C Master Mode 26.6.1 I2C MASTER MODE OPERATION Master mode is enabled by setting and clearing the appropriate SSPM bits in the SSPCON1 register and by setting the SSPEN bit. In Master mode, the SDA and SCK pins must be configured as inputs. The MSSP peripheral hardware will override the output driver TRIS controls when necessary to drive the pins low. The master device generates all of the serial clock pulses and the Start and Stop conditions.
PIC16(L)F1782/3 26.6.2 CLOCK ARBITRATION Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, releases the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<7:0> and begins counting.
PIC16(L)F1782/3 26.6.4 I2C MASTER MODE START CONDITION TIMING Note 1: If at the beginning of the Start condition, the SDA and SCL pins are already sampled low, or if during the Start condition, the SCL line is sampled low before the SDA line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag, BCLIF, is set, the Start condition is aborted and the I2C module is reset into its Idle state.
PIC16(L)F1782/3 26.6.5 I2C MASTER MODE REPEATED SSPCON2 register will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDA pin held low. As soon as a Start condition is detected on the SDA and SCL pins, the S bit of the SSPSTAT register will be set. The SSPIF bit will not be set until the Baud Rate Generator has timed out.
PIC16(L)F1782/3 26.6.6 I2C MASTER MODE TRANSMISSION 26.6.6.3 Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPBUF register. This action will set the Buffer Full flag bit, BF and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted.
2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 26.6.7 I2C MASTER MODE RECEPTION 26.6.7.4 Master mode reception is enabled by programming the Receive Enable bit, RCEN bit of the SSPCON2 register. Note: The MSSP module must be in an Idle state before the RCEN bit is set or the RCEN bit will be disregarded. The Baud Rate Generator begins counting and on each rollover, the state of the SCL pin changes (high-to-low/low-to-high) and data is shifted into the SSPSR.
2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 26.6.8 ACKNOWLEDGE SEQUENCE TIMING 26.6.9 A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN bit of the SSPCON2 register. At the end of a receive/transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and counts down to ‘0’.
PIC16(L)F1782/3 FIGURE 26-31: STOP CONDITION RECEIVE OR TRANSMIT MODE SCL = 1 for TBRG, followed by SDA = 1 for TBRG after SDA sampled high. P bit (SSPSTAT<4>) is set. Write to SSPCON2, set PEN PEN bit (SSPCON2<2>) is cleared by hardware and the SSPIF bit is set Falling edge of 9th clock TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period. 26.6.10 SLEEP OPERATION 26.6.
PIC16(L)F1782/3 FIGURE 26-32: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCL = 0 SDA line pulled low by another source SDA released by master Sample SDA. While SCL is high, data does not match what is driven by the master. Bus collision has occurred. SDA SCL Set bus collision interrupt (BCLIF) BCLIF DS41579D-page 308 Preliminary 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 26.6.13.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDA or SCL are sampled low at the beginning of the Start condition (Figure 26-32). SCL is sampled low before SDA is asserted low (Figure 26-33). During a Start condition, both the SDA and the SCL pins are monitored. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 26-34).
PIC16(L)F1782/3 FIGURE 26-34: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF.
PIC16(L)F1782/3 26.6.13.2 Bus Collision During a Repeated Start Condition If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, Figure 26-35). If SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time.
PIC16(L)F1782/3 26.6.13.3 Bus Collision During a Stop Condition The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPADD and counts down to 0. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 26-37).
PIC16(L)F1782/3 TABLE 26-3: Name APFCON SUMMARY OF REGISTERS ASSOCIATED WITH I2C™ OPERATION Bit 7 Bit 6 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: SDOSEL SCKSEL SDISEL TXSEL RXSEL CCP2SEL 119 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 84 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 85 PIE2 OSFIE C2IE C1IE EEIE BCL1IE — C3IE CCP2IE 86 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 88 PIR2 OSFIF C2IF C1IF EEIF BCL1IF
PIC16(L)F1782/3 26.7 BAUD RATE GENERATOR The MSSP module has a Baud Rate Generator available for clock generation in both I2C and SPI Master modes. The Baud Rate Generator (BRG) reload value is placed in the SSPADD register (Register 26-6). When a write occurs to SSPBUF, the Baud Rate Generator will automatically begin counting down. clock line. The logic dictating when the reload signal is asserted depends on the mode the MSSP is being operated in.
PIC16(L)F1782/3 26.
PIC16(L)F1782/3 REGISTER 26-1: bit 0 SSPSTAT: SSP STATUS REGISTER (CONTINUED) BF: Buffer Full Status bit Receive (SPI and I2 C modes): 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit (I2 C mode only): 1 = Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full 0 = Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty DS41579D-page 316 Preliminary 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 REGISTER 26-2: SSPCON1: SSP CONTROL REGISTER 1 R/C/HS-0/0 R/C/HS-0/0 R/W-0/0 R/W-0/0 WCOL SSPOV SSPEN CKP R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SSPM<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared bit 7 WCOL: Write Collision Detect bit Master mode: 1
PIC16(L)F1782/3 REGISTER 26-3: SSPCON2: SSP CONTROL REGISTER 2 R/W-0/0 R-0/0 R/W-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/W/HS-0/0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware S = User set bit 7 GCEN: General Call Enable bit (i
PIC16(L)F1782/3 REGISTER 26-4: SSPCON3: SSP CONTROL REGISTER 3 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only)(3) 1 = Indicates the I2C bus is in
PIC16(L)F1782/3 REGISTER 26-5: R/W-1/1 SSPMSK: SSP MASK REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 MSK<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 MSK<7:1>: Mask bits 1 = The received address bit n is compared to SSPADD to detect I2C address match 0 = The received address bit
PIC16(L)F1782/3 27.
PIC16(L)F1782/3 FIGURE 27-2: EUSART RECEIVE BLOCK DIAGRAM SPEN CREN RX/DT pin Baud Rate Generator Data Recovery FOSC SPBRGH SPBRGL Multiplier x4 x16 x64 SYNC 1 X 0 0 0 BRGH X 1 1 0 0 BRG16 X 1 0 1 0 Stop (8) ••• 7 1 LSb 0 START RX9 ÷n BRG16 +1 RSR Register MSb Pin Buffer and Control RCIDL OERR n FERR RX9D RCREG Register 8 FIFO Data Bus RCIF RCIE Interrupt The operation of the EUSART module is controlled through three registers: • Transmit Status and Control (TXSTA) •
PIC16(L)F1782/3 27.1 EUSART Asynchronous Mode 27.1.1.2 The EUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a VOH mark state which represents a ‘1’ data bit, and a VOL space state which represents a ‘0’ data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission.
PIC16(L)F1782/3 27.1.1.5 TSR Status 27.1.1.7 The TRMT bit of the TXSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied to this bit, so the user has to poll this bit to determine the TSR status. Note: 27.1.1.6 1. 2. 3.
PIC16(L)F1782/3 FIGURE 27-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREG TX/CK pin Start bit bit 0 bit 1 Word 1 1 TCY TXIF bit (Transmit Buffer Reg. Empty Flag) bit 7/8 Stop bit Start bit Word 2 bit 0 1 TCY Word 1 Transmit Shift Reg. TRMT bit (Transmit Shift Reg. Empty Flag) Note: Word 2 Word 1 BRG Output (Shift Clock) Word 2 Transmit Shift Reg. This timing diagram shows two consecutive transmissions.
PIC16(L)F1782/3 27.1.2 EUSART ASYNCHRONOUS RECEIVER 27.1.2.2 The Asynchronous mode is typically used in RS-232 systems. The receiver block diagram is shown in Figure 27-2. The data is received on the RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate.
PIC16(L)F1782/3 27.1.2.4 Receive Framing Error 27.1.2.7 Each character in the receive FIFO buffer has a corresponding framing error Status bit. A framing error indicates that a Stop bit was not seen at the expected time. The framing error status is accessed via the FERR bit of the RCSTA register. The FERR bit represents the status of the top unread character in the receive FIFO. Therefore, the FERR bit must be read before reading the RCREG.
PIC16(L)F1782/3 27.1.2.8 Asynchronous Reception Set-up: 27.1.2.9 1. Initialize the SPBRGH, SPBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 27.4 “EUSART Baud Rate Generator (BRG)”). 2. Clear the ANSEL bit for the RX pin (if applicable). 3. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. 4. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register.
PIC16(L)F1782/3 TABLE 27-2: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page C2OUTSEL CC1PSEL SDOSEL SCKSEL SDISEL TXSEL RXSEL CCP2SEL 119 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 333 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 84 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 85 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF Name APFCON BAUDCON INTCON RCREG R
PIC16(L)F1782/3 27.2 Clock Accuracy with Asynchronous Operation The factory calibrates the internal oscillator block output (INTOSC). However, the INTOSC frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. The first (preferred) method uses the OSCTUNE register to adjust the INTOSC output.
PIC16(L)F1782/3 27.
PIC16(L)F1782/3 REGISTER 27-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pi
PIC16(L)F1782/3 REGISTER 27-3: BAUDCON: BAUD RATE CONTROL REGISTER R-0/0 R-1/1 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-b
PIC16(L)F1782/3 27.4 EUSART Baud Rate Generator (BRG) EXAMPLE 27-1: The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit of the BAUDCON register selects 16-bit mode.
PIC16(L)F1782/3 TABLE 27-3: BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula 0 8-bit/Asynchronous FOSC/[64 (n+1)] 0 1 8-bit/Asynchronous 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous 1 x 16-bit/Synchronous SYNC BRG16 BRGH 0 0 0 1 Legend: FOSC/[4 (n+1)] x = Don’t care, n = value of SPBRGH, SPBRGL register pair TABLE 27-4: Name BAUDCON RCSTA FOSC/[16 (n+1)] SUMMARY OF REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR Bi
PIC16(L)F1782/3 TABLE 27-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 32.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 20.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 18.432 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 — — — — — — — — — — — — 1200 — — — 1221 1.73 255 1200 0.00 239 1200 0.00 143 2400 2404 0.16 207 2404 0.
PIC16(L)F1782/3 TABLE 27-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 8.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 4.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 3.6864 MHz Actual Rate FOSC = 1.000 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 300 1200 — — — — — — — 1202 — 0.16 — 207 — 1200 — 0.00 — 191 300 1202 0.16 0.16 207 51 2400 2404 0.16 207 2404 0.
PIC16(L)F1782/3 TABLE 27-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 1200 300.0 1200 0.00 0.00 26666 6666 300.0 1200 0.00 -0.01 16665 4166 300.0 1200 0.00 0.00 15359 3839 300.0 1200 0.00 0.00 9215 2303 2400 2400 0.01 3332 2400 0.02 2082 2400 0.00 1919 2400 0.
PIC16(L)F1782/3 27.4.1 AUTO-BAUD DETECT The EUSART module supports automatic detection and calibration of the baud rate. and SPBRGL registers are clocked at 1/8th the BRG base clock rate. The resulting byte measurement is the average bit time when clocked at full speed. Note 1: If the WUE bit is set with the ABDEN bit, auto-baud detection will occur on the byte following the Break character (see Section 27.4.3 “Auto-Wake-up on Break”).
PIC16(L)F1782/3 27.4.2 AUTO-BAUD OVERFLOW 27.4.3.1 During the course of automatic baud detection, the ABDOVF bit of the BAUDCON register will be set if the baud rate counter overflows before the fifth rising edge is detected on the RX pin. The ABDOVF bit indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the SPBRGH:SPBRGL register pair. After the ABDOVF bit has been set, the counter continues to count until the fifth rising edge is detected on the RX pin.
PIC16(L)F1782/3 FIGURE 27-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Auto Cleared Bit set by user WUE bit RX/DT Line RCIF Note 1: Cleared due to User Read of RCREG The EUSART remains in idle while the WUE bit is set.
PIC16(L)F1782/3 27.4.4 BREAK CHARACTER SEQUENCE The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. A Break character consists of a Start bit, followed by 12 ‘0’ bits and a Stop bit. To send a Break character, set the SENDB and TXEN bits of the TXSTA register. The Break character transmission is then initiated by a write to the TXREG. The value of data written to TXREG will be ignored and all ‘0’s will be transmitted.
PIC16(L)F1782/3 27.5 EUSART Synchronous Mode Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line.
PIC16(L)F1782/3 FIGURE 27-10: SYNCHRONOUS TRANSMISSION RX/DT pin bit 0 bit 1 Word 1 bit 2 bit 7 bit 0 bit 1 Word 2 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit TXEN bit ‘1’ Note: ‘1’ Sync Master mode, SPBRGL = 0, continuous transmission of two 8-bit words.
PIC16(L)F1782/3 27.5.1.5 Synchronous Master Reception Data is received at the RX/DT pin. The RX/DT pin output driver is automatically disabled when the EUSART is configured for synchronous master receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCSTA register) or the Continuous Receive Enable bit (CREN of the RCSTA register).
PIC16(L)F1782/3 FIGURE 27-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RCREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
PIC16(L)F1782/3 27.5.2 SYNCHRONOUS SLAVE MODE The following bits are used to configure the EUSART for synchronous slave operation: • • • • • SYNC = 1 CSRC = 0 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 1. 2. 3. 4. Setting the SYNC bit of the TXSTA register configures the device for synchronous operation. Clearing the CSRC bit of the TXSTA register configures the device as a slave.
PIC16(L)F1782/3 27.5.2.3 EUSART Synchronous Slave Reception 27.5.2.4 The operation of the Synchronous Master and Slave modes is identical (Section 27.5.1.5 “Synchronous Master Reception”), with the following exceptions: • Sleep • CREN bit is always set, therefore the receiver is never idle • SREN bit, which is a “don’t care” in Slave mode 1. 2. 3. A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep.
PIC16(L)F1782/3 27.6 EUSART Operation During Sleep The EUSART will remain active during Sleep only in the Synchronous Slave mode. All other modes require the system clock and therefore cannot generate the necessary signals to run the Transmit or Receive Shift registers during Sleep. Synchronous Slave mode uses an externally generated clock to run the Transmit and Receive Shift registers. 27.6.
PIC16(L)F1782/3 NOTES: DS41579D-page 350 Preliminary 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 28.0 IN-CIRCUIT SERIAL PROGRAMMING™ (ICSP™) 28.3 ICSP™ programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can be done after the assembly process, allowing the device to be programmed with the most recent firmware or a custom firmware. Five pins are needed for ICSP™ programming: • ICSPCLK • ICSPDAT • MCLR/VPP • VDD • VSS Connection to a target device is typically done through an ICSP™ header.
PIC16(L)F1782/3 FIGURE 28-2: PICkit™ PROGRAMMER STYLE CONNECTOR INTERFACE Pin 1 Indicator Pin Description* 1 = VPP/MCLR 1 2 3 4 5 6 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT 5 = ICSPCLK 6 = No Connect * FIGURE 28-3: The 6-pin header (0.100" spacing) accepts 0.025" square pins.
PIC16(L)F1782/3 29.0 INSTRUCTION SET SUMMARY 29.1 Read-Modify-Write Operations • Byte Oriented • Bit Oriented • Literal and Control Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction, or the destination designator ‘d’. A read operation is performed on a register even if the instruction writes to that register.
PIC16(L)F1782/3 FIGURE 29-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 OPCODE d f (FILE #) 0 d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 OPCODE b (BIT #) f (FILE #) 0 b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE 8 7 0 k (literal) k = 8-bit immediate value CALL and GOTO instructions only 13 11 10 OPCODE 0 k (literal
PIC16(L)F1782/3 TABLE 29-3: PIC16(L)F1782/3 INSTRUCTION SET Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ADDWFC ANDWF ASRF LSLF LSRF CLRF CLRW COMF DECF INCF IORWF MOVF MOVWF RLF RRF SUBWF SUBWFB SWAPF XORWF f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d f, d Add W and f Add with Carry W and f AND W with f Arithmetic Right Shift Logical Left Shift Logical Right Shift Clear f C
PIC16(L)F1782/3 TABLE 29-3: PIC16(L)F1782/3 INSTRUCTION SET (CONTINUED) Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes CONTROL OPERATIONS 2 2 2 2 2 2 2 2 BRA BRW CALL CALLW GOTO RETFIE RETLW RETURN k – k – k k k – Relative Branch Relative Branch with W Call Subroutine Call Subroutine with W Go to address Return from interrupt Return with literal in W Return from Subroutine CLRWDT NOP OPTION RESET SLEEP TRIS – – – – – f Clear Watchdog Timer No Operation Load
PIC16(L)F1782/3 29.2 Instruction Descriptions ADDFSR Add Literal to FSRn ANDLW AND literal with W Syntax: [ label ] ADDFSR FSRn, k Syntax: [ label ] ANDLW Operands: -32 k 31 n [ 0, 1] Operands: 0 k 255 Operation: FSR(n) + k FSR(n) Status Affected: None Description: The signed 6-bit literal ‘k’ is added to the contents of the FSRnH:FSRnL register pair. k Operation: (W) .AND.
PIC16(L)F1782/3 BCF Bit Clear f Syntax: [ label ] BCF BTFSC f,b Bit Test f, Skip if Clear Syntax: [ label ] BTFSC f,b 0 f 127 0b7 Operands: 0 f 127 0b7 Operands: Operation: 0 (f) Operation: skip if (f) = 0 Status Affected: None Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared. Description: If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed.
PIC16(L)F1782/3 CALL Call Subroutine CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0 k 2047 Operands: None Operation: (PC)+ 1 TOS, k PC<10:0>, (PCLATH<6:3>) PC<14:11> Operation: Status Affected: None 00h WDT 0 WDT prescaler, 1 TO 1 PD Description: Call Subroutine. First, return address (PC + 1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH.
PIC16(L)F1782/3 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f) - 1 (destination); skip if result = 0 Operation: (f) + 1 (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in the W register.
PIC16(L)F1782/3 LSLF Logical Left Shift MOVF f {,d} Move f Syntax: [ label ] LSLF Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f<7>) C (f<6:0>) dest<7:1> 0 dest<0> Operation: (f) (dest) Status Affected: C, Z Description: The contents of register ‘f’ are shifted one bit to the left through the Carry flag. A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’, the result is placed in W.
PIC16(L)F1782/3 MOVIW Move INDFn to W Syntax: [ label ] MOVIW ++FSRn [ label ] MOVIW --FSRn [ label ] MOVIW FSRn++ [ label ] MOVIW FSRn-[ label ] MOVIW k[FSRn] MOVLP Operands: n [0,1] mm [00,01, 10, 11] -32 k 31 Operation: INDFn W Effective address is determined by • FSR + 1 (preincrement) • FSR - 1 (predecrement) • FSR + k (relative offset) After the Move, the FSR value will be either: • FSR + 1 (all increments) • FSR - 1 (all decrements) • Unchanged Status Affected: Syntax: [ label ]
PIC16(L)F1782/3 NOP MOVWI Move W to INDFn Syntax: [ label ] MOVWI ++FSRn [ label ] MOVWI --FSRn [ label ] MOVWI FSRn++ [ label ] MOVWI FSRn-[ label ] MOVWI k[FSRn] Operands: Operation: Status Affected: n [0,1] mm [00,01, 10, 11] -32 k 31 W INDFn Effective address is determined by • FSR + 1 (preincrement) • FSR - 1 (predecrement) • FSR + k (relative offset) After the Move, the FSR value will be either: • FSR + 1 (all increments) • FSR - 1 (all decrements) Unchanged None Syntax: [ label ]
PIC16(L)F1782/3 RETFIE Return from Interrupt Syntax: [ label ] RETFIE RETURN Return from Subroutine Syntax: [ label ] None RETURN Operands: None Operands: Operation: TOS PC, 1 GIE Operation: TOS PC Status Affected: None Status Affected: None Description: Description: Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction.
PIC16(L)F1782/3 SUBLW Subtract W from literal Syntax: [ label ] RRF Rotate Right f through Carry Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 k 255 Operation: k - (W) W) Operation: See description below Status Affected: C, DC, Z Status Affected: C Description: Description: The contents of register ‘f’ are rotated one bit to the right through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register.
PIC16(L)F1782/3 SWAPF Swap Nibbles in f XORLW Exclusive OR literal with W Syntax: [ label ] Syntax: [ label ] Operands: 0 f 127 d [0,1] Operation: SWAPF f,d (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) XORLW k Operands: 0 k 255 Operation: (W) .XOR. k W) Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register.
PIC16(L)F1782/3 30.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings(†) Ambient temperature under bias....................................................................................................... -40°C to +125°C Storage temperature ........................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS, PIC16F1782/3 .......................................................................... -0.
PIC16(L)F1782/3 PIC16F1782/3 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C FIGURE 30-1: VDD (V) 5.5 2.7 2.3 0 10 4 16 32 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 30-1 for each Oscillator mode’s supported frequencies. PIC16LF1782/3 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C VDD (V) FIGURE 30-2: 3.6 2.7 1.
PIC16(L)F1782/3 FIGURE 30-3: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE 125 ± 5% 85 Temperature (°C) ± 3% 60 ± 2% 25 0 -20 -40 1.8 ± 5% 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 30.1 DC Characteristics: PIC16(L)F1782/3-I/E (Industrial, Extended) PIC16LF1782/3 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F1782/3 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param. No. D001 Sym. VDD D001 D002* VDR D002* Characteristic Min. Typ† Max.
PIC16(L)F1782/3 FIGURE 30-4: POR AND POR REARM WITH SLOW RISING VDD VDD VPOR VPORR VSS NPOR POR REARM VSS TVLOW(3) Note 1: 2: 3: TPOR(2) When NPOR is low, the device is held in Reset. TPOR 1 s typical. TVLOW 2.7 s typical. 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 30.2 DC Characteristics: PIC16(L)F1782/3-I/E (Industrial, Extended) PIC16LF1782/3 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F1782/3 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Min. Typ† Max.
PIC16(L)F1782/3 30.2 DC Characteristics: PIC16(L)F1782/3-I/E (Industrial, Extended) (Continued) PIC16LF1782/3 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F1782/3 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Min. Typ† Max.
PIC16(L)F1782/3 30.2 DC Characteristics: PIC16(L)F1782/3-I/E (Industrial, Extended) (Continued) PIC16LF1782/3 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F1782/3 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Min. Typ† Max.
PIC16(L)F1782/3 30.3 DC Characteristics: PIC16(L)F1782/3-I/E (Power-Down) PIC16LF1782/3 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F1782/3 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Max. +85°C Max. +125°C Units — 0.05 1.0 8.0 A — 0.08 2.0 9.0 A 3.0 — 0.3 3 11 A 2.
PIC16(L)F1782/3 30.3 DC Characteristics: PIC16(L)F1782/3-I/E (Power-Down) (Continued) PIC16LF1782/3 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F1782/3 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Typ† Max. +85°C — 0.05 — 0.08 — — Min.
PIC16(L)F1782/3 30.4 DC Characteristics: PIC16(L)F1782/3-I/E DC CHARACTERISTICS Param No. Sym. VIL Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Min. Typ† Max. Units Conditions Input Low Voltage I/O PORT: D034 — — 0.8 V 4.5V VDD 5.5V — — 0.15 VDD V 1.8V VDD 4.5V with Schmitt Trigger buffer — — 0.2 VDD V 2.0V VDD 5.5V with I2C™ levels — — 0.
PIC16(L)F1782/3 30.4 DC Characteristics: PIC16(L)F1782/3-I/E (Continued) DC CHARACTERISTICS Param No. Sym. Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Min. Typ† Max.
PIC16(L)F1782/3 30.5 Memory Programming Requirements Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C DC CHARACTERISTICS Param No. Sym. Characteristic Min. Typ† Max. Units Conditions Program Memory Programming Specifications D110 VIHH Voltage on MCLR/VPP/RE3 pin 8.0 — 9.0 V D111 IDDP Supply Current during Programming — — 10 mA D112 VDD for Bulk Erase 2.
PIC16(L)F1782/3 30.6 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. TH01 TH02 TH03 TH04 TH05 Sym. Characteristic Typ. Units JA Thermal Resistance Junction to Ambient 60 C/W 28-pin SPDIP package 80 C/W 28-pin SOIC package 90 C/W 28-pin SSOP package 27.5 C/W 28-pin UQFN 4x4mm package 27.5 C/W 28-pin QFN 6x6mm package 31.
PIC16(L)F1782/3 30.7 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2.
PIC16(L)F1782/3 30.8 AC Characteristics: PIC16(L)F1782/3-I/E FIGURE 30-6: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1/CLKIN OS02 OS04 OS04 OS03 OSC2/CLKOUT (LP,XT,HS Modes) OSC2/CLKOUT (CLKOUT Mode) TABLE 30-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. OS01 Sym.
PIC16(L)F1782/3 TABLE 30-2: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. OS08 Sym. Characteristic HFOSC Internal Calibrated HFINTOSC Frequency(2) OS08A MFOSC Internal Calibrated MFINTOSC Frequency(2) OS09 LFOSC Internal LFINTOSC Frequency OS10* TIOSC ST HFINTOSC Wake-up from Sleep Start-up Time MFINTOSC Wake-up from Sleep Start-up Time Freq. Tolerance Min. Typ† Max. Units ±2% ±3% — — 16.0 16.
PIC16(L)F1782/3 FIGURE 30-7: Cycle CLKOUT AND I/O TIMING Write Fetch Q1 Q4 Read Execute Q2 Q3 FOSC OS12 OS11 OS20 OS21 CLKOUT OS19 OS16 OS13 OS18 OS17 I/O pin (Input) OS14 OS15 I/O pin (Output) New Value Old Value OS18, OS19 DS41579D-page 384 Preliminary 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 TABLE 30-4: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. OS11 OS12 Sym.
PIC16(L)F1782/3 FIGURE 30-9: BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD VBOR and VHYST VBOR (Device in Brown-out Reset) (Device not in Brown-out Reset) 37 Reset 33(1) (due to BOR) Note 1: 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’. 2 ms delay if PWRTE = 0. DS41579D-page 386 Preliminary 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 TABLE 30-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. Sym. Characteristic MCLR Pulse Width (low) Min. Typ† Max. Units Conditions 2 5 — — — — s s VDD = 3.3-5V, -40°C to +85°C VDD = 3.3-5V 10 16 27 ms VDD = 3.
PIC16(L)F1782/3 FIGURE 30-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 49 47 TMR0 or TMR1 TABLE 30-6: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. 40* Sym. TT0H Characteristic T0CKI High Pulse Width Min.
PIC16(L)F1782/3 FIGURE 30-11: CAPTURE/COMPARE/PWM TIMINGS (CCP) CCPx (Capture mode) CC01 CC02 CC03 Note: Refer to Figure 30.5 for load conditions. TABLE 30-7: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP) Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param Sym. No. Characteristic CC01* TccL CCPx Input Low Time No Prescaler CC02* TccH CCPx Input High Time No Prescaler With Prescaler With Prescaler CC03* TccP * † CCPx Input Period Min.
PIC16(L)F1782/3 TABLE 30-8: PIC16(L)F1782/3 ADC CONVERTER (ADC) 12-BIT DIFFERENTIAL CHARACTERISTICS: Operating Conditions VDD = 3V, Temp. = 25°C, Single-ended 2 s TAD, VREF+ = 3V, VREF- = VSS Param Sym. No. Characteristic Min. Typ† Max. Units Conditions AD01 NR Resolution — — 10 bit AD02 EIL Integral Error — ±1 ±1.6 LSb AD03 EDL Differential Error — ±1 ±1.
PIC16(L)F1782/3 FIGURE 30-12: PIC16(L)F1782/3 ADC CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO AD134 1 Tcy (TOSC/2(1)) AD131 Q4 AD130 ADC CLK 7 ADC Data 6 5 4 3 2 1 0 NEW_DATA OLD_DATA ADRES 1 Tcy ADIF GO Sample DONE Sampling Stopped AD132 Note 1: If the ADC clock source is selected as RC, a time of TCY is added before the ADC clock starts. This allows the SLEEP instruction to be executed.
PIC16(L)F1782/3 TABLE 30-10: OPERATIONAL AMPLIFIER (OPA) Standard Operating Conditions (unless otherwise stated): VDD = 3.0 Temperature 25°C, High-Power Mode DC CHARACTERISTICS Param No. Symbol OPA01 GBWP Parameters Min Typ Max Units Gain Bandwidth Product — 4.
PIC16(L)F1782/3 TABLE 30-12: DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS Operating Conditions: VDD = 3V, Temperature = 25°C (unless otherwise stated). Param No. Sym. Characteristics Min. Typ. Max. Units DAC01* CLSB Step Size — VDD/256 — V DAC02* CACC Absolute Accuracy — — 1.5 LSb DAC03* CR Unit Resistor Value (R) — 600 — DAC04* CST Settling Time(1) — — 10 s Comments * These parameters are characterized but not tested.
PIC16(L)F1782/3 TABLE 30-14: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param. No. Symbol Characteristic US125 TDTV2CKL SYNC RCV (Master and Slave) Data-hold before CK (DT hold time) US126 TCKL2DTL DS41579D-page 394 Data-hold after CK (DT hold time) Preliminary Min. Max. Units 10 — ns 15 — ns Conditions 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 FIGURE 30-16: SPI MASTER MODE TIMING (CKE = 0, SMP = 0) SS SP70 SCK (CKP = 0) SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 bit 6 - - - - - -1 MSb SDO LSb SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 30-5 for load conditions.
PIC16(L)F1782/3 FIGURE 30-18: SPI SLAVE MODE TIMING (CKE = 0) SS SP70 SCK (CKP = 0) SP83 SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 MSb SDO LSb bit 6 - - - - - -1 SP77 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 30-5 for load conditions.
PIC16(L)F1782/3 TABLE 30-15: SPI MODE REQUIREMENTS Param No. Symbol Characteristic SP70* TSSL2SCH, SS to SCK or SCK input TSSL2SCL Min. Typ† Max. Units Conditions TCY — — ns SP71* TSCH SCK input high time (Slave mode) TCY + 20 — — ns SP72* TSCL SCK input low time (Slave mode) TCY + 20 — — ns 100 — — ns 100 — — ns 3.0-5.5V — 10 25 ns 1.8-5.
PIC16(L)F1782/3 TABLE 30-16: I2C™ BUS START/STOP BITS REQUIREMENTS Param No. Symbol Characteristic SP90* TSU:STA Start condition SP91* THD:STA SP92* TSU:STO SP93 THD:STO Stop condition Typ 4700 — Max. Units — Setup time 400 kHz mode 600 — — Start condition 100 kHz mode 4000 — — Hold time 400 kHz mode 600 — — Stop condition 100 kHz mode 4700 — — Setup time Hold time * 100 kHz mode Min.
PIC16(L)F1782/3 TABLE 30-17: I2C™ BUS DATA REQUIREMENTS Param. No. Symbol SP100* THIGH Characteristic Clock high time Min. Max. Units 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz SSP module SP101* TLOW Clock low time 1.5TCY — 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a minimum of 10 MHz 1.
PIC16(L)F1782/3 NOTES: DS41579D-page 400 Preliminary 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 31.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range. Unless otherwise noted, all graphs apply to both the L and LF devices.
PIC16(L)F1782/3 FIGURE 31-1: IPD BASE, PIC16LF1782/3 ONLY 450 400 Max: 85°C + 3 Typical: 25°C Max. 350 IPD (nA (nA) 300 250 200 150 100 Typical 50 0 16 1.6 1 1.8 8 2 2.0 0 2 2.2 2 2 2.4 4 2 2.6 6 2 2.8 8 3 3.0 0 3 3.2 2 3 3.4 4 3 3.6 6 3 3.8 8 VDD (V) IPD BASE, LOW-POWER SLEEP MODE (VREGPM = 1), PIC16F1782/3 ONLY FIGURE 31-2: 600 Max: 85°C + 3 Typical: 25°C 500 Max. IPD (nA (nA) 400 300 200 Typical 100 0 23 2.3 2 5 2.5 2 7 2.7 2 9 2.9 3 1 3.1 3 3 3.3 3 5 3.5 3 7 3.
PIC16(L)F1782/3 FIGURE 31-3: IPD, WATCH DOG TIMER (WDT), PIC16LF1782/3 ONLY 1200 Max: 85°C + 3 Typical: 25°C 1000 Max. IPD (nA) 800 600 Typical 400 200 0 16 1.6 1.8 18 2.0 20 2.2 22 2.4 24 2.6 26 2.8 28 3.0 30 3.2 32 3.4 34 3.6 36 3.8 38 VDD (V) FIGURE 31-4: IPD, WATCH DOG TIMER (WDT), PIC16F1782/3 ONLY 1200 Max: 85°C + 3 Typical: 25°C 1000 Max. IPD (nA (nA) 800 600 Typical 400 200 0 1 5 1.5 2 0 2.0 2 5 2.5 3 0 3.0 3 5 3.5 4 0 4.0 4 5 4.5 5 0 5.0 5 5 5.5 6 0 6.
PIC16(L)F1782/3 FIGURE 31-5: IPD, BROWN-OUT RESET (BOR), PIC16LF1782/3 ONLY 11 Max: 85°C + 3 Typical: 25°C 10 Max. IPD ((μA) 9 Typical 8 7 6 5 4 2 4 2.4 2 6 2.6 2 8 2.8 3 0 3.0 3 2 3.2 3 4 3.4 3 6 3.6 3 8 3.8 5 4 5.4 5 9 5.9 VDD (V) FIGURE 31-6: IPD, BROWN-OUT RESET (BOR), PIC16F1782/3 ONLY 14 Max: 85°C + 3 Typical: 25°C 12 Max. IPD (μA) 10 Typical 8 6 4 2 0 2 4 2.4 2 9 2.9 3 4 3.4 3 9 3.9 4 4 4.4 4 9 4.
PIC16(L)F1782/3 FIGURE 31-7: IPD, LOW-POWER BROWN-OUT RESET (LPBOR), PIC16LF1782/3 ONLY 800 Max: 85°C + 3 Typical: 25°C 700 Max. 600 IPD (nA (nA) 500 400 300 Typical 200 100 0 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 31-8: IPD, LOW-POWER BROWN-OUT RESET (LPBOR), PIC16F1782/3 ONLY 700 Max: 85°C + 3 Typical: 25°C 600 Max. IPD (nA (nA) 500 400 300 Typical 200 100 0 2 0 2.0 2 5 2.5 3 0 3.0 3 5 3.5 4 0 4.0 4 5 4.5 5 0 5.0 5 5 5.5 6 0 6.
PIC16(L)F1782/3 FIGURE 31-9: IPD, TIMER1 OSCILLATOR, FOSC = 32 kHz, PIC16LF1782/3 ONLY 6 Max: 85°C + 3 Typical: 25°C 5 Max. IPD (μA (μA) 4 3 2 Typical 1 0 16 1.6 1 8 1.8 2 0 2.0 2 2 2.2 2 4 2.4 2 6 2.6 2 8 2.8 3 0 3.0 3 2 3.2 3 4 3.4 3 6 3.6 3 8 3.8 VDD (V) FIGURE 31-10: IPD, TIMER1 OSCILLATOR, FSC = 32 kHz, PIC16F1782/3 ONLY 12 Max: 85°C + 3 Typical: 25°C 10 Max. IPD (μA) 8 6 Typical 4 2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.
PIC16(L)F1782/3 FIGURE 31-11: VOH vs. IOH OVER TEMPERATURE, VDD = 5.0V, PIC16F1782/3 ONLY 6 Graph represents 3 Limits 5 VOH (V) 4 -40°C 3 125°C 2 Typical 1 0 -30 -25 -20 -15 -10 -5 0 IOH (mA) FIGURE 31-12: VOL vs. IOL OVER TEMPERATURE, VDD = 5.0V, PIC16F1782/3 ONLY 5 Graph represents 3 Limits 4 VOL (V) 3 -40°C 2 Typical 125°C 1 0 0 10 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 FIGURE 31-13: VOH vs. IOH OVER TEMPERATURE, VDD = 3.0V 3.5 Graph represents 3 Limits 3.0 VOH (V) 2.5 2.0 1.5 125°C Typical 1.0 -40°C 0.5 0.0 -14 -12 -10 -8 -6 -4 -2 0 IOH (mA) FIGURE 31-14: VOL vs. IOL OVER TEMPERATURE, VDD = 3.0V 3.0 Graph represents 3 Limits 2.5 VOL (V) 2.0 -40°C Typical 1.5 125°C 1.0 0.5 0.0 0 5 10 15 20 25 30 IOL (mA) DS41579D-page 408 Preliminary 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 FIGURE 31-15: VOH vs. IOH OVER TEMPERATURE, VDD = 1.8V, PIC16LF1782/3 ONLY 2.0 Graph represents 3 Limits 1.8 1.6 VOH (V) 1.4 1.2 125°C 1.0 0.8 Typical -40°C 0.6 0.4 0.2 0.0 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0 IOH (mA) FIGURE 31-16: VOL vs. IOL OVER TEMPERATURE, VDD = 1.8V, PIC16LF1782/3 ONLY 1.8 Graph represents 3 Limits 1.6 1.4 Vol (V) 1.2 1 125°C Typical 0.8 -40°C 0.6 0.4 0.2 0 0 1 2 3 4 5 6 7 8 9 10 IOL (mA) 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 FIGURE 31-17: POR RELEASE VOLTAGE 1.7 1.68 Max. 1.66 Voltage (V) 1.64 Typical 1.62 Min. 1.6 1.58 1.56 Max: Typical + 3 Typical: 25°C Min: Typical - 3 1.54 1.52 1.5 -40 -20 0 20 40 60 80 100 120 Temperature (°C) FIGURE 31-18: POR REARM VOLTAGE, NORMAL POWER MODE (VREGPM1 = 0), PIC16F1782/3 ONLY 1.54 Max: Typical + 3 Typical: 25°C Min: Typical - 3 1.52 1.5 Max. Voltage (V) 1.48 1.46 1.44 Typical 1.42 1.4 Min. 1.38 1.36 1.
PIC16(L)F1782/3 FIGURE 31-19: BROWN-OUT RESET VOLTAGE, LOW TRIP POINT (BORV = 1), PIC16LF1782/3 ONLY 2.10 Max: Typical + 3 Min: Typical - 3 2.05 2.00 Voltage (V) Max. 1.95 1.90 Min. 1.85 1.80 1.75 1.70 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 31-20: BROWN-OUT RESET HYSTERESIS, LOW TRIP POINT (BORV = 1), PIC16LF1782/3 ONLY 70 Max. 60 Voltage (mV) 50 Typical 40 30 Min.
PIC16(L)F1782/3 FIGURE 31-21: BROWN-OUT RESET VOLTAGE, HIGH TRIP POINT (BORV = 0) 2.90 2.85 Max: Typical + 3 Min: Typical - 3 2.80 Max. Voltage (V) 2.75 2.70 2.65 Min. 2.60 2.55 2.50 2.45 2.40 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 31-22: BROWN-OUT RESET HYSTERESIS, HIGH TRIP POINT (BORV = 0) 90 80 Max. 70 Voltage (mV) 60 50 Typical 40 30 20 Max: Typical + 3 Typical: 25°C Min: Typical - 3 Min.
PIC16(L)F1782/3 FIGURE 31-23: LPBOR RESET VOLTAGE 2.45 2.40 Max. 2.35 Max: Typical + 3 Typical: 25°C Min: Typical - 3 2.30 Voltage (V) 2.25 2.20 Typical 2.15 2.10 2.05 2.00 1.95 Min. 1.90 1.85 1.80 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 31-24: LPBOR RESET HYSTERESIS 60 Max. 50 Voltage (mV) 40 Typical 30 20 Min.
PIC16(L)F1782/3 FIGURE 31-25: WDT TIME-OUT PERIOD 24 22 Max. Time (mS) 20 18 Typical 16 14 Min. Max: Typical + 3 (-40°C to +125°C) Typical; statistical mean @ 25°C Min: Typical - 3 (-40°C to +125°C) 12 10 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 Voltage (V) FIGURE 31-26: PWRT PERIOD 110 100 Max. Time (mS) 90 80 Typical 70 Min. 60 Max: Typical + 3 (-40°C to +125°C) Typical; statistical mean @ 25°C Min: Typical - 3 (-40°C to +125°C) 50 40 1.5 2 2.5 3 3.5 4 4.5 5 5.
PIC16(L)F1782/3 FIGURE 31-27: ADC 12-BIT MODE, SINGE-ENDED DNL, VDD = 3.0V, TAD = 4S, 25°C 1.5 DNL (LSb) 1.0 0.5 0.0 -0.5 -1.0 -1.5 0 512 1024 1536 2048 2560 3072 3584 4096 Output Code FIGURE 31-28: ADC 12-BIT MODE, SINGE-ENDED DNL, VDD = 5.5V, TAD = 4S, 25°C 1.0 DNL (LSb) 0.5 0.0 -0.5 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096 Output Code 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 FIGURE 31-29: COMPARATOR HYSTERESIS, NORMAL SPEED MODE (CxSP = 1), VDD = 1.8V, TYPICAL MEASURED VALUES, PIC16LF1782/3 ONLY 70 Typical 125° Hysteresis (mV) 65 60 55 Typical 25°C 50 45 Typical -40°C 40 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Common Mode Voltage (V) FIGURE 31-30: COMPARATOR HYSTERESIS, NORMAL SPEED MODE (CxSP = 1), VDD = 3.6V, TYPICAL MEASURED VALUES 45 Typical -40°C Hysteresis (mV) 40 Typical 25°C 35 Typical 125° 30 25 0 0.5 1 1.5 2 2.5 3 3.
PIC16(L)F1782/3 FIGURE 31-31: COMPARATOR HYSTERESIS, NORMAL SPEED MODE (CxSP = 1), VDD = 5.5V, TYPICAL MEASURED VALUES, PIC16F1782/3 ONLY 55 Typical -40°C Hysteresis (mV) 50 45 Typical 25°C 40 35 30 Typical 125° 25 0 1 2 3 4 5 6 Common Mode Voltage (V) FIGURE 31-32: COMPARATOR RESPONSE TIME OVER TEMPERATURE, NORMAL POWER MODE (CxSP = 1), TYPICAL MEASURED VALUES 120.0 110.0 Time (nS) 100.0 125°C 90.0 80.0 -40°C 70.0 60.0 50.0 25°C 40.0 1.5 2 2.5 3 3.5 4 4.5 5 5.
PIC16(L)F1782/3 NOTES: DS41579D-page 418 Preliminary 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 32.0 DEVELOPMENT SUPPORT 32.
PIC16(L)F1782/3 32.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 32.
PIC16(L)F1782/3 32.7 MPLAB SIM Software Simulator 32.9 The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC16(L)F1782/3 32.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 32.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
PIC16(L)F1782/3 33.0 PACKAGING INFORMATION 33.1 Package Marking Information 28-Lead SPDIP (.300”) Example PIC16F1782 -I/SP e3 1204017 28-Lead SOIC (7.50 mm) Example XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX PIC16F1782 -I/SO e3 1204017 YYWWNNN 28-Lead SSOP (5.30 mm) Example PIC16F1782 -I/SS e3 1204017 Legend: XX...
PIC16(L)F1782/3 Package Marking Information (Continued) 28-Lead QFN (6x6 mm) Example PIN 1 PIN 1 XXXXXXXX XXXXXXXX YYWWNNN -I/ML e3 120417 28-Lead UQFN (4x4x0.5 mm) Example PIN 1 PIN 1 Legend: XX...
PIC16(L)F1782/3 33.2 Package Details The following sections give the technical details of the packages.
PIC16(L)F1782/3 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41579D-page 426 Preliminary 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41579D-page 428 Preliminary 2011-2012 Microchip Technology Inc.
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PIC16(L)F1782/3 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41579D-page 430 Preliminary 2011-2012 Microchip Technology Inc.
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PIC16(L)F1782/3 /HDG 3ODVWLF 4XDG )ODW 1R /HDG 3DFNDJH 0/ ± [ PP %RG\ >4)1@ ZLWK PP &RQWDFW /HQJWK 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ DS41579D-page 432 Preliminary 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41579D-page 434 Preliminary 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 APPENDIX A: DATA SHEET REVISION HISTORY Revision A (04/2011) Original release. Revision B (06/2011) Revised Section 18.0; Revised Table 30-8; Add Operational Amplifier Table. Revision C (03/2012) Electrical Specifications update. Revision D (11/2012) Revised: Table 5-4, Section 6.2.1.3, 9.0, Table 15-1 (LDO), Figure 16-1, Section 17.1.6, 17.2.3, 20.7, 24.1, 24.1.1-24.1.3, 24.2.7, 24.2.8, 24.3.4.1, 24.3.11, 24.8.1.1-24.8.1.3; Register 24.
PIC16(L)F1782/3 NOTES: DS41579D-page 440 Preliminary 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 INDEX A A/D Specifications............................................................ 390 Absolute Maximum Ratings .............................................. 367 AC Characteristics Industrial and Extended ............................................ 382 Load Conditions ........................................................ 381 ACKSTAT ......................................................................... 302 ACKSTAT Status Flag ......................................................
PIC16(L)F1782/3 XT ....................................................................... 59 Internal Modes ............................................................ 62 HFINTOSC.......................................................... 63 Internal Oscillator Clock Switch Timing............... 65 LFINTOSC .......................................................... 63 MFINTOSC ......................................................... 63 Clock Switching.......................................................
PIC16(L)F1782/3 FVRCON (Fixed Voltage Reference Control) Register ..... 145 I I2C Mode (MSSP) Acknowledge Sequence Timing................................ 306 Bus Collision During a Repeated Start Condition ................... 311 During a Stop Condition.................................... 312 Effects of a Reset...................................................... 307 I2C Clock Rate w/BRG.............................................. 314 Master Mode Operation ...............................................
PIC16(L)F1782/3 MSSPx I2C Mode ................................................................... 278 I2C Mode Operation .................................................. 280 O ODCONA Register ............................................................ 124 ODCONB Register ............................................................ 130 ODCONC Register............................................................ 134 OPA Module Associated Registers ................................................
PIC16(L)F1782/3 PSMCxPRL Register ........................................................ 251 PSMCxPRS Register ........................................................ 245 PSMCxREBS Register...................................................... 242 PSMCxSTR0 Register ...................................................... 254 PSMCxSTR1 Register ...................................................... 256 PSMCxTMRH Register ..................................................... 248 PSMCxTMRL Register..........
PIC16(L)F1782/3 TRISE (Tri-State PORTE) ......................................... 137 TXSTA (Transmit Status and Control) ...................... 331 VREGCON (Voltage Regulator Control) ..................... 96 WDTCON (Watchdog Timer Control)........................ 101 WPUA (Weak Pull-up PORTA) ................................. 123 WPUB (Weak Pull-up PORTB) ................................. 129 WPUC (Weak Pull-up PORTC)................................. 134 RESET .............................................
PIC16(L)F1782/3 Wake-up from Interrupt ............................................... 94 Timing Diagrams and Specifications PLL Clock.................................................................. 383 Timing Parameter Symbology........................................... 381 Timing Requirements I2C Bus Data ............................................................. 399 I2C Bus Start/Stop Bits ............................................. 398 SPI Mode ...................................................
PIC16(L)F1782/3 NOTES: DS41579D-page 448 Preliminary 2011-2012 Microchip Technology Inc.
PIC16(L)F1782/3 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC16(L)F1782/3 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PIC16(L)F1782/3 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. [X](1) PART NO.
PIC16(L)F1782/3 NOTES: DS41579D-page 452 Preliminary 2011-2012 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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