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Table Of Contents

High-Performance RISC CPU:
Flexible Oscillator Structure:
Special Microcontroller Features:
Extreme Low-Power Management PIC16LF1526/7 with XLP:
Analog Features:
Peripheral Features:
PIC16(L)F151X/152X Family Types
- TABLE 1: 64-Pin Device Allocation Table (PIC16(L)F1526/7)
- TABLE 1: 64-Pin Device Allocation Table (PIC16(L)F1526/7) (Continued)
Table of Contents
Most Current Data Sheet
Errata
Customer Notification System
1.0 Device Overview
- TABLE 1-1: Device Peripheral Summary
- FIGURE 1-1: PIC16(L)F1526/7 Block Diagram
- TABLE 1-2: PIC16(L)F1526/7 Pinout Description
2.0 Enhanced Mid-Range CPU
- FIGURE 2-1: Core Block Diagram
- 2.1 Automatic Interrupt Context Saving
- 2.2 16-level Stack with Overflow and Underflow
- 2.3 File Select Registers
- 2.4 Instruction Set
3.0 Memory Organization
- 3.1 Program Memory Organization
- 3.2 Data Memory Organization
  - 3.2.1 Core Registers
    - TABLE 3-2: Core Registers
- 3.3 Register Definitions: Status
  - Register 3-1: STATUS: STATUS Register
- 3.4 Special Function Register
- 3.5 PCL and PCLATH
- 3.6 Stack
  - 3.6.1 Accessing the Stack
  - 3.6.2 Overflow/Underflow Reset
- 3.7 Indirect Addressing
4.0 Device Configuration
- 4.1 Configuration Words
- 4.2 Register Definitions: Configuration Words
  - Register 4-1: CONFIG1: Configuration Word 1
  - Register 4-2: CONFIG2: Configuration Word 2
- 4.3 Code Protection
  - 4.3.1 Program Memory Protection
- 4.4 Write Protection
- 4.5 User ID
- 4.6 Device ID and Revision ID
  - Register 4-3: DEVID: Device ID Register
5.0 Oscillator Module (with Fail-Safe Clock Monitor)
- 5.1 Overview
  - FIGURE 5-1: Simplified PIC® MCU Clock Source Block Diagram
- 5.2 Clock Source Types
  - 5.2.1 External Clock Sources
  - 5.2.2 Internal Clock Sources
    - FIGURE 5-7: Internal Oscillator Switch Timing
- 5.3 Clock Switching
- 5.4 Two-Speed Clock Start-up Mode
- 5.5 Fail-Safe Clock Monitor
- 5.6 Register Definitions: Oscillator Control
6.0 Resets
- FIGURE 6-1: Simplified Block Diagram of On-Chip Reset Circuit
- 6.1 Power-On Reset (POR)
  - 6.1.1 Power-up Timer (PWRT)
- 6.2 Brown-Out Reset (BOR)
- 6.3 Register Definitions: BOR Control
  - Register 6-1: BORCON: Brown-out Reset Control Register
- 6.4 Low-Power Brown-Out Reset (LPBOR)
  - 6.4.1 Enabling LPBOR
- 6.5 MCLR
- 6.6 Watchdog Timer (WDT) Reset
- 6.7 RESET Instruction
- 6.8 Stack Overflow/Underflow Reset
- 6.9 Programming Mode Exit
- 6.10 Power-up Timer
- 6.11 Start-up Sequence
  - FIGURE 6-3: Reset Start-up Sequence
- 6.12 Determining the Cause of a Reset
  - TABLE 6-3: Reset Status Bits and Their Significance
  - TABLE 6-4: Reset Condition for Special Registers
- 6.13 Power Control (PCON) Register
- 6.14 Register Definitions: Power Control
  - Register 6-2: PCON: Power Control Register
  - TABLE 6-5: Summary of Registers Associated with Resets
7.0 Interrupts
- FIGURE 7-1: Interrupt Logic
- 7.1 Operation
- 7.2 Interrupt Latency
  - FIGURE 7-2: Interrupt Latency
  - FIGURE 7-3: INT Pin Interrupt Timing
- 7.3 Interrupts During Sleep
- 7.4 INT Pin
- 7.5 Automatic Context Saving
- 7.6 Register Definitions: Interrupt Control
8.0 Power-Down Mode (Sleep)
- 8.1 Wake-up from Sleep
  - 8.1.1 Wake-up Using Interrupts
    - FIGURE 8-1: Wake-up from Sleep through Interrupt
- 8.2 Low-Power Sleep Mode
  - 8.2.1 Sleep Current vs. Wake-up Time
  - 8.2.2 Peripheral Usage in Sleep
- 8.3 Register Definitions: Voltage Regulator Control
  - Register 8-1: VREGCON: Voltage Regulator Control Register(1)
  - TABLE 8-1: Summary of Registers Associated with Power-down Mode
9.0 Low Dropout (LDO) Voltage Regulator
- TABLE 9-1: VCAPEN Select Bit
- TABLE 9-2: Summary of Configuration Word with LDO
10.0 Watchdog Timer (WDT)
- FIGURE 10-1: Watchdog Timer Block Diagram
- 10.1 Independent Clock Source
- 10.2 WDT Operating Modes
- 10.3 Time-out Period
- 10.4 Clearing the WDT
- 10.5 Operation During Sleep
  - TABLE 10-2: WDT Clearing Conditions
- 10.6 Register Definitions: Watchdog Control
11.0 Flash Program Memory Control
- 11.1 PMADRL and PMADRH Registers
  - 11.1.1 PMCON1 and PMCON2 Registers
- 11.2 Flash Program Memory Overview
- 11.3 Modifying Flash Program Memory
  - FIGURE 11-7: Flash Program Memory Modify Flowchart
- 11.4 User ID, Device ID and Configuration Word Access
  - TABLE 11-2: User ID, Device ID and Configuration Word Access (CFGS = 1)
  - EXAMPLE 11-4: Configuration Word and Device ID Access
- 11.5 Write Verify
  - FIGURE 11-8: Flash Program Memory Verify Flowchart
- 11.6 Register Definitions: Flash Program Memory Control
12.0 I/O Ports
- TABLE 12-1: Port Availability per Device
- FIGURE 12-1: Generic I/O Port Operation
- 12.1 Alternate Pin Function
- 12.2 Register Definitions: Alternate Pin Function Control
  - Register 12-1: APFCON: Alternate Pin Function Control Register
- 12.3 PORTA Registers
- 12.4 Register Definitions: PORTA
- 12.5 PORTB Registers
- 12.6 Register Definitions: PORTB
- 12.7 PORTC Registers
- 12.8 Register Definitions: PORTC
- 12.9 PORTD Registers
- 12.10 Register Definitions: PORTD
- 12.11 PORTE Registers
- 12.12 Register Definitions: PORTE
- 12.13 PORTF Registers
- 12.14 Register Definitions: PORTF
- 12.15 PORTG Registers
- 12.16 Register Definitions: PORTG
13.0 Interrupt-On-Change
- 13.1 Enabling the Module
- 13.2 Individual Pin Configuration
- 13.3 Interrupt Flags
- 13.4 Clearing Interrupt Flags
  - EXAMPLE 13-1: Clearing Interrupt Flags (PORTA Example)
- 13.5 Operation in Sleep
  - FIGURE 13-1: Interrupt-On-Change Block Diagram
- 13.6 Register Definitions: Interrupt-on-change Control
14.0 Fixed Voltage Reference (FVR)
- 14.1 Independent Gain Amplifiers
- 14.2 FVR Stabilization Period
  - FIGURE 14-1: Voltage Reference Block Diagram
  - TABLE 14-1: Peripherals Requiring the Fixed Voltage Reference (FVR)
- 14.3 Register Definitions: FVR Control
  - Register 14-1: FVRCON: Fixed Voltage Reference Control Register
  - TABLE 14-2: Summary of Registers Associated with Fixed Voltage Reference
15.0 Temperature Indicator Module
- 15.1 Circuit Operation
  - EQUATION 15-1: Vout Ranges
  - FIGURE 15-1: Temperature Circuit Diagram
- 15.2 Minimum Operating Vdd
  - TABLE 15-1: Recommended Vdd vs. Range
- 15.3 Temperature Output
- 15.4 ADC Acquisition Time
  - TABLE 15-2: Summary of Registers Associated with the Temperature Indicator
16.0 Analog-to-Digital Converter (ADC) Module
- FIGURE 16-1: ADC Block Diagram
- 16.1 ADC Configuration
- 16.2 ADC Operation
- 16.3 Register Definitions: ADC Control
- 16.4 ADC Acquisition Requirements
17.0 Timer0 Module
- 17.1 Timer0 Operation
- 17.2 Register Definitions: Option Register
  - Register 17-1: OPTION_REG: OPTION Register
  - TABLE 17-1: Summary of Registers Associated with Timer0
18.0 Timer1/3/5 Module with Gate Control
- FIGURE 18-1: Timer1/3/5 Block Diagram
- FIGURE 18-2: Timer1/3/5 Clock Source Diagram
- 18.1 Timer1/3/5 Operation
  - TABLE 18-1: Timer1/3/5 Enable Selections
- 18.2 Clock Source Selection
  - 18.2.1 Internal Clock Source
  - 18.2.2 External Clock Source
    - TABLE 18-2: Clock Source Selections
- 18.3 Timer1/3/5 Prescaler
- 18.4 Timer1/3/5 Oscillator
- 18.5 Timer1/3/5 Operation in Asynchronous Counter Mode
  - 18.5.1 Reading and Writing Timer1/3/5 in Asynchronous Counter Mode
- 18.6 Timer1/3/5 Gate
- 18.7 Timer1/3/5 Interrupt
- 18.8 Timer1/3/5 Operation During Sleep
- 18.9 ECCP/CCP Capture/Compare Time Base
- 18.10 ECCP/CCP Special Event Trigger
- 18.11 Register Definitions: Timer1/3/5 Control
  - Register 18-1: TxCON: Timer1/3/5 Control Register
- 18.12 Register Definitions: Timer1/3/5 Gate Control
  - Register 18-2: TxGCON: Timer1/3/5 Gate Control Register
  - 18.12.1 Alternate Pin Locations
    - TABLE 18-5: Summary of Registers Associated with Timer1/3/5
19.0 Timer2/4/6/8/10 Modules
- FIGURE 19-1: Timer2/4/6/8/10 Block Diagram
- 19.1 Timer2/4/6/8/10 Operation
- 19.2 Timer2/4/6/8/10 Interrupt
- 19.3 Timer2/4/6/8/10 Output
- 19.4 Timer2/4/6/8/10 Operation During Sleep
- 19.5 Register Definitions: Timer2/4/6/8/10 Control
  - Register 19-1: TxCON: Timer2/Timer4/Timer6/Timer8/Timer10 Control Register
  - TABLE 19-1: Summary of Registers Associated with Timer2/4/6/8/10
20.0 Capture/Compare/PWM Modules
- 20.1 Capture Mode
- 20.2 Compare Mode
- 20.3 PWM Overview
- 20.4 Register Definitions: ECCP Control
21.0 Master Synchronous Serial Port (MSSP1 and MSSP2) Module
- 21.1 Master SSPx (MSSPx) Module Overview
- 21.2 SPI Mode Overview
- 21.3 I2C Mode Overview
- 21.4 I2C Mode Operation
- 21.5 I2C Slave Mode Operation
- 21.6 I2C Master Mode
- 21.7 Baud Rate Generator
  - FIGURE 21-40: Baud Rate Generator Block Diagram
  - TABLE 21-4: MSSPx Clock Rate w/BRG
- 21.8 Register Definitions: MSSP Control
22.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)
- FIGURE 22-1: EUSART Transmit Block Diagram
- FIGURE 22-2: EUSART Receive Block Diagram
- 22.1 EUSART Asynchronous Mode
  - 22.1.1 EUSART Asynchronous Transmitter
  - 22.1.2 EUSART Asynchronous Receiver
    - FIGURE 22-5: Asynchronous Reception
    - TABLE 22-2: Summary of Registers Associated with Asynchronous Reception
- 22.2 Clock Accuracy with Asynchronous Operation
- 22.3 Register Definitions: EUSART Control
- 22.4 EUSART Baud Rate Generator (BRG)
- 22.5 EUSART Synchronous Mode
  - 22.5.1 Synchronous Master Mode
  - 22.5.2 Synchronous Slave Mode
    - TABLE 22-9: Summary of Registers Associated with Synchronous Slave Transmission
    - TABLE 22-10: Registers Associated with Synchronous Slave Reception
23.0 In-Circuit Serial Programming™ (ICSP™)
- 23.1 High-Voltage Programming Entry Mode
- 23.2 Low-Voltage Programming Entry Mode
- 23.3 Common Programming Interfaces
24.0 Instruction Set Summary
- 24.1 Read-Modify-Write Operations
- 24.2 Instruction Descriptions
25.0 Electrical Specifications
- Absolute Maximum Ratings(†)
- 25.1 DC Characteristics: Supply Voltage
  - FIGURE 25-4: POR and POR Rearm with Slow Rising Vdd
- 25.2 DC Characteristics: Supply Current (Idd)
- 25.3 DC Characteristics: Power-Down Currents (Ipd)
- 25.4 DC Characteristics: I/O Ports
- 25.5 Memory Programming Requirements
- 25.6 Thermal Considerations
- 25.7 Timing Parameter Symbology
  - FIGURE 25-5: Load Conditions
- 25.8 AC Characteristics: PIC16(L)F1526/7-I/E
26.0 DC and AC Characteristics Graphs and Charts
- FIGURE 26-1: Idd, LP Oscillator, Fosc = 32 kHz, PIC16LF1526 ONLY
- FIGURE 26-2: Idd, LP Oscillator, Fosc = 32 kHz, PIC16F1526/7 ONLY
- FIGURE 26-3: Idd Typical, XT and EXTRC Oscillator, PIC16LF1526 ONLY
- FIGURE 26-4: Idd Maximum, XT and EXTRC Oscillator, PIC16LF1526 ONLY
- FIGURE 26-5: Idd Typical, XT and EXTRC Oscillator, PIC16F1526/7 ONLY
- FIGURE 26-6: Idd Maximum, XT and EXTRC Oscillator, PIC16F1526/7 ONLY
- FIGURE 26-7: Idd, External Clock (ECL), Low-Power Mode, Fosc = 32 kHz, PIC16LF1526 ONLY
- FIGURE 26-8: Idd, External Clock (ECL), Low-Power Mode, Fosc = 32 kHz, PIC16F1526/7 ONLY
- FIGURE 26-9: Idd, External Clock (ECL), Low-Power Mode, Fosc = 500 kHz, PIC16LF1526 ONLY
- FIGURE 26-10: Idd, External Clock (ECL), Low-Power Mode, Fosc = 500 kHz, PIC16F1526/7 ONLY
- FIGURE 26-11: Idd Typical, External Clock (ECM), Medium-Power Mode, PIC16LF1526 ONLY
- FIGURE 26-12: Idd Maximum, External Clock (ECM), Medium-Power Mode, PIC16LF1526 ONLY
- FIGURE 26-13: Idd Typical, External Clock (ECM), Medium-Power Mode, PIC16F1526/7 ONLY
- FIGURE 26-14: Idd Maximum, External Clock (ECM), Medium-Power Mode, PIC16F1526/7 ONLY
- FIGURE 26-15: Idd Typical, External Clock (ECH), High-Power Mode, PIC16LF1526 ONLY
- FIGURE 26-16: Idd Maximum, External Clock (ECH), High-Power Mode, PIC16LF1526 ONLY
- FIGURE 26-17: Idd Typical, External Clock (ECH), High-Power Mode, PIC16F1526/7 ONLY
- FIGURE 26-18: Idd Maximum, External Clock (ECH), High-Power Mode, PIC16F1526/7 ONLY
- FIGURE 26-19: Idd, LFINTOSC, Fosc = 31 kHz, PIC16LF1526 Only
- FIGURE 26-20: Idd, LFINTOSC, Fosc = 31 kHz, PIC16F1526/7 Only
- FIGURE 26-21: Idd, MFINTOSC, Fosc = 500 kHz, PIC16LF1526 ONLY
- FIGURE 26-22: Idd, MFINTOSC, Fosc = 500 kHz, PIC16F1526/7 ONLY
- FIGURE 26-23: Idd Typical, HFINTOSC, PIC16LF1526 ONLY
- FIGURE 26-24: Idd Maximum, HFINTOSC, PIC16LF1526 ONLY
- FIGURE 26-25: Idd Typical, HFINTOSC, PIC16F1526/7 ONLY
- FIGURE 26-26: Idd Maximum, HFINTOSC, PIC16F1526/7 ONLY
- FIGURE 26-27: Idd Typical, HS OScillator, PIC16LF1526 ONLY
- FIGURE 26-28: Idd Maximum, HS Oscillator, PIC16LF1526 ONLY
- FIGURE 26-29: Idd Typical, HS Oscillator, PIC16F1526/7 ONLY
- FIGURE 26-30: Idd Maximum, HS Oscillator, PIC16F1526/7 ONLY
- FIGURE 26-31: Ipd Base, Sleep Mode, PIC16LF1526 ONly
- FIGURE 26-32: Ipd Base, Low-Power Sleep Mode, VREGPM = 1, PIC16F1526/7 ONLy
- FIGURE 26-33: Ipd, Watchdog Timer (WDT), PIC16LF1526 ONLy
- FIGURE 26-34: Ipd, Watchdog Timer (WDT), PIC16F1526/7 ONLy
- FIGURE 26-35: Ipd, Fixed Voltage Reference (FVR), PIC16LF1526 ONLy
- FIGURE 26-36: Ipd, Fixed Voltage Reference (FVR), PIC16F1526/7 ONLy
- FIGURE 26-37: Ipd, Brown-Out Reset (BOR), BORV = 1, PIC16LF1526 ONLY
- FIGURE 26-38: Ipd, Brown-Out Reset (BOR), BORV = 1, PIC16F1526/7 ONLy
- FIGURE 26-39: Ipd, Secondary Oscillator, Fosc = 32 kHz, PIC16LF1526 ONLy
- FIGURE 26-40: Ipd, Secondary Oscillator, Fosc = 32 kHz, PIC16F1526/7 ONly
- FIGURE 26-41: Voh vs. Ioh over Temperature, Vdd = 5.5V, PIC16F1526/7 ONLy
- FIGURE 26-42: Vol vs. Iol over Temperature, Vdd = 5.5V, PIC16F1526/7 ONLy
- FIGURE 26-43: Voh vs. Ioh over Temperature, Vdd = 3.0V
- FIGURE 26-44: Vol vs. Iol over Temperature, Vdd = 3.0V
- FIGURE 26-45: Voh vs. Ioh over Temperature, Vdd = 1.8V, PIC16LF1526 Only
- FIGURE 26-46: Vol vs. Iol over Temperature, Vdd = 1.8V, PIC16LF1526 Only
- FIGURE 26-47: POR Release Voltage
- FIGURE 26-48: POR Rearm Voltage, PIC16F1526/7 ONLy
- FIGURE 26-49: Brown-Out Reset Voltage, BORV = 1, PIC16LF1526 Only
- FIGURE 26-50: Brown-Out Reset Hysteresis, BORV = 1, PIC16LF1526 Only
- FIGURE 26-51: Brown-Out Reset Voltage, BORV = 1, PIC16F1526/7 Only
- FIGURE 26-52: Brown-Out Reset Hysteresis, BORV = 1, PIC16F1526/7 Only
- FIGURE 26-53: Brown-Out Reset Voltage, BORV = 0
- FIGURE 26-54: Brown-Out Reset Hysteresis, BORV = 0
- FIGURE 26-55: Low-Power Brown-Out Reset Voltage, LPBOR = 0
- FIGURE 26-56: Low-Power Brown-Out Reset Hysteresis, LPBOR = 0
- FIGURE 26-57: WDT Time-Out Period
- FIGURE 26-58: PWRT Period
- FIGURE 26-59: FVR Stabilization Period
- FIGURE 26-60: LFINTOSC Frequency Over Vdd and Temperature, PIC16LF1526 Only
- FIGURE 26-61: LFINTOSC Frequency Over Vdd and Temperature, PIC16F1526/7 Only
- FIGURE 26-62: Sleep Mode, Wake Period with HFINTOSC Source, PIC16LF1526/7 Only
- FIGURE 26-63: Low-Power Sleep Mode, Wake Period with HFINTOSC Source, VREGPM = 1, PIC16F1526/7 Only
- FIGURE 26-64: Sleep Mode, Wake Period with HFINTOSC Source, VREGPM = 0, PIC16F1526/7 Only
27.0 Development Support
- 27.1 MPLAB Integrated Development Environment Software
- 27.2 MPLAB C Compilers for Various Device Families
- 27.3 HI-TECH C for Various Device Families
- 27.4 MPASM Assembler
- 27.5 MPLINK Object Linker/ MPLIB Object Librarian
- 27.6 MPLAB Assembler, Linker and Librarian for Various Device Families
- 27.7 MPLAB SIM Software Simulator
- 27.8 MPLAB REAL ICE In-Circuit Emulator System
- 27.9 MPLAB ICD 3 In-Circuit Debugger System
- 27.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express
- 27.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express
- 27.12 MPLAB PM3 Device Programmer
- 27.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits
28.0 Packaging Information
- 28.1 Package Marking Information
- 28.2 Package Details
Appendix A: Data Sheet Revision History
INDEX
- A
- B
- C
- D
- E
- F
- I
- L
- M
- O
- P
- R
- S
- T
- U
- V
- W
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 2011-2013 Microchip Technology Inc. DS41458C-page 201

PIC16(L)F1526/7

FIGURE 21-3: MSSPX BLOCK DIAGRAM (I

2

C™ SLAVE MODE)

Read Write

SSPxSR Reg

Match Detect

SSPxADD Reg

Start and

Stop bit Detect

SSPxBUF Reg

Internal

Data Bus

Addr Match

Set, Reset

S, P bits

(SSPxSTAT Reg)

SCLx

SDAx

Shift

Clock

MSb

LSb

SSPxMSK Reg