Datasheet

 2011-2013 Microchip Technology Inc. DS41458C-page 187
PIC16(L)F1526/7
20.2.3 SOFTWARE INTERRUPT MODE
When Generate Software Interrupt mode is chosen
(CCPxM<3:0> = 1010), the CCPx module does not
assert control of the CCPx pin (see the CCPxCON
register).
20.2.4 SPECIAL EVENT TRIGGER
When Special Event Trigger mode is chosen
(CCPxM<3:0> = 1011), the CCPx module does the
following:
• Resets Timer1/3/5
• Starts an ADC conversion if ADC is enabled
The CCPx module does not assert control of the CCPx
pin in this mode.
The Special Event Trigger output of the CCP occurs
immediately upon a match between the TMRxH,
TMRxL register pair and the CCPRxH, CCPRxL regis-
ter pair. The TMRxH, TMRxL register pair is not reset
until the next rising edge of the Timer1/3/5 clock. The
Special Event Trigger output starts an ADC conversion
(if the ADC module is enabled). This allows the
CCPRxH, CCPRxL register pair to effectively provide a
16-bit programmable period register for Timer1/3/5.
Refer to
Section 16.2.5 “Special Event Trigger” for
more information.
20.2.5 COMPARE DURING SLEEP
The Compare mode is dependent upon the system
clock (F
OSC) for proper operation. Since FOSC is shut
down during Sleep mode, the Compare mode will not
function properly during Sleep.
20.2.6 ALTERNATE PIN LOCATIONS
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
register, APFCON. To determine which pins can be
moved and what their default locations are upon a
reset, see
Section 12.1 “Alternate Pin Function” for
more information.
TABLE 20-4: SPECIAL EVENT TRIGGER
Device CCPx
PIC16(L)F1526/7 CCP10
Note 1: The Special Event Trigger from the CCP
module does not set interrupt flag bit
TMRxIF of the PIRx register.
2: Removing the match condition by
changing the contents of the CCPRxH
and CCPRxL register pair, between the
clock edge that generates the Special
Event Trigger and the clock edge that
generates the Timer1/3/5 Reset, will
preclude the Reset from occurring.