Datasheet

PIC16(L)F1526/7
DS41458C-page 178  2011-2013 Microchip Technology Inc.
19.1 Timer2/4/6/8/10 Operation
The clock input to the Timer2/4/6/8/10 modules is the
system instruction clock (F
OSC/4).
TMR2/4/6/8/10 increments from 00h on each clock
edge.
A 4-bit counter/prescaler on the clock input allows direct
input, divide-by-4 and divide-by-16 prescale options.
These options are selected by the prescaler control bits,
TxCKPS<1:0> of the TxCON register. The value of
TMR2/4/6/8/10 is compared to that of the Period
register, PR2/4/6/8/10, on each clock cycle. When the
two values match, the comparator generates a match
signal as the timer output. This signal also resets the
value of TMR2/4/6/8/10 to 00h on the next cycle and
drives the output counter/postscaler (see
Section 19.2
“Timer2/4/6/8/10 Interrupt”
).
The TMR2/4/6/8/10 and PR2/4/6/8/10 registers are
both directly readable and writable. The TMR2/4/6/8/10
register is cleared on any device Reset, whereas the
PR2/4/6/8/10 register initializes to FFh. Both the
prescaler and postscaler counters are cleared on the
following events:
• a write to the TMR2/4/6/8/10 register
• a write to the TxCON register
• Power-on Reset (POR)
• Brown-out Reset (BOR)
•MCLR
Reset
• Watchdog Timer (WDT) Reset
• Stack Overflow Reset
• Stack Underflow Reset
• RESET Instruction
19.2 Timer2/4/6/8/10 Interrupt
Timer2/4/6/8/10 can also generate an optional device
interrupt. The Timer2/4/6/8/10 output signal
(TMRx-to-PRx match) provides the input for the 4-bit
counter/postscaler. This counter generates the TMRx
match interrupt flag which is latched in TMRxIF of the
PIRx register. The interrupt is enabled by setting the
TMR2/4/6/8/10 Match Interrupt Enable bit, TMRxIE of
the PIEx register.
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, TxOUTPS<3:0>, of the TxCON register.
19.3 Timer2/4/6/8/10 Output
The unscaled output of TMR2/4/6/8/10 is available pri-
marily to the CCP modules, where it is used as a time
base for operations in PWM mode.
Timer2 can be optionally used as the shift clock source
for the MSSPx modules operating in SPI mode.
Additional information is provided in
Section 21.1
“Master SSPx (MSSPx) Module Overview”
19.4 Timer2/4/6/8/10 Operation During
Sleep
The Timer2/4/6/8/10 timers cannot be operated while
the processor is in Sleep mode. The contents of the
TMR2/4/6/8/10 and PR2/4/6/8/10 registers will remain
unchanged while the processor is in Sleep mode.
Note: TMR2/4/6/8/10 is not cleared when TxCON
is written.