Datasheet

PIC16(L)F1526/7
DS41458C-page 170  2011-2013 Microchip Technology Inc.
18.6.6 TIMER1/3/5 GATE EVENT
INTERRUPT
When Timer1/3/5 Gate Event Interrupt is enabled, it is
possible to generate an interrupt upon the completion
of a gate event. When the falling edge of TxGVAL
occurs, the TMRxGIF flag bit in the PIR1 register will be
set. If the TMRxGIE bit in the PIE1 register is set, then
an interrupt will be recognized.
The TMRxGIF flag bit operates even when the
Timer1/3/5 gate is not enabled (TMRxGE bit is
cleared).
18.7 Timer1/3/5 Interrupt
The Timer1/3/5 register pair (TMRxH:TMRxL)
increments to FFFFh and rolls over to 0000h. When
Timer1/3/5 rolls over, the Timer1/3/5 interrupt flag bit of
the PIR1 register is set. To enable the interrupt on
rollover, you must set these bits:
• TMRxON bit of the TxCON register
• TMRxIE bit of the PIE1 register
• PEIE bit of the INTCON register
• GIE bit of the INTCON register
The interrupt is cleared by clearing the TMRxIF bit in
the Interrupt Service Routine.
18.8 Timer1/3/5 Operation During Sleep
Timer1/3/5 can only operate during Sleep when setup
in Asynchronous Counter mode. In this mode, an exter-
nal crystal or clock source can be used to increment the
counter. To set up the timer to wake the device:
• TMRxON bit of the TxCON register must be set
• TMRxIE bit of the PIE1 register must be set
• PEIE bit of the INTCON register must be set
• TxSYNC
bit of the TxCON register must be set
• TMRxCS bits of the TxCON register must be
configured
• SOSCEN bit of the TxCON register must be
configured
The device will wake-up on an overflow and execute
the next instructions. If the GIE bit of the INTCON
register is set, the device will call the Interrupt Service
Routine.
Timer1/3/5 oscillator will continue to operate in Sleep
regardless of the TxSYNC
bit setting.
18.9 ECCP/CCP Capture/Compare Time
Base
The CCP module uses the TMRxH:TMRxL register pair
as the time base when operating in Capture or Com-
pare mode.
In Capture mode, the value in the TMRxH:TMRxL
register pair is copied into the CCPR1H:CCPR1L
register pair on a configured event.
In Compare mode, an event is triggered when the value
CCPR1H:CCPR1L register pair matches the value in
the TMRxH:TMRxL register pair. This event can be a
Special Event Trigger.
For more information, see
Section 20.0
“Capture/Compare/PWM Modules”
.
18.10 ECCP/CCP Special Event Trigger
When the CCP is configured to trigger a special event,
the trigger will clear the TMRxH:TMRxL register pair.
This special event does not cause a Timer1/3/5 inter-
rupt. The CCP module may still be configured to gener-
ate a CCP interrupt.
In this mode of operation, the CCPR1H:CCPR1L
register pair becomes the period register for
Timer1/3/5.
Timer1/3/5 should be synchronized and F
OSC/4 should
be selected as the clock source in order to utilize the
Special Event Trigger. Asynchronous operation of
Timer1/3/5 can cause a Special Event Trigger to be
missed.
In the event that a write to TMRxH or TMRxL coincides
with a Special Event Trigger from the CCP, the write will
take precedence.
For more information, see
Section 16.2.5 “Special
Event Trigger”
.
Note: The TMRxH:TMRxL register pair and the
TMRxIF bit should be cleared before
enabling interrupts.