PIC16(L)F1526/7 64-Pin Flash Microcontrollers with XLP Technology High-Performance RISC CPU: • C Compiler Optimized Architecture • Only 49 Instructions • Up to 28 Kbytes Linear Program Memory Addressing • Up to 1536 Bytes Linear Data Memory Addressing • Operating Speed: - DC – 20 MHz clock input @ 2.5V - DC – 16 MHz clock input @ 1.
PIC16(L)F1526/7 Note: Debug(1) XLP PIC16(L)F1512 (1) 2048 128 25 17 Y 2/1 1 1 PIC16(L)F1513 (1) 4096 256 25 17 Y 2/1 1 1 PIC16(L)F1516 (2) 8192 512 25 17 N 2/1 1 1 PIC16(L)F1517 (2) 8192 512 36 28 N 2/1 1 1 PIC16(L)F1518 (2) 16384 1024 25 17 N 2/1 1 1 PIC16(L)F1519 (2) 16384 1024 36 28 N 2/1 1 1 PIC16(L)F1526 (3) 8192 768 54 30 N 6/3 2 2 PIC16(L)F1527 (3) 16384 1536 54 30 N 6/3 2 2 Note 1: I - Debugging, Integrated on Chip; H - Debugging, available using Debug Header. 2: One pin is input-only.
PIC16(L)F1526/7 FIGURE 1: 64-PIN TQFP (10MM X 10MM) PACKAGE DIAGRAM FOR PIC16(L)F1526/7 RD0 VDD VSS RD1 RD2 RD3 RD4 RD5 RD6 RD7 RE2 RE3 RE4 RE5 RE6 RE7 TQFP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RE1 RE0 RG0 RG1 RG2 RG3 VPP/MCLR/RG5 RG4 VSS VDD RF7 RF6 RF5 RF4 RF3 RF2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIC16(L)F1526 PIC16(L)F1527 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RB0 RB1 RB2 RB3 RB4 RB5 RB6 VSS RA6 RA7 VDD RB7 RC5 RC4 RC3 RC2 RF1 RF0 AVDD AVSS RA3 RA2 RA1 RA0 VSS VDD RA5
PIC16(L)F1526/7 FIGURE 2: 64-PIN QFN (9MM X 9MM) PACKAGE DIAGRAM FOR PIC16(L)F1526/7 RD0 VDD VSS RD1 RD2 RD3 RD4 RD5 RD6 RD7 RE2 RE3 RE4 RE5 RE6 RE7 QFN 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RE1 RE0 RG0 RG1 RG2 RG3 VPP/MCLR/RG5 RG4 VSS VDD RF7 RF6 RF5 RF4 RF3 RF2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIC16(L)F1526 PIC16(L)F1527 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RB0 RB1 RB2 RB3 RB4 RB5 RB6 VSS RA6 RA7 VDD RB7 RC5 RC4 RC3 RC2 RF1 RF0 AVDD AVSS RA3 RA2 RA1 RA0 VSS VDD RA5 RA4
PIC16(L)F1526/7 CCP USART SSP AN0 AN1 AN2 AN3 — AN4 — — AN17 — — — — T0CKI T3G — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — RB1 RB2 RB3 RB4 RB5 RB6 RB7 RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 RD0 RD1 RD2 RD3 RD4 RD5 RD6 47 46 45 44 43 42 37 30 29 33 34 35 36 31 32 58 55 54 53 52 51 50 AN18 AN19 AN20 AN21 AN22 — — — — — — — — — — AN23 AN24 AN25 AN26 — — — — — — T3CKI(1) T1G/T3CKI — — SOSCO/T1CKI SOSCI — — — — — — — T5CKI — — — — — — — — — — — — — CCP2 CCP1 — — — — — — — — — — — — — — — —
PIC16(L)F1526/7 64-Pin TQFP, QFN ADC Timers CCP USART SSP Interrupt Pull-up Basic 64-PIN DEVICE ALLOCATION TABLE (PIC16(L)F1526/7) (CONTINUED) I/O TABLE 1: RE7 RF0 RF1 RF2 RF3 RF4 RF5 RF6 59 18 17 16 15 14 13 12 — AN16 AN6 AN7 AN8 AN9 AN10 AN11 — — — — — — — — CCP2(1) — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Y — — — — — — — — VCAP — — — — — — RF7 RG0 RG1 RG2 RG3 RG4 11 3 4 5 6 8 AN5 — AN15 AN14 AN13 AN12 — — — — — T5G — CCP3 — — CCP4 CCP5 — — TX2/CK2 RX2/DT2 —
PIC16(L)F1526/7 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 15 3.0 Memory Organization ..............................................................................
PIC16(L)F1526/7 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.
PIC16(L)F1526/7 1.0 DEVICE OVERVIEW The PIC16(L)F1526/7 are described within this data sheet. They are available in 64-pin packages. Figure 1-1 shows a block diagram of the PIC16(L)F1526/7 devices. Table 1-2 shows the pinout descriptions. Reference Table 1-1 for peripherals available per device.
PIC16(L)F1526/7 FIGURE 1-1: PIC16(L)F1526/7 BLOCK DIAGRAM PORTA Program Flash Memory RAM PORTB OSC2/CLKOUT Timing Generation OSC1/CLKIN PORTC CPU INTRC Oscillator PORTD (Figure 2-1) MCLR PORTE PORTF Timer0 Timer1/3/5 Timer2/4/6/8/10 EUSARTs PORTG CCP1-10 Note 1: 2: DS41458C-page 10 MSSPs Temp. Indicator ADC 10-Bit FVR See applicable chapters for more information on peripherals. See Table 1-1 for peripherals available on specific devices. 2011-2013 Microchip Technology Inc.
PIC16(L)F1526/7 TABLE 1-2: PIC16(L)F1526/7 PINOUT DESCRIPTION Name RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF+ RA4/T0CKI RA5/AN4/T3G RA6/OSC2/CLKOUT RA7/OSC1/CLKIN RB0/AN17/INT RB1/AN18 RB2/AN19 RB3/AN20 RB4/AN21/T3CKI(1) RB5/AN22/T1G/T3CKI RB6/ICSPCLK/ICDCLK RB7/ICSPDAT/ICDDAT Function Input Type Output Type RA0 TTL AN0 AN RA1 TTL AN1 AN RA2 TTL AN2 AN RA3 TTL AN3 AN — ADC Channel 3 input. VREF+ AN — ADC Positive Voltage Reference input.
PIC16(L)F1526/7 TABLE 1-2: PIC16(L)F1526/7 PINOUT DESCRIPTION (CONTINUED) Name RC0/SOSCO/T1CKI RC1/SOSCI/CCP2 RC2/CCP1 RC3/SCK1/SCL1(2) RC4/SDI1/SDA1 (2) RC5/SDO1 RC6/TX1/CK1 RC7/RX1/DT1 RDO/AN23 RD1/AN24/T5CKI RD2/AN25 RD3/AN26 RD4/SDO2 RD5/SDI2/SDA2(2) RD6/SCK2/SCL2(2) RD7/SS2 RE0/AN27 Function Input Type RC0 ST SOSCO XTAL XTAL T1CKI ST — RC1 ST SOSCI XTAL Output Type Description CMOS General purpose I/O. Timer1/3/5 oscillator connection. Timer1/3/5 clock input.
PIC16(L)F1526/7 TABLE 1-2: PIC16(L)F1526/7 PINOUT DESCRIPTION (CONTINUED) Name RE1/AN28 RE2/AN29/CCP10 RE3/CCP9 RE4/CCP8 RE5/CCP7 RE6/CCP6 RE7/CCP2(1) RF0/AN16/VCAP RF1/AN6 RF2/AN7 RF3/AN8 RF4/AN9 RF5/AN10 RF6/AN11 RF7/AN5/SS1 RG0/CCP3 RG1/AN15/TX2/CK2 RG2/AN14/RX2/DT2 Function Input Type RE1 ST AN28 AN RE2 ST AN29 AN CCP10 ST Output Type Description CMOS General purpose I/O with WPU. — ADC Channel 28 input. CMOS General purpose I/O with WPU. — ADC Channel 29 input.
PIC16(L)F1526/7 TABLE 1-2: PIC16(L)F1526/7 PINOUT DESCRIPTION (CONTINUED) Name RG3/AN13/CCP4 RG4/AN12/T5G/CCP5 RG5/MCLR/VPP Function Input Type RG3 ST AN13 AN CCP4 ST Output Type Description CMOS General purpose I/O. — ADC Channel 13 input. CMOS Capture/Compare/PWM4. RG4 ST — General purpose input. AN12 AN — ADC Channel 12 input. — Timer5 gate input. T5G ST CCP5 ST RG5 ST — General purpose input with WPU. MCLR ST — Master Clear with internal pull-up.
PIC16(L)F1526/7 2.0 ENHANCED MID-RANGE CPU Relative Addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory. This family of devices contain an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability.
PIC16(L)F1526/7 2.1 Automatic Interrupt Context Saving During interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. This saves stack space and user code. See Section 7.5 “Automatic Context Saving”, for more information. 2.2 16-level Stack with Overflow and Underflow These devices have an external stack memory 15 bits wide and 16 words deep.
PIC16(L)F1526/7 3.0 MEMORY ORGANIZATION These devices contain the following types of memory: • Program Memory - Configuration Words - Device ID - User ID - Flash Program Memory • Data Memory - Core Registers - Special Function Registers - General Purpose RAM - Common RAM 3.1 Program Memory Organization The enhanced mid-range core has a 15-bit program counter capable of addressing a 32K x 14 program memory space. Table 3-1 shows the memory sizes implemented for the PIC16(L)F1526/7 family.
PIC16(L)F1526/7 FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR PIC16(L)F1526 FIGURE 3-2: PC<14:0> CALL, CALLW RETURN, RETLW Interrupt, RETFIE PC<14:0> 15 Stack Level 0 Stack Level 1 CALL, CALLW 15 RETURN, RETLW Interrupt, RETFIE Stack Level 0 Stack Level 1 Stack Level 15 Stack Level 15 Reset Vector 0000h Reset Vector 0000h Interrupt Vector 0004h 0005h Interrupt Vector 0004h 0005h Page 0 Page 0 07FFh 0800h On-chip Program Memory PROGRAM MEMORY MAP AND STACK FOR PIC16(L)F1527 07FFh 0800h P
PIC16(L)F1526/7 3.1.1 READING PROGRAM MEMORY AS DATA There are two methods of accessing constants in program memory. The first method is to use tables of RETLW instructions. The second method is to set an FSR to point to the program memory. 3.1.1.1 RETLW Instruction The RETLW instruction can be used to provide access to tables of constants. The recommended way to create such a table is shown in Example 3-1.
PIC16(L)F1526/7 3.2 Data Memory Organization The data memory is partitioned in 32 memory banks with 128 bytes in a bank. Each bank consists of (Figure 3-3): • • • • 12 core registers 20 Special Function Registers (SFR) Up to 80 bytes of General Purpose RAM (GPR) 16 bytes of common RAM The active bank is selected by writing the bank number into the Bank Select Register (BSR). Unimplemented memory will read as ‘0’.
PIC16(L)F1526/7 3.2.1.1 STATUS Register The STATUS register, shown in Register 3-1, contains: • the arithmetic status of the ALU • the Reset status The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable.
PIC16(L)F1526/7 3.4 Special Function Register The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). The registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet. 3.4.
2011-2013 Microchip Technology Inc.
PIC16(L)F1526/7 MEMORY MAP (CONTINUED) BANK 8 400h BANK 9 480h Core Registers (Table 3-2) 40Bh ANSELF ANSELG — — — TMR3L TMR3H T3CON T3GCON TMR4 PR4 T4CON TMR5L TMR5H T5CON T5GCON TMR6 PR6 T6CON — 40Ch 40Dh 40Eh 40Fh 410h 411h 412h 413h 414h 415h 416h 417h 418h 419h 41Ah 41Bh 41Ch 41Dh 41Eh 41Fh 420h General Purpose Register 80 Bytes 2011-2013 Microchip Technology Inc.
2011-2013 Microchip Technology Inc.
PIC16(L)F1526 MEMORY MAP (CONTINUED) Bank 31 F80h Core Registers (Table 3-2) F8Bh F8Ch Unimplemented Read as ‘0’ FE3h FE4h FE5h FE6h FE7h FE8h FE9h FEAh FEBh FECh FEDh FEEh FEFh FF0h FFFh Legend: STATUS_SHAD WREG_SHAD BSR_SHAD PCLATH_SHAD FSR0L_SHAD FSR0H_SHAD FSR1L_SHAD FSR1H_SHAD — STKPTR TOSL TOSH Common RAM (Accesses 70h – 7Fh) = Unimplemented data memory locations, read as ‘0’. PIC16(L)F1526/7 DS41458C-page 26 TABLE 3-3: 2011-2013 Microchip Technology Inc.
PIC16(L)F1526/7 3.4.4 CORE FUNCTION REGISTERS SUMMARY The Core Function registers listed in Table 3-4 can be addressed from any Bank.
PIC16(L)F1526/7 TABLE 3-2: Addr Name SPECIAL FUNCTION REGISTER SUMMARY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 0 00Ch PORTA PORTA Data Latch when written: PORTA pins when read xxxx xxxx uuuu uuuu 00Dh PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 00Eh PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu 00Fh PORTD PORTD Data Latch when written: PORTD pins when read xxxx xx
PIC16(L)F1526/7 TABLE 3-2: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 2 10Ch LATA PORTA Data Latch xxxx xxxx uuuu uuuu 10Dh LATB PORTB Data Latch xxxx xxxx uuuu uuuu 10Eh LATC PORTC Data Latch xxxx xxxx uuuu uuuu 10Fh LATD PORTD Data Latch xxxx xxxx uuuu uuuu 110h PORTE Data Latch xxxx xxxx uuuu uuuu LATE 111h to — 115h Unimplemented — 116h BORCON SBOREN BORFS — —
PIC16(L)F1526/7 TABLE 3-2: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Value on POR, BOR Value on all other Resets — — Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 1111 Bank 4 20Ch — Unimplemented 20Dh WPUB 20Eh — WPUB6 Unimplemented 20Fh WPUD 210h WPUE 211h WPUB7 SSP1BUF — — WPUD7 WPUD6 WPUD5 WPUD4 WPUD3 WPUD2 WPUD1 WPUD0 1111 1111 1111 1111 WPUE7 WPUE6 WPUE5 WPUE4 WPUE3 WPUE2 WPUE1 WPUE0 1111
PIC16(L)F1526/7 TABLE 3-2: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bit 7 Bit 6 Bit 5 30Ch TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 1111 1111 1111 1111 30Dh TRISG — — —(2) TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 --11 1111 --11 1111 Bank 6 30Eh — Unimplemented — — 30Fh — Unimplemented — — 310h — Unimplemented — — 311h CCPR3L Capture/Compare/PWM Register 3 (LS
PIC16(L)F1526/7 TABLE 3-2: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 40Ch ANSELF ANSF7 ANSF6 ANSF5 ANSF4 ANSF3 40Dh ANSELG — — — ANSG4 ANSG3 Bit 2 Value on POR, BOR Value on all other Resets Bit 1 Bit 0 ANSF2 ANSF1 ANSF0 1111 1111 1111 1111 ANSG2 ANSG1 — ---1 111- ---1 111- Bank 8 40Eh — Unimplemented — — 40Fh — Unimplemented — — 410h — Unimplemented — — 411h TMR3L Holding Register for the Least Significant Byte of th
PIC16(L)F1526/7 TABLE 3-2: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on POR, BOR Value on all other Resets Unimplemented — — Unimplemented — — Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bank 10 50Ch — — 51Fh Bank 11 58Ch — — 594h 595h TMR8 Timer 8 Module Register 596h PR8 Timer 8 Period Register 597h T8CON — Unimplemented 59Ch TMR10 Timer 10 Module Register 59Dh PR10 Timer 10 Period Register 59Fh — 1111 1111 1111 1111 T8OUTPS<3:0> 598h — — 59Bh 59Eh T
PIC16(L)F1526/7 TABLE 3-2: Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets — — Bank 31 F8Ch — — FE3h Unimplemented FE4h STATUS_SHAD FE5h WREG_SHAD — — — — — Z_SHAD DC_SHAD C_SHAD Working Register Normal (Non-ICD) Shadow FE6h BSR_SHAD — FE7h PCLATH_SHAD — — — ---- -xxx ---- -uuu xxxx xxxx uuuu uuuu Bank Select Register Normal (Non-ICD) Shadow Program Counter Latch High Regist
PIC16(L)F1526/7 3.5 PCL and PCLATH 3.5.2 The Program Counter (PC) is 15 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<14:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 3-4 shows the five situations for the loading of the PC.
PIC16(L)F1526/7 3.6 Stack 3.6.1 The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack. Both registers are read/writable. TOS is split into TOSH and TOSL due to the 15-bit size of the PC. To access the stack, adjust the value of STKPTR, which will position TOSH:TOSL, then read/write to TOSH:TOSL. STKPTR is 5 bits to allow detection of overflow and underflow.
PIC16(L)F1526/7 FIGURE 3-6: ACCESSING THE STACK EXAMPLE 2 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 This figure shows the stack configuration after the first CALL or a single interrupt. If a RETURN instruction is executed, the return address will be placed in the Program Counter and the Stack Pointer decremented to the empty state (0x1F).
PIC16(L)F1526/7 FIGURE 3-8: ACCESSING THE STACK EXAMPLE 4 TOSH:TOSL 3.6.
PIC16(L)F1526/7 FIGURE 3-9: INDIRECT ADDRESSING 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x1000 0x1FFF 0x0FFF Reserved 0x2000 Linear Data Memory 0x29AF 0x29B0 FSR Address Range 0x7FFF 0x8000 Reserved 0x0000 Program Flash Memory 0xFFFF Note: 0x7FFF Not all memory regions are completely implemented. Consult device memory tables for memory limits. 2011-2013 Microchip Technology Inc.
PIC16(L)F1526/7 3.7.1 TRADITIONAL DATA MEMORY The traditional data memory is a region from FSR address 0x000 to FSR address 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers.
PIC16(L)F1526/7 3.7.2 3.7.3 LINEAR DATA MEMORY The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the banks. Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the FSR beyond one bank will go directly to the GPR memory of the next bank.
PIC16(L)F1526/7 NOTES: DS41458C-page 42 2011-2013 Microchip Technology Inc.
PIC16(L)F1526/7 4.0 DEVICE CONFIGURATION Device configuration consists of Configuration Words, Code Protection and Device ID. 4.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h. Note: The DEBUG bit in Configuration Word 2 is managed automatically by device development tools including debuggers and programmers.
PIC16(L)F1526/7 4.
PIC16(L)F1526/7 REGISTER 4-1: bit 2-0 CONFIG1: CONFIGURATION WORD 1 (CONTINUED) FOSC<2:0>: Oscillator Selection bits 111 = ECH: External Clock, High-Power mode (4-20 MHz): device clock supplied to CLKIN pin 110 = ECM: External Clock, Medium-Power mode (0.5-4 MHz): device clock supplied to CLKIN pin 101 = ECL: External Clock, Low-Power mode (0-0.
PIC16(L)F1526/7 REGISTER 4-2: CONFIG2: CONFIGURATION WORD 2 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 U-1 LVP DEBUG LPBOR BORV STVREN — bit 13 U-1 U-1 — — bit 8 U-1 — R/P-1 (1) VCAPEN U-1 U-1 — — R/P-1 R/P-1 WRT<1:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase bit 13 LVP: Low-Voltage Programming Enable bit 1 = Low-voltage programming enabled 0 = High-volta
PIC16(L)F1526/7 4.3 Code Protection Code protection allows the device to be protected from unauthorized access. Program memory protection is controlled independently. Internal access to the program memory is unaffected by any code protection setting. 4.3.1 PROGRAM MEMORY PROTECTION The entire program memory space is protected from external reads and writes by the CP bit in Configuration Words. When CP = 0, external reads and writes of program memory are inhibited and a read will return all ‘0’s.
PIC16(L)F1526/7 4.6 Device ID and Revision ID The memory location 8006h is where the Device ID and Revision ID are stored. The upper nine bits hold the Device ID. The lower five bits hold the Revision ID. See Section 11.5 “User ID, Device ID and Configuration Word Access” for more information on accessing these memory locations. Development tools, such as device programmers and debuggers, may be used to read the Device ID and Revision ID.
PIC16(L)F1526/7 5.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR) 5.1 Overview The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 5-1 illustrates a block diagram of the oscillator module. Clock sources can be supplied from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits.
PIC16(L)F1526/7 SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM FIGURE 5-1: Low Power Mode Event Switch (SCS<1:0>) Primary Oscillator OSC2 Primary Oscillator (OSC) 2 OSC1 Primary Clock 00 SOSCO/ T1CKI SOSCI Secondary Oscillator (SOSC) Secondary Clock INTOSC 01 1x Clock Switch MUX Secondary Oscillator Internal Oscillator IRCF<3:0> 4 Start-Up Osc LF-INTOSC (31.
PIC16(L)F1526/7 5.2 Clock Source Types Clock sources can be classified as external or internal. External clock sources rely on external circuitry for the clock source to function. Examples are: oscillator modules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC) mode circuits. Internal clock sources are contained within the oscillator module.
PIC16(L)F1526/7 FIGURE 5-3: QUARTZ CRYSTAL OPERATION (LP, XT OR HS MODE) FIGURE 5-4: CERAMIC RESONATOR OPERATION (XT OR HS MODE) PIC® MCU PIC® MCU OSC1/CLKIN C1 To Internal Logic Quartz Crystal C2 OSC1/CLKIN RS(1) RF(2) Sleep OSC2/CLKOUT Note 1: A series resistor (RS) may be required for quartz crystals with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M.
PIC16(L)F1526/7 5.2.1.4 5.2.1.5 Secondary Oscillator External RC Mode The secondary oscillator is a separate crystal oscillator that is associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the SOSCO and SOSCI device pins. The external Resistor-Capacitor (RC) modes support the use of an external RC circuit.
PIC16(L)F1526/7 5.2.2 INTERNAL CLOCK SOURCES The device may be configured to use the internal oscillator block as the system clock by performing one of the following actions: • Program the FOSC<2:0> bits in Configuration Words to select the INTOSC clock source, which will be used as the default system clock upon a device Reset. • Write the SCS<1:0> bits in the OSCCON register to switch the system clock source to the internal oscillator during run-time. See Section 5.
PIC16(L)F1526/7 5.2.2.3 Internal Oscillator Frequency Selection The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register. The outputs of the 16 MHz HFINTOSC and LFINTOSC connects to a postscaler and multiplexer (see Figure 5-1). The Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register select the frequency output of the internal oscillators.
PIC16(L)F1526/7 FIGURE 5-7: HFINTOSC INTERNAL OSCILLATOR SWITCH TIMING LFINTOSC (FSCM and WDT disabled) HFINTOSC Start-up Time 2-cycle Sync Running LFINTOSC IRCF <3:0> 0 0 System Clock HFINTOSC LFINTOSC (Either FSCM or WDT enabled) HFINTOSC 2-cycle Sync Running LFINTOSC 0 IRCF <3:0> 0 System Clock LFINTOSC HFINTOSC LFINTOSC turns off unless WDT or FSCM is enabled LFINTOSC Start-up Time 2-cycle Sync Running HFINTOSC IRCF <3:0> =0 0 System Clock DS41458C-page 56 2011-
PIC16(L)F1526/7 5.3 Clock Switching 5.3.3 SECONDARY OSCILLATOR The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bits of the OSCCON register. The following clock sources can be selected using the SCS bits: The secondary oscillator is a separate crystal oscillator associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the SOSCO and SOSCI device pins.
PIC16(L)F1526/7 5.4 Two-Speed Clock Start-up Mode 5.4.1 Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device.
PIC16(L)F1526/7 5.4.2 1. 2. 3. 4. 5. 6. 7. TWO-SPEED START-UP SEQUENCE 5.4.3 Wake-up from Power-on Reset or Sleep. Instructions begin execution by the internal oscillator at the frequency set in the IRCF<3:0> bits of the OSCCON register. OST enabled to count 1024 clock cycles. OST timed out, wait for falling edge of the internal oscillator. OSTS is set. System clock held low until the next falling edge of new clock (LP, XT or HS mode). System clock is switched to external clock source.
PIC16(L)F1526/7 5.5 Fail-Safe Clock Monitor 5.5.3 The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the Configuration Words. The FSCM is applicable to all external Oscillator modes (LP, XT, HS, EC, RC and secondary oscillator).
PIC16(L)F1526/7 FIGURE 5-10: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure System Clock Output Clock Monitor Output (Q) Failure Detected OSCFIF Test Note: Test Test The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. 2011-2013 Microchip Technology Inc.
PIC16(L)F1526/7 5.
PIC16(L)F1526/7 REGISTER 5-2: OSCSTAT: OSCILLATOR STATUS REGISTER R-1/q U-0 R-q/q R-0/q U-0 U-0 R-0/0 R-0/q SOSCR — OSTS HFIOFR — — LFIOFR HFIOFS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Conditional bit 7 SOSCR: Secondary Oscillator Ready bit If SOSCEN = 1: 1 = Secondary oscillator is ready 0 = Se
PIC16(L)F1526/7 NOTES: DS41458C-page 64 2011-2013 Microchip Technology Inc.
PIC16(L)F1526/7 6.0 RESETS A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 6-1. There are multiple ways to reset this device: • • • • • • • • • Power-On Reset (POR) Brown-Out Reset (BOR) Low-Power Brown-Out Reset (LPBOR) MCLR Reset WDT Reset RESET instruction Stack Overflow Stack Underflow Programming mode exit To allow VDD to stabilize, an optional power-up timer can be enabled to extend the Reset time after a BOR or POR event.
PIC16(L)F1526/7 6.1 Power-On Reset (POR) 6.2 Brown-Out Reset (BOR) The POR circuit holds the device in Reset until VDD has reached an acceptable level for minimum operation. Slow rising VDD, fast operating speeds or analog performance may require greater than minimum VDD. The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met. The BOR circuit holds the device in Reset when VDD reaches a selectable minimum level.
PIC16(L)F1526/7 FIGURE 6-2: BROWN-OUT SITUATIONS VDD VBOR Internal Reset TPWRT(1) VDD VBOR Internal Reset < TPWRT TPWRT(1) VDD VBOR Internal Reset Note 1: 6.3 TPWRT(1) TPWRT delay only if PWRTE bit is programmed to ‘0’.
PIC16(L)F1526/7 6.4 Low-Power Brown-Out Reset (LPBOR) The Low-Power Brown-Out Reset (LPBOR) is an essential part of the Reset subsystem. Refer to Figure 6-1 to see how the BOR interacts with other modules. The LPBOR is used to monitor the external VDD pin. When too low of a voltage is detected, the device is held in Reset. When this occurs, a register bit (BOR) is changed to indicate that a BOR Reset has occurred. The same bit is set for both the BOR and the LPBOR. Refer to Register 6-2. 6.4.
PIC16(L)F1526/7 FIGURE 6-3: RESET START-UP SEQUENCE VDD Internal POR TPWRT Power-Up Timer MCLR TMCLR Internal RESET Oscillator Modes External Crystal TOST Oscillator Start-Up Timer Oscillator FOSC Internal Oscillator Oscillator FOSC External Clock (EC) CLKIN FOSC 2011-2013 Microchip Technology Inc.
PIC16(L)F1526/7 6.12 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON register are updated to indicate the cause of the Reset. Table 6-3 and Table 6-4 show the Reset conditions of these registers.
PIC16(L)F1526/7 6.13 Power Control (PCON) Register The Power Control (PCON) register contains flag bits to differentiate between a: • • • • • • • Power-on Reset (POR) Brown-out Reset (BOR) Reset Instruction Reset (RI) MCLR Reset (RMCLR) Watchdog Timer Reset (RWDT) Stack Underflow Reset (STKUNF) Stack Overflow Reset (STKOVF) The PCON register bits are shown in Register 6-2. 6.
PIC16(L)F1526/7 TABLE 6-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BORCON SBOREN BORFS — — — — — BORRDY 67 PCON STKOVF STKUNF — RWDT RMCLR RI POR BOR 71 STATUS — — — TO PD Z DC C 21 WDTCON — — SWDTEN 97 WDTPS<4:0> Legend: — = unimplemented bit, read as ‘0’. Shaded cells are not used by Resets.
PIC16(L)F1526/7 7.0 INTERRUPTS The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode. This chapter contains the following information for Interrupts: • • • • • Operation Interrupt Latency Interrupts During Sleep INT Pin Automatic Context Saving Many peripherals produce interrupts. Refer to the corresponding chapters for details.
PIC16(L)F1526/7 7.1 Operation Interrupts are disabled upon any device Reset. They are enabled by setting the following bits: • GIE bit of the INTCON register • Interrupt Enable bit(s) for the specific interrupt event(s) • PEIE bit of the INTCON register (if the Interrupt Enable bit of the interrupt event is contained in the PIEx register) 7.2 Interrupt Latency Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins.
PIC16(L)F1526/7 FIGURE 7-2: INTERRUPT LATENCY OSC1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKR Interrupt Sampled during Q1 Interrupt GIE PC Execute PC-1 PC 1 Cycle Instruction at PC PC+1 0004h 0005h NOP NOP Inst(0004h) PC+1/FSR ADDR New PC/ PC+1 0004h 0005h Inst(PC) NOP NOP Inst(0004h) FSR ADDR PC+1 PC+2 0004h 0005h INST(PC) NOP NOP NOP Inst(0004h) Inst(0005h) FSR ADDR PC+1 0004h 0005h INST(PC) NOP NOP Inst(00
PIC16(L)F1526/7 FIGURE 7-3: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT (3) (4) INT pin (1) (1) INTF Interrupt Latency (2) (5) GIE INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: PC Inst (PC) Inst (PC – 1) PC + 1 Inst (PC + 1) Inst (PC) PC + 1 — Forced NOP 0004h Inst (0004h) Forced NOP 0005h Inst (0005h) Inst (0004h) INTF flag is sampled here (every Q1).
PIC16(L)F1526/7 7.3 Interrupts During Sleep Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction.
PIC16(L)F1526/7 7.
PIC16(L)F1526/7 REGISTER 7-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMR1GIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit 1 = Enables the Timer1
PIC16(L)F1526/7 REGISTER 7-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 OSFIE TMR5GIE TMR3GIE — BCL1IE TMR10IE TMR8IE CCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSFIE: Oscillator Fail Interrupt Enable bit 1 = Enables the Oscillat
PIC16(L)F1526/7 REGISTER 7-4: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 CCP6IE CCP5IE CCP4IE CCP3IE TMR6IE TMR5IE TMR4IE TMR3IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CCP6IE: CCP6 Interrupt Enable bit 1 = Enables the CCP6 interr
PIC16(L)F1526/7 REGISTER 7-5: PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 CCP10IE CCP9IE RC2IE TX2IE CCP8IE CCP7IE BCL2IE SSP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CCP10IE: CCP10 Interrupt Enable bit 1 = Enables the CCP10 interrup
PIC16(L)F1526/7 REGISTER 7-6: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMR1GIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit 1 = Interrupt is pending 0
PIC16(L)F1526/7 REGISTER 7-7: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 OSFIF TMR5GIF TMR3GIF — BCL1IF TMR10IF TMR8IF CCP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSFIF: Oscillator Fail Interrupt Flag bit 1 = Interrupt is pending
PIC16(L)F1526/7 REGISTER 7-8: PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 CCP6IF CCP5IF CCP4IF CCP3IF TMR6IF TMR5IF TMR4IF TMR3IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CCP6IF: CCP6 Interrupt Flag bit 1 = Interrupt is pending 0 =
PIC16(L)F1526/7 REGISTER 7-9: PIR4: PERIPHERAL INTERRUPT REQUEST REGISTER 4 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 CCP10IF CCP9IF RC2IF TX2IF CCP8IF CCP7IF BCL2IF SSP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CCP10IF: CCP10 Interrupt Flag bit 1 = Interrupt is pending 0 = In
PIC16(L)F1526/7 TABLE 7-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Bit 7 INTCON Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 78 IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 141 IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 141 IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 141 OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PIE1 TMR1GIE A
PIC16(L)F1526/7 NOTES: DS41458C-page 88 2011-2013 Microchip Technology Inc.
PIC16(L)F1526/7 8.0 POWER-DOWN MODE (SLEEP) 8.1 Wake-up from Sleep The Power-down mode is entered by executing a SLEEP instruction. The device can wake-up from Sleep through one of the following events: Upon entering Sleep mode, the following conditions exist: 1. 2. 3. 4. 5. 6. 1. 2. 3. 4. 5. 6. 7. 8. 9. WDT will be cleared but keeps running, if enabled for operation during Sleep. PD bit of the STATUS register is cleared. TO bit of the STATUS register is set. CPU clock is disabled.
PIC16(L)F1526/7 8.1.1 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: • If the interrupt occurs before the execution of a SLEEP instruction - SLEEP instruction will execute as a NOP. - WDT and WDT prescaler will not be cleared - TO bit of the STATUS register will not be set - PD bit of the STATUS register will not be cleared.
PIC16(L)F1526/7 8.2 Low-Power Sleep Mode The PIC16F1526 device contains an internal Low Dropout (LDO) voltage regulator, which allows the device I/O pins to operate at voltages up to 5.5V while the internal device logic operates at a lower voltage. The LDO and its associated reference circuitry must remain active when the device is in Sleep mode. The PIC16F1526 allows the user to optimize the operating current in Sleep, depending on the application requirements.
PIC16(L)F1526/7 8.
PIC16(L)F1526/7 9.0 LOW DROPOUT (LDO) VOLTAGE REGULATOR The PIC16F1526/7 has an internal Low Dropout Regulator (LDO) which provides operation above 3.6V. The LDO regulates a voltage for the internal device logic while permitting the VDD and I/O pins to operate at a higher voltage. There is no user enable/disable control available for the LDO, it is always active. The PIC16LF1526/7 operates at a maximum VDD of 3.6V and does not incorporate an LDO.
PIC16(L)F1526/7 NOTES: DS41458C-page 94 2011-2013 Microchip Technology Inc.
PIC16(L)F1526/7 10.0 WATCHDOG TIMER (WDT) The Watchdog Timer is a system timer that generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The Watchdog Timer is typically used to recover the system from unexpected events.
PIC16(L)F1526/7 10.1 Independent Clock Source 10.3 Time-out Period The WDT derives its time base from the 31 kHz LFINTOSC internal oscillator. Time intervals in this chapter are based on a nominal interval of 1 ms. See Section 25.0 “Electrical Specifications” for the LFINTOSC tolerances. The WDTPS bits of the WDTCON register set the time-out period from 1 ms to 256 seconds (nominal). After a Reset, the default time-out period is 2 seconds. 10.
PIC16(L)F1526/7 10.
PIC16(L)F1526/7 TABLE 10-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER Bit 7 Bit 6 Bit 5 — OSCCON — STATUS — — WDTCON — — Legend: CONFIG1 Legend: Bit 3 IRCF<3:0> Bit 2 Bit 1 — TO PD Bit 0 SCS<1:0> Z DC WDTPS<4:0> Register on Page 62 C 21 SWDTEN 97 x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Watchdog Timer.
PIC16(L)F1526/7 11.0 FLASH PROGRAM MEMORY CONTROL The Flash program memory is readable and writable during normal operation over the full VDD range. Program memory is indirectly addressed using Special Function Registers (SFRs).
PIC16(L)F1526/7 TABLE 11-1: FLASH MEMORY ORGANIZATION BY DEVICE Device PIC16(L)F1526 PIC16(L)F1527 11.2.1 Row Erase (words) Write Latches (words) 32 32 READING THE FLASH PROGRAM MEMORY To read a program memory location, the user must: 1. 2. 3. Write the desired address to the PMADRH:PMADRL register pair. Clear the CFGS bit of the PMCON1 register. Then, set control bit RD of the PMCON1 register.
PIC16(L)F1526/7 FIGURE 11-2: FLASH PROGRAM MEMORY READ CYCLE EXECUTION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC Flash ADDR Flash Data PC + 1 INSTR (PC) INSTR(PC - 1) executed here PC +3 PC+3 PMADRH,PMADRL INSTR (PC + 1) BSF PMCON1,RD executed here PMDATH,PMDATL INSTR(PC + 1) instruction ignored Forced NOP executed here PC + 4 INSTR (PC + 3) INSTR(PC + 2) instruction ignored Forced NOP executed here PC + 5 INSTR (PC + 4) INSTR(PC + 3) executed here INSTR
PIC16(L)F1526/7 11.2.2 FLASH MEMORY UNLOCK SEQUENCE The unlock sequence is a mechanism that protects the Flash program memory from unintended self-write programming or erasing.
PIC16(L)F1526/7 11.2.3 ERASING FLASH PROGRAM MEMORY While executing code, program memory can only be erased by rows. To erase a row: 1. 2. 3. 4. 5. Load the PMADRH:PMADRL register pair with any address within the row to be erased. Clear the CFGS bit of the PMCON1 register. Set the FREE and WREN bits of the PMCON1 register. Write 55h, then AAh, to PMCON2 (Flash programming unlock sequence). Set control bit WR of the PMCON1 register to begin the erase operation. See Example 11-2.
PIC16(L)F1526/7 EXAMPLE 11-2: ERASING ONE ROW OF PROGRAM MEMORY Required Sequence ; This row erase routine assumes the following: ; 1. A valid address within the erase row is loaded in ADDRH:ADDRL ; 2.
PIC16(L)F1526/7 11.2.4 WRITING TO FLASH PROGRAM MEMORY Program memory is programmed using the following steps: 1. 2. 3. 4. Load the address in PMADRH:PMADRL of the row to be programmed. Load each write latch with data. Initiate a programming operation. Repeat steps 1 through 3 until all data is written. The following steps should be completed to load the write latches and program a row of program memory. These steps are divided into two parts.
7 BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES 6 0 7 5 4 PMADRH - r9 r8 r7 r6 r5 0 7 PMADRL r4 r3 r2 r1 r0 c4 c3 c2 c1 c0 5 - 0 7 PMDATH 6 0 PMDATL 8 14 10 Program Memory Write Latches 5 14 Write Latch #0 00h PMADRL<4:0> 14 CFGS = 0 2011-2013 Microchip Technology Inc.
PIC16(L)F1526/7 FIGURE 11-6: FLASH PROGRAM MEMORY WRITE FLOWCHART Start Write Operation Determine number of words to be written into Program or Configuration Memory. The number of words cannot exceed the number of words per row. (word_cnt) Disable Interrupts (GIE = 0) Select Program or Config.
PIC16(L)F1526/7 EXAMPLE 11-3: ; ; ; ; ; ; ; WRITING TO FLASH PROGRAM MEMORY This write routine assumes the following: 1. 64 bytes of data are loaded, starting at the address in DATA_ADDR 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR, stored in little endian format 3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL 4.
PIC16(L)F1526/7 11.3 Modifying Flash Program Memory When modifying existing data in a program memory row, and data within that row must be preserved, it must first be read and saved in a RAM image. Program memory is modified using the following steps: 1. 2. 3. 4. 5. 6. 7. Load the starting address of the row to be modified. Read the existing data from the row into a RAM image. Modify the RAM image to contain the new data to be written into program memory.
PIC16(L)F1526/7 11.4 User ID, Device ID and Configuration Word Access Instead of accessing program memory, the User ID’s, Device ID/Revision ID and Configuration Words can be accessed when CFGS = 1 in the PMCON1 register. This is the region that would be pointed to by PC<15> = 1, but not all addresses are accessible. Different access may exist for reads and writes. Refer to Table 11-2.
PIC16(L)F1526/7 11.5 Write Verify It is considered good programming practice to verify that program memory writes agree with the intended value. Since program memory is stored as a full page then the stored program memory contents are compared with the intended data stored in RAM after the last write is complete. FIGURE 11-8: FLASH PROGRAM MEMORY VERIFY FLOWCHART Start Verify Operation This routine assumes that the last row of data written was from an image saved in RAM.
PIC16(L)F1526/7 11.
PIC16(L)F1526/7 REGISTER 11-5: PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER U-1 R/W-0/0 R/W-0/0 R/W/HC-0/0 R/W/HC-x/q(2) R/W-0/0 R/S/HC-0/0 R/S/HC-0/0 —(1) CFGS LWLO FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 Unimplemented: Read as ‘1’ bit 6
PIC16(L)F1526/7 REGISTER 11-6: W-0/0 PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 Program Memory Control Register 2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Flash Memory Unlock Pattern bits To unlock writes, a 55h must be written first, followed by an AAh, before
PIC16(L)F1526/7 12.0 I/O PORTS FIGURE 12-1: GENERIC I/O PORT OPERATION In general, when a peripheral is enabled on a port pin, that pin cannot be used as a general purpose output. However, the pin can still be read. Each port has three standard registers for its operation.
PIC16(L)F1526/7 12.1 Alternate Pin Function The Alternate Pin Function Control (APFCON) registers are used to steer specific peripheral input and output functions between different pins. The APFCON registers are shown in Register 12-1. For this device family, the following functions can be moved between different pins. • Timer3 • CCP2 These bits have no effect on the values of any TRIS register. PORT and TRIS overrides will be routed to the correct pin. The unselected pin will be unaffected. 12.
PIC16(L)F1526/7 12.3 12.3.1 PORTA Registers DATA REGISTER PORTA is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 12-3). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). Example 12-1 shows how to initialize an I/O port.
PIC16(L)F1526/7 12.
PIC16(L)F1526/7 REGISTER 12-5: ANSELA: PORTA ANALOG SELECT REGISTER U-0 U-0 R/W-1/1 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5 ANSA5: Analog Select between Analog or Digital Function on pins
PIC16(L)F1526/7 12.5 12.5.1 PORTB Registers DATA REGISTER PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB (Register 12-7). Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin).
PIC16(L)F1526/7 12.
PIC16(L)F1526/7 REGISTER 12-9: ANSELB: PORTB ANALOG SELECT REGISTER U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 ANSB<5:0>: Analog Select between Analog or Digital Fu
PIC16(L)F1526/7 12.7 12.7.1 PORTC Registers DATA REGISTER PORTC is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISC (Register 12-12). Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin).
PIC16(L)F1526/7 12.
PIC16(L)F1526/7 TABLE 12-8: Name APFCON LATC SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 — — — — — — LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 Bit 1 Bit 0 T3CKISEL CCP2SEL LATC1 Register on Page 122 LATC0 121 PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 121 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 121 Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.
PIC16(L)F1526/7 12.9 12.9.1 PORTD Registers DATA REGISTER PORTD is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISD (Register 12-15). Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin).
PIC16(L)F1526/7 12.
PIC16(L)F1526/7 REGISTER 12-17: ANSELD: PORTD ANALOG SELECT REGISTER U-0 U-0 — U-0 — — U-0 R/W-1 R/W-1 R/W-1 R/W-1 — ANSD3 ANSD2 ANSD1 ANSD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 ANSD<3:0>: Analog Select between Analog or Digital Function on pins RD<3:0>, r
PIC16(L)F1526/7 12.11 PORTE Registers 12.11.1 DATA REGISTER PORTE is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISE (Register 12-20). Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin).
PIC16(L)F1526/7 12.
PIC16(L)F1526/7 REGISTER 12-22: ANSELE: PORTE ANALOG SELECT REGISTER U-0 U-0 — U-0 — U-0 — — U-0 R/W-1 R/W-1 R/W-1 — ANSE2 ANSE1 ANSE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 ANSE<2:0>: Analog Select between Analog or Digital Function on pins RE<2:0>, respect
PIC16(L)F1526/7 12.13 PORTF Registers 12.13.1 DATA REGISTER PORTF is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISF (Register 12-25). Setting a TRISF bit (= 1) will make the corresponding PORTF pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISF bit (= 0) will make the corresponding PORTF pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin).
PIC16(L)F1526/7 12.
PIC16(L)F1526/7 REGISTER 12-27: ANSELF: PORTF ANALOG SELECT REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 ANSF7 ANSF6 ANSF5 ANSF4 ANSF3 ANSF2 ANSF1 ANSF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: ANSF<7:0>: Analog Select between Analog or Digital Function on pins RF<7:0>, respe
PIC16(L)F1526/7 12.15 PORTG Registers 12.15.1 DATA REGISTER PORTG is a 6-bit wide, bidirectional port. The corresponding data direction register is TRISG (Register 12-29). Setting a TRISG bit (= 1) will make the corresponding PORTG pin an input (i.e., disable the output driver). Clearing a TRISG bit (= 0) will make the corresponding PORTG pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin).
PIC16(L)F1526/7 12.
PIC16(L)F1526/7 REGISTER 12-30: LATG: PORTG DATA LATCH REGISTER U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — — LATG4 LATG3 LATG2 LATG1 LATG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 LATG<4:0>: PORTG Output Latch Value bits(1) Note 1: Writes to POR
PIC16(L)F1526/7 REGISTER 12-32: WPUG: WEAK PULL-UP PORTG REGISTER U-0 U-0 R/W-1/1 U-0 U-0 U-0 U-0 U-0 — — WPUG5 — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5 WPUG5: Weak Pull-up Register bit 1 = Pull-up enabled 0 = Pull-up disabled bit 4-0 Note 1: 2: Unim
PIC16(L)F1526/7 13.0 INTERRUPT-ON-CHANGE The PORTB pins can be configured to operate as Interrupt-On-Change (IOC) pins. An interrupt can be generated by detecting a signal that has either a rising edge or a falling edge. Any individual PORTB pin, or combination of PORTB pins, can be configured to generate an interrupt.
PIC16(L)F1526/7 FIGURE 13-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM IOCBNx D Q4Q1 Q CK edge detect R RBx IOCBPx D data bus = 0 or 1 Q write IOCBFx CK D S Q to data bus IOCBFx CK IOCIE R Q2 from all other IOCBFx individual pin detectors Q1 Q3 Q4 Q4Q1 DS41458C-page 140 Q1 Q1 Q2 Q2 Q2 Q3 Q4 Q4Q1 IOC interrupt to CPU core Q3 Q4 Q4 Q4Q1 Q4Q1 2011-2013 Microchip Technology Inc.
PIC16(L)F1526/7 13.
PIC16(L)F1526/7 TABLE 13-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 122 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 78 Name IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 141 IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 141 IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF
PIC16(L)F1526/7 14.0 FIXED VOLTAGE REFERENCE (FVR) 14.1 Independent Gain Amplifiers The output of the FVR supplied to the ADC module is routed through two independent programmable gain amplifiers. Each amplifier can be configured to amplify the reference voltage by 1x, 2x or 4x, to produce the three possible voltage levels. The Fixed Voltage Reference, or FVR, is a stable voltage reference, independent of VDD, with 1.024V, 2.048V or 4.096V selectable output levels.
PIC16(L)F1526/7 14.
PIC16(L)F1526/7 15.0 TEMPERATURE INDICATOR MODULE FIGURE 15-1: This family of devices is equipped with a temperature circuit designed to measure the operating temperature of the silicon die. The circuit’s range of operating temperature falls between -40°C and +85°C. The output is a voltage that is proportional to the device temperature. The output of the temperature indicator is internally connected to the device ADC.
PIC16(L)F1526/7 15.4 ADC Acquisition Time To ensure accurate temperature measurements, the user must wait at least 200 s after the ADC input multiplexer is connected to the temperature indicator output before the conversion is performed. In addition, the user must wait 200 s between sequential conversions of the temperature indicator output.
PIC16(L)F1526/7 16.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter.
PIC16(L)F1526/7 16.1 ADC Configuration When configuring and using the ADC the following functions must be considered: • • • • • • Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Result formatting 16.1.1 PORT CONFIGURATION The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits. Refer to Section 12.
PIC16(L)F1526/7 TABLE 16-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES ADC Clock Period (TAD) Device Frequency (FOSC) ADC Clock Source ADCS<2:0> 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz FOSC/2 000 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s FOSC/4 100 (2) 200 ns (2) 250 ns (2) FOSC/8 001 400 ns(2) 0.5 s(2) FOSC/16 101 800 ns 1.0 s FOSC/32 1.6 s 010 2.0 s FOSC/64 110 3.2 s 4.0 s FRC x11 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) Legend: Note 1: 2: 3: 4: 1.
PIC16(L)F1526/7 16.1.5 INTERRUPTS 16.1.6 The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. RESULT FORMATTING The 10-bit ADC conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON1 register controls the output format.
PIC16(L)F1526/7 16.2 16.2.1 ADC Operation STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a ‘1’. Setting the GO/DONE bit of the ADCON0 register to a ‘1’ will start the Analog-to-Digital conversion. Note: 16.2.2 The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 16.2.6 “ADC Conversion Procedure”.
PIC16(L)F1526/7 16.2.6 ADC CONVERSION PROCEDURE This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. 2. 3. 4. 5. 6. 7. 8.
PIC16(L)F1526/7 16.
PIC16(L)F1526/7 REGISTER 16-2: R/W-0/0 ADCON1: ADC CONTROL REGISTER 1 R/W-0/0 ADFM R/W-0/0 R/W-0/0 ADCS<2:0> U-0 U-0 — — R/W-0/0 R/W-0/0 ADPREF<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: ADC Result Format Select bit 1 = Right justified.
PIC16(L)F1526/7 REGISTER 16-3: R/W-x/u ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ADRES<9:2>: ADC Result Register bits Upper 8 bits of 10-bit conversion result REGISTER 16-4: R/W-x/u AD
PIC16(L)F1526/7 REGISTER 16-5: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — — — — — R/W-x/u R/W-x/u ADRES<9:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Reserved: Do not use.
PIC16(L)F1526/7 16.4 ADC Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 16-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), refer to Figure 16-4.
PIC16(L)F1526/7 FIGURE 16-4: ANALOG INPUT MODEL VDD Analog Input pin Rs VT 0.6V CPIN 5 pF VA RIC 1k Sampling Switch SS Rss I LEAKAGE(1) VT 0.
PIC16(L)F1526/7 TABLE 16-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH ADC Bit 7 ADCON0 — ADCON1 ADFM Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 — — CHS<4:0> ADCS<2:0> Bit 1 Bit 0 GO/DONE ADON ADPREF<1:0> Register on Page 153 154 ADRESH ADC Result Register High 155, 156 ADRESL ADC Result Register Low 155, 156 ANSELA — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 119 ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 122 ANSELD — — — — ANSD3 ANSD2 ANSD1 ANSD0 128 ANSELE — — —
PIC16(L)F1526/7 NOTES: DS41458C-page 160 2011-2013 Microchip Technology Inc.
PIC16(L)F1526/7 17.0 TIMER0 MODULE 17.1.2 In 8-Bit Counter mode, the Timer0 module will increment on either the rising or falling edge of the T0CKI pin.
PIC16(L)F1526/7 17.1.3 SOFTWARE PROGRAMMABLE PRESCALER A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION_REG register. Note: The Watchdog Timer (WDT) uses its own independent prescaler. There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION_REG register.
PIC16(L)F1526/7 17.
PIC16(L)F1526/7 NOTES: DS41458C-page 164 2011-2013 Microchip Technology Inc.
PIC16(L)F1526/7 18.0 TIMER1/3/5 MODULE WITH GATE CONTROL • • • • The Timer1/3/5 module is a 16-bit timer/counter with the following features: Figure 18-1 is a block diagram of the Timer1/3/5 module.
PIC16(L)F1526/7 FIGURE 18-2: TIMER1/3/5 CLOCK SOURCE DIAGRAM To Clock Switching (SOSC users) (1) TMR1CS<1:0> 0 10 SOSCO/T1CKI OUT 1 Secondary Oscillator SOSCI Timer 1 EN LFINTOSC 11 FOSC/4 00 FOSC 01 Timer1 T1CON[SOSCEN] T3CON[SOSCEN] T5CON[SOSCEN] TMR3CS<1:0> 1 10 (1) 0 T3CKI Timer 3 LFINTOSC 11 FOSC/4 00 FOSC 01 Timer3 TMR5CS<1:0> 1 10 (1) T5CKI 0 Timer 5 LFINTOSC 11 FOSC/4 00 FOSC 01 Timer5 Note 1: ST Buffer is high-speed type when using TxCKI.
PIC16(L)F1526/7 18.1 Timer1/3/5 Operation 18.2 The Timer1/3/5 module is a 16-bit incrementing counter which is accessed through the TMRxH:TMRxL register pair. Writes to TMRxH or TMRxL directly update the counter. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and increments on every selected edge of the external source.
PIC16(L)F1526/7 18.3 Timer1/3/5 Prescaler Timer1/3/5 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The TxCKPS bits of the TxCON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMRxH or TMRxL. 18.4 Timer1/3/5 Oscillator 18.5.
PIC16(L)F1526/7 18.6.2 TIMER1/3/5 GATE SOURCE SELECTION The Timer1/3/5 gate source can be selected from one of four different sources. Source selection is controlled by the TxGSS bits of the TxGCON register. The polarity for each available source is also selectable. Polarity selection is controlled by the TxGPOL bit of the TxGCON register.
PIC16(L)F1526/7 18.6.6 TIMER1/3/5 GATE EVENT INTERRUPT When Timer1/3/5 Gate Event Interrupt is enabled, it is possible to generate an interrupt upon the completion of a gate event. When the falling edge of TxGVAL occurs, the TMRxGIF flag bit in the PIR1 register will be set. If the TMRxGIE bit in the PIE1 register is set, then an interrupt will be recognized. The TMRxGIF flag bit operates even when the Timer1/3/5 gate is not enabled (TMRxGE bit is cleared). 18.
PIC16(L)F1526/7 FIGURE 18-3: TIMER1/3/5 INCREMENTING EDGE TXCKI = 1 when TMR1 Enabled TXCKI = 0 when TMR1 Enabled Note 1: 2: Arrows indicate counter increments. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. FIGURE 18-4: TIMER1/3/5 GATE ENABLE MODE TMRxGE TxGPOL txg_in TxCKI TxGVAL Timer1/3/5 N 2011-2013 Microchip Technology Inc.
PIC16(L)F1526/7 FIGURE 18-5: TIMER1/3/5 GATE TOGGLE MODE TMRxGE TxGPOL TxGTM txg_in TxCKI TxGVAL Timer1/3/5 FIGURE 18-6: N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 TIMER1/3/5 GATE SINGLE-PULSE MODE TMRxGE TxGPOL TxGSPM TxGGO/ Cleared by hardware on falling edge of TxGVAL Set by software DONE Counting enabled on rising edge of TxG txg_in TxCKI TxGVAL Timer1/3/5 TMRxGIF DS41458C-page 172 N Cleared by software N+1 N+2 Set by hardware on falling edge of TxGVAL Cleared by software 2011-20
PIC16(L)F1526/7 FIGURE 18-7: TIMER1/3/5 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMRxGE TxGPOL TxGSPM TxGTM TxGGO/ Cleared by hardware on falling edge of TxGVAL Set by software DONE Counting enabled on rising edge of TxG txg_in TxCKI TxGVAL Timer1/3/5 TMRxGIF N Cleared by software 2011-2013 Microchip Technology Inc.
PIC16(L)F1526/7 18.
PIC16(L)F1526/7 18.
PIC16(L)F1526/7 TABLE 18-5: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1/3/5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 119 APFCON — — — — — — CCP1CON — — DC1B<1:0> CCP1M<3:0> 195 CCP2CON — — DC2B<1:0> CCP2M<3:0> 195 CCP3CON — — DC3B<1:0> CCP3M<3:0> 195 CCP4CON — — DC4B<1:0> CCP4M<3:0> 195 CCP5CON — — DC5B<1:0> CCP5M<3:0> 195 CCP6CON — — DC6B<1:0> CCP6M<3:0> 195 CCP7CON — — DC7B<
PIC16(L)F1526/7 19.0 TIMER2/4/6/8/10 MODULES There are up to five identical Timer2-type modules available. To maintain pre-existing naming conventions, the Timers are called Timer2, Timer4, Timer6, Timer8 and Timer10 (also Timer2/4/6/8/10). Note: The ‘x’ variable used in this section is used to designate Timer2, Timer4, Timer6, Timer8 or Timer10. For example, TxCON references T2CON, T4CON, T6CON, T8CON or T10CON. PRx references PR2, PR4, PR6, PR8 or PR10.
PIC16(L)F1526/7 19.1 Timer2/4/6/8/10 Operation The clock input to the Timer2/4/6/8/10 modules is the system instruction clock (FOSC/4). TMR2/4/6/8/10 increments from 00h on each clock edge. A 4-bit counter/prescaler on the clock input allows direct input, divide-by-4 and divide-by-16 prescale options. These options are selected by the prescaler control bits, TxCKPS<1:0> of the TxCON register. The value of TMR2/4/6/8/10 is compared to that of the Period register, PR2/4/6/8/10, on each clock cycle.
PIC16(L)F1526/7 19.
PIC16(L)F1526/7 TABLE 19-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2/4/6/8/10 Bit 6 CCP1CON — — DC1B<1:0> CCP1M<3:0> 195 CCP2CON — — DC2B<1:0> CCP2M<3:0> 195 CCP3CON — — DC3B<1:0> CCP3M<3:0> 195 CCP4CON — — DC4B<1:0> CCP4M<3:0> 195 CCP5CON — — DC5B<1:0> CCP5M<3:0> 195 CCP6CON — — DC6B<1:0> CCP6M<3:0> 195 CCP7CON — — DC7B<1:0> CCP7M<3:0> 195 CCP8CON — — DC8B<1:0> CCP8M<3:0> 195 CCP9CON — — DC9B<1:0> CCP9M<3:0> 195 CCP10CON — — DC10B<1:0> CCP
PIC16(L)F1526/7 20.0 CAPTURE/COMPARE/PWM MODULES The Capture/Compare/PWM module is a peripheral which allows the user to time and control different events, and to generate Pulse-Width Modulation (PWM) signals. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate Pulse-Width Modulated signals of varying frequency and duty cycle.
PIC16(L)F1526/7 20.1 Capture Mode 20.1.2 The Capture mode function described in this section is available and identical for CCP modules. Capture mode makes use of the 16-bit Timer1/3/5 resource. When an event occurs on the CCPx pin, the 16-bit CCPRxH:CCPRxL register pair captures and stores the 16-bit value of the TMRxH:TMRxL register pair, respectively.
PIC16(L)F1526/7 20.1.4 CCP PRESCALER There are four prescaler settings specified by the CCPxM<3:0> bits of the CCPxCON register. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. Any Reset will clear the prescaler counter. Switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt.
PIC16(L)F1526/7 TABLE 20-2: Name SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE Register on Page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 APFCON — — — — — — T3CKISEL CCP2SEL CCP1CON — — DC1B<1:0> CCP1M<3:0> 195 CCP2CON — — DC2B<1:0> CCP2M<3:0> 195 CCP3CON — — DC3B<1:0> CCP3M<3:0> 195 CCP4CON — — DC4B<1:0> CCP4M<3:0> 195 CCP5CON — — DC5B<1:0> CCP5M<3:0> 195 CCP6CON — — DC6B<1:0> CCP6M<3:0> 195 CCP7CON — — DC7B<1:0> CCP7M<3:0> 195 CCP8CON — —
PIC16(L)F1526/7 TABLE 20-2: Name T5GCON SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 TMR5GE T5GPOL T5GTM T5GSPM T5GGO/DONE T5GVAL Bit 1 Bit 0 T5GSS<1:0> Register on Page 175 TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 170* TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register 170* TMR6L Holding Register for the Least Significant Byte of the 16-bit TMR6 Register 170* T
PIC16(L)F1526/7 20.2 Compare Mode 20.2.1 CCP PIN CONFIGURATION The Compare mode function described in this section is available and identical for CCP modules. The user must configure the CCPx pin as an output by clearing the associated TRIS bit. Compare mode makes use of the 16-bit Timer1/3/5 resource. The 16-bit value of the CCPRxH:CCPRxL register pair is constantly compared against the 16-bit value of the TMRxH:TMRxL register pair.
PIC16(L)F1526/7 20.2.3 SOFTWARE INTERRUPT MODE 20.2.5 COMPARE DURING SLEEP When Generate Software Interrupt mode is chosen (CCPxM<3:0> = 1010), the CCPx module does not assert control of the CCPx pin (see the CCPxCON register). The Compare mode is dependent upon the system clock (FOSC) for proper operation. Since FOSC is shut down during Sleep mode, the Compare mode will not function properly during Sleep. 20.2.4 20.2.
PIC16(L)F1526/7 TABLE 20-5: Name SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE Register on Page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 APFCON — — — — — — T3CKISEL CCP2SEL CCP1CON — — DC1B<1:0> CCP1M<3:0> 195 CCP2CON — — DC2B<1:0> CCP2M<3:0> 195 CCP3CON — — DC3B<1:0> CCP3M<3:0> 195 CCP4CON — — DC4B<1:0> CCP4M<3:0> 195 CCP5CON — — DC5B<1:0> CCP5M<3:0> 195 CCP6CON — — DC6B<1:0> CCP6M<3:0> 195 CCP7CON — — DC7B<1:0> CCP7M<3:0> 195 CCP8CON — —
PIC16(L)F1526/7 TABLE 20-5: Name T5GCON SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 TMR5GE T5GPOL T5GTM T5GSPM T5GGO/DONE T5GVAL Bit 1 Bit 0 T5GSS<1:0> Register on Page 175 TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 170* TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register 170* TMR6L Holding Register for the Least Significant Byte of the 16-bit TMR6 Register 170* T
PIC16(L)F1526/7 20.3 PWM Overview Pulse-Width Modulation (PWM) is a scheme that provides power to a load by switching quickly between fully on and fully off states. The PWM signal resembles a square wave where the high portion of the signal is considered the on state and the low portion of the signal is considered the off state. The high portion, also known as the pulse width, can vary in time and is defined in steps.
PIC16(L)F1526/7 20.3.2 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for standard PWM operation: 1. 2. 3. 4. 5. 6. Disable the CCPx pin output driver by setting the associated TRIS bit. Load the PRx register with the PWM period value. Configure the CCP module for the PWM mode by loading the CCPxCON register with the appropriate values. Load the CCPRxL register and the DCxBx bits of the CCPxCON register, with the PWM duty cycle value.
PIC16(L)F1526/7 20.3.5 PWM DUTY CYCLE The PWM duty cycle is specified by writing a 10-bit value to multiple registers: CCPRxL register and DCxB<1:0> bits of the CCPxCON register. The CCPRxL contains the eight MSbs and the DCxB<1:0> bits of the CCPxCON register contain the two LSbs. CCPRxL and DCxB<1:0> bits of the CCPxCON register can be written to at any time. The duty cycle value is not latched into CCPRxH until after the period completes (i.e., a match between PRx and TMRx registers occurs).
PIC16(L)F1526/7 20.3.7 OPERATION IN SLEEP MODE 20.3.9 In Sleep mode, the TMRx register will not increment and the state of the module will not change. If the CCPx pin is driving a value, it will continue to drive that value. When the device wakes up, TMRx will continue from its previous state. 20.3.8 CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See Section 5.
PIC16(L)F1526/7 TABLE 20-10: SUMMARY OF REGISTERS ASSOCIATED WITH STANDARD PWM (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 T8CON — T8OUTPS<3:0> TMR8ON T8CKPS<:0>1 T10CON — T10OUTPS<3:0> TMR10ON T10CKPS<:0>1 Register on Page 174 174 TMR2 Timer2 Module Register 177* TMR4 Timer4 Module Register 177* TMR6 Timer6 Module Register 177* TMR8 Timer8 Module Register 177* TMR10 Timer10 Module Register TRISA TRISA7 TRISA6 177* TRISA5 TRISA4 TRISA3 TRISA2 TR
PIC16(L)F1526/7 20.
PIC16(L)F1526/7 REGISTER 20-2: R/W-0/0 CCPTMRS0: CCP TIMER SELECTION CONTROL REGISTER 0 R/W-0/0 C4TSEL<1:0> R/W-0/0 R/W-0/0 R/W-0/0 C3TSEL<1:0> R/W-0/0 R/W-0/0 C2TSEL<1:0> R/W-0/0 C1TSEL<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 C4TSEL<1:0>: CCP4 Timer Selection bits When in Capture/Compare mod
PIC16(L)F1526/7 REGISTER 20-3: R/W-0/0 CCPTMRS1: CCP TIMER SELECTION CONTROL REGISTER 1 R/W-0/0 R/W-0/0 C8TSEL<1:0> R/W-0/0 R/W-0/0 C7TSEL<1:0> R/W-0/0 R/W-0/0 C6TSEL<1:0> bit 7 R/W-0/0 C5TSEL<1:0> bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 C8TSEL<1:0>: CCP8 Timer Selection bits When in Capture/Compare mode
PIC16(L)F1526/7 REGISTER 20-4: CCPTMRS2: CCP TIMER SELECTION CONTROL REGISTER 2 U-0 U-0 U-0 U-0 — — — — R/W-0/0 R/W-0/0 R/W-0/0 C10TSEL<1:0> R/W-0/0 C9TSEL<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-2 C10TSEL<1:0>: CCP10 Timer Selection bits When in Capture/
PIC16(L)F1526/7 21.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP1 AND MSSP2) MODULE 21.1 Master SSPx (MSSPx) Module Overview The Master Synchronous Serial Port (MSSPx) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc.
PIC16(L)F1526/7 The I2C interface supports the following modes and features: Master mode Slave mode Byte NACKing (Slave mode) Limited Multi-master support 7-bit and 10-bit addressing Start and Stop interrupts Interrupt masking Clock stretching Bus collision detection General call address matching Address masking Address Hold and Data Hold modes Selectable SDAx hold times Note 1: In devices with more than one MSSP module, it is very important to pay close attention to SSPxCONx register names.
PIC16(L)F1526/7 FIGURE 21-3: MSSPX BLOCK DIAGRAM (I2C™ SLAVE MODE) Internal Data Bus Read Write SSPxBUF Reg SCLx Shift Clock SSPxSR Reg SDAx MSb LSb SSPxMSK Reg Match Detect Addr Match SSPxADD Reg Start and Stop bit Detect 2011-2013 Microchip Technology Inc.
PIC16(L)F1526/7 21.2 SPI Mode Overview The Serial Peripheral Interface (SPI) bus is a synchronous serial data communication bus that operates in Full-Duplex mode. Devices communicate in a master/slave environment where the master device initiates the communication. A slave device is controlled through a chip select known as Slave Select.
PIC16(L)F1526/7 FIGURE 21-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION SPI Master SCKx SCKx SDOx SDIx SDIx SDOx General I/O General I/O SSx General I/O SCKx SDIx SDOx SPI Slave #1 SPI Slave #2 SSx SCKx SDIx SDOx SPI Slave #3 SSx 21.2.1 SPI MODE REGISTERS The MSSPx module has five registers for SPI mode operation.
PIC16(L)F1526/7 21.2.2 SPI MODE OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>).
PIC16(L)F1526/7 21.2.3 SPI MASTER MODE The master can initiate the data transfer at any time because it controls the SCKx line. The master determines when the slave (Processor 2, Figure 21-5) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPxBUF register is written to. If the SPI is only going to receive, the SDOx output could be disabled (programmed as an input).
PIC16(L)F1526/7 21.2.4 SPI SLAVE MODE In Slave mode, the data is transmitted and received as external clock pulses appear on SCKx. When the last bit is latched, the SSPxIF interrupt flag bit is set. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCKx pin. The Idle state is determined by the CKP bit of the SSPxCON1 register.
PIC16(L)F1526/7 FIGURE 21-7: SPI DAISY-CHAIN CONNECTION SPI Master SCK SCK SDOx SDIx SDIx SDOx General I/O SPI Slave #1 SSx SCK SDIx SDOx SPI Slave #2 SSx SCK SDIx SDOx SPI Slave #3 SSx FIGURE 21-8: SLAVE SELECT SYNCHRONOUS WAVEFORM SSx SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF Shift register SSPxSR and bit count are reset SSPxBUF to SSPxSR SDOx bit 7 bit 6 bit 7 SDIx bit 6 bit 0 bit 0 bit 7 bit 7 Input Sample SSPxIF Interrupt Flag SSPxSR to SSPxBUF 2011-2
PIC16(L)F1526/7 FIGURE 21-9: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SSx Optional SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF Valid SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDIx bit 0 bit 7 Input Sample SSPxIF Interrupt Flag SSPxSR to SSPxBUF Write Collision detection active FIGURE 21-10: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SSx Not Optional SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) Write to SSPxBUF Valid SDOx bit 7 bit 6 bit 5 bit 4 bit 3 b
PIC16(L)F1526/7 21.2.6 SPI OPERATION IN SLEEP MODE In SPI Master mode, module clocks may be operating at a different speed than when in Full-Power mode; in the case of the Sleep mode, all clocks are halted. Special care must be taken by the user when the MSSPx clock is much faster than the system clock. In Slave mode, when MSSPx interrupts are enabled, after the master completes sending data, an MSSPx interrupt will wake the controller from Sleep.
PIC16(L)F1526/7 21.3 I2C MODE OVERVIEW The Inter-Integrated Circuit Bus (I2C) is a multi-master serial data communication bus. Devices communicate in a master/slave environment where the master devices initiate the communication. A slave device is controlled through addressing. VDD SCLx The I2C bus specifies two signal connections: • Serial Clock (SCLx) • Serial Data (SDAx) Figure 21-2 and Figure 21-3 shows the block diagram of the MSSPx module when operating in I2C mode.
PIC16(L)F1526/7 When one device is transmitting a logical one, or letting the line float, and a second device is transmitting a logical zero, or holding the line low, the first device can detect that the line is not a logical one. This detection, when used on the SCLx line, is called clock stretching. Clock stretching gives slave devices a mechanism to control the flow of data. When this detection is used on the SDAx line, it is called arbitration.
PIC16(L)F1526/7 21.4 I2C MODE OPERATION All MSSPx I2C communication is byte oriented and shifted out MSb first. Six SFR registers and 2 interrupt flags interface the module with the PIC® microcontroller and user software. Two pins, SDAx and SCLx, are exercised by the module to communicate with other external I2C devices. 21.4.1 BYTE FORMAT All communication in I2C is done in 9-bit segments. A byte is sent from a master to a slave or vice-versa, followed by an Acknowledge bit sent back.
PIC16(L)F1526/7 21.4.5 21.4.7 START CONDITION The I2C specification defines a Start condition as a transition of SDAx from a high to a low state while SCLx line is high. A Start condition is always generated by the master and signifies the transition of the bus from an Idle to an Active state. Figure 21-12 shows wave forms for Start and Stop conditions. A bus collision can occur on a Start condition if the module samples the SDAx line low before asserting it low.
PIC16(L)F1526/7 FIGURE 21-13: I2C RESTART CONDITION Sr Change of Change of Data Allowed Restart Data Allowed Condition DS41458C-page 214 2011-2013 Microchip Technology Inc.
PIC16(L)F1526/7 21.4.9 ACKNOWLEDGE SEQUENCE The 9th SCLx pulse for any transferred byte in I2C is dedicated as an Acknowledge. It allows receiving devices to respond back to the transmitter by pulling the SDAx line low. The transmitter must release control of the line during this time to shift in the response. The Acknowledge (ACK) is an active-low signal, pulling the SDAx line low indicated to the transmitter that the device has received the transmitted data and is ready to receive more.
PIC16(L)F1526/7 21.5.2 SLAVE RECEPTION When the R/W bit of a matching received address byte is clear, the R/W bit of the SSPxSTAT register is cleared. The received address is loaded into the SSPxBUF register and acknowledged. When the overflow condition exists for a received address, then not Acknowledge is given. An overflow condition is defined as either bit BF of the SSPxSTAT register is set, or bit SSPOV of the SSPxCON1 register is set. The BOEN bit of the SSPxCON3 register modifies this operation.
2011-2013 Microchip Technology Inc. SSPOV BF SSPxIF S 1 A7 2 A6 3 A5 4 A4 5 A3 Receiving Address 6 A2 7 A1 8 9 ACK 1 D7 2 D6 4 5 D3 6 D2 7 D1 SSPxBUF is read Cleared by software 3 D4 Receiving Data D5 8 9 2 D6 First byte of data is available in SSPxBUF 1 D0 ACK D7 4 5 D3 6 D2 7 D1 SSPOV set because SSPxBUF is still full. ACK is not sent.
DS41458C-page 218 CKP SSPOV BF SSPxIF 1 SCLx S A7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 9 R/W=0 ACK SEN 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 CKP is written to ‘1’ in software, releasing SCLx SSPxBUF is read Cleared by software Clock is held low until CKP is set to ‘1’ 1 D7 Receive Data 9 ACK SEN 3 D5 4 D4 5 D3 First byte of data is available in SSPxBUF 6 D2 7 D1 SSPOV set because SSPxBUF is still full. ACK is not sent.
2011-2013 Microchip Technology Inc.
DS41458C-page 220 P S ACKTIM CKP ACKDT BF SSPxIF S Receiving Address 4 5 6 7 8 When AHEN = 1; on the 8th falling edge of SCLx of an address byte, CKP is cleared Slave software clears ACKDT to ACK the received byte Received address is loaded into SSPxBUF 2 3 ACKTIM is set by hardware on 8th falling edge of SCLx 1 A7 A6 A5 A4 A3 A2 A1 9 ACK Receive Data 2 3 4 5 6 7 8 ACKTIM is cleared by hardware on 9th rising edge of SCLx When DHEN = 1; on the 8th falling edge of SCLx of a receiv
PIC16(L)F1526/7 21.5.3 SLAVE TRANSMISSION 21.5.3.2 7-bit Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPxSTAT register is set. The received address is loaded into the SSPxBUF register, and an ACK pulse is sent by the slave on the ninth bit. A master device can transmit a read request to a slave, and then clock data out of the slave.
DS41458C-page 222 P S D/A R/W ACKSTAT CKP BF SSPxIF S 1 2 5 6 7 8 Received address is read from SSPxBUF 4 Indicates an address has been received R/W is copied from the matching address byte When R/W is set SCLx is always held low after 9th SCLx falling edge 3 9 Automatic 2 3 4 5 Set by software Data to transmit is loaded into SSPxBUF Cleared by software 1 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK Transmitting Data 2 3 4 5 7 8 CKP is not held for not ACK 6 Masters not
PIC16(L)F1526/7 21.5.3.3 7-bit Transmission with Address Hold Enabled Setting the AHEN bit of the SSPxCON3 register enables additional clock stretching and interrupt generation after the 8th falling edge of a received matching address. Once a matching address has been clocked in, CKP is cleared and the SSPxIF interrupt is set. Figure 21-19 displays a standard waveform of a 7-bit Address Slave Transmission with AHEN enabled. 1. 2. Bus starts Idle.
DS41458C-page 224 D/A R/W ACKTIM CKP ACKSTAT ACKDT BF SSPxIF S Receiving Address 2 4 5 6 7 8 Slave clears ACKDT to ACK address ACKTIM is set on 8th falling edge of SCLx 9 ACK When R/W = 1; CKP is always cleared after ACK R/W = 1 Received address is read from SSPxBUF 3 When AHEN = 1; CKP is cleared by hardware after receiving matching address.
PIC16(L)F1526/7 21.5.4 SLAVE MODE 10-BIT ADDRESS RECEPTION This section describes a standard sequence of events for the MSSPx module configured as an I2C slave in 10-bit Addressing mode. Figure 21-20 is used as a visual reference for this description. This is a step by step process of what must be done by slave software to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. Bus starts Idle. Master sends Start condition; S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled.
DS41458C-page 226 CKP UA BF SSPxIF S 1 1 2 1 5 6 7 0 A9 A8 8 Set by hardware on 9th falling edge 4 1 When UA = 1; SCLx is held low 9 ACK If address matches SSPxADD it is loaded into SSPxBUF 3 1 Receive First Address Byte 1 3 4 5 6 7 8 Software updates SSPxADD and releases SCLx 2 9 A7 A6 A5 A4 A3 A2 A1 A0 ACK Receive Second Address Byte 1 3 4 5 6 7 8 9 1 3 4 5 6 7 Data is read from SSPxBUF SCLx is held low while CKP = 0 2 8 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK
2011-2013 Microchip Technology Inc.
DS41458C-page 228 D/A R/W ACKSTAT CKP UA BF SSPxIF 4 5 6 7 Set by hardware 3 Indicates an address has been received UA indicates SSPxADD must be updated SSPxBUF loaded with received address 2 8 9 1 SCLx S Receiving Address R/W = 0 1 1 1 1 0 A9 A8 ACK 1 3 4 5 6 7 8 After SSPxADD is updated, UA is cleared and SCLx is released Cleared by software 2 9 A7 A6 A5 A4 A3 A2 A1 A0 ACK Receiving Second Address Byte 1 4 5 6 7 8 Set by hardware 2 3 R/W is copied from the matching
PIC16(L)F1526/7 21.5.6 21.5.6.2 CLOCK STRETCHING Clock stretching occurs when a device on the bus holds the SCLx line low effectively pausing communication. The slave may stretch the clock to allow more time to handle data or prepare a response for the master device. A master device is not concerned with stretching as anytime it is active on the bus and not transferring data it is stretching.
PIC16(L)F1526/7 21.5.8 GENERAL CALL ADDRESS SUPPORT In 10-bit Address mode, the UA bit will not be set on the reception of the general call address. The slave will prepare to receive the second byte as data, just as it would in 7-bit mode. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master device. The exception is the general call address which can address all devices.
PIC16(L)F1526/7 21.6 I2C MASTER MODE 21.6.1 I2C MASTER MODE OPERATION Master mode is enabled by setting and clearing the appropriate SSPM bits in the SSPxCON1 register and by setting the SSPEN bit. In Master mode, the SDA and SCK pins must be configured as inputs. The MSSP peripheral hardware will override the output driver TRIS controls when necessary to drive the pins low. The master device generates all of the serial clock pulses and the Start and Stop conditions.
PIC16(L)F1526/7 21.6.2 CLOCK ARBITRATION Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, releases the SCLx pin (SCLx allowed to float high). When the SCLx pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCLx pin is actually sampled high. When the SCLx pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and begins counting.
PIC16(L)F1526/7 21.6.4 I2C MASTER MODE START by hardware; the Baud Rate Generator is suspended, leaving the SDAx line held low and the Start condition is complete. CONDITION TIMING To initiate a Start condition (Figure 21-26), the user sets the Start Enable bit, SEN bit of the SSPxCON2 register. If the SDAx and SCLx pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and starts its count.
PIC16(L)F1526/7 21.6.5 I2C MASTER MODE REPEATED SSPxCON2 register will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDAx pin held low. As soon as a Start condition is detected on the SDAx and SCLx pins, the S bit of the SSPxSTAT register will be set. The SSPxIF bit will not be set until the Baud Rate Generator has timed out.
PIC16(L)F1526/7 21.6.6 I2C MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPxBUF register. This action will set the Buffer Full flag bit, BF and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDAx pin after the falling edge of SCLx is asserted.
DS41458C-page 236 S R/W PEN SEN BF (SSPxSTAT<0>) SSPxIF SCLx SDAx A6 A5 A4 A3 A2 A1 3 4 5 Cleared by software 2 6 7 8 9 After Start condition, SEN cleared by hardware SSPxBUF written 1 D7 1 SCLx held low while CPU responds to SSPxIF ACK = 0 R/W = 0 SSPxBUF written with 7-bit address and R/W start transmit A7 Transmit Address to Slave 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 SSPxBUF is written by software Cleared by software service routine from SSPx interrupt 2 D6 Transm
PIC16(L)F1526/7 21.6.7 I2C MASTER MODE RECEPTION Master mode reception (Figure 21-29) is enabled by programming the Receive Enable bit, RCEN bit of the SSPxCON2 register. Note: The MSSPx module must be in an Idle state before the RCEN bit is set or the RCEN bit will be disregarded. The Baud Rate Generator begins counting and on each rollover, the state of the SCLx pin changes (high-to-low/low-to-high) and data is shifted into the SSPxSR.
DS41458C-page 238 RCEN ACKEN SSPOV BF (SSPxSTAT<0>) SDAx = 0, SCLx = 1 while CPU responds to SSPxIF SSPxIF S 1 A7 2 4 5 6 Cleared by software 3 A6 A5 A4 A3 A2 Transmit Address to Slave 7 8 9 ACK Receiving Data from Slave 2 3 5 6 7 8 D0 9 ACK Receiving Data from Slave 2 3 4 RCEN cleared automatically 5 6 7 Cleared by software Set SSPxIF interrupt at end of Acknowledge sequence Data shifted in on falling edge of CLK 1 ACK from Master SDAx = ACKDT = 0 Cleared in softwa
PIC16(L)F1526/7 21.6.8 ACKNOWLEDGE SEQUENCE TIMING 21.6.9 A Stop bit is asserted on the SDAx pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN bit of the SSPxCON2 register. At the end of a receive/transmit, the SCLx line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDAx line low. When the SDAx line is sampled low, the Baud Rate Generator is reloaded and counts down to ‘0’.
PIC16(L)F1526/7 FIGURE 21-31: STOP CONDITION RECEIVE OR TRANSMIT MODE SCLx = 1 for TBRG, followed by SDAx = 1 for TBRG after SDAx sampled high. P bit (SSPxSTAT<4>) is set. Write to SSPxCON2, set PEN PEN bit (SSPxCON2<2>) is cleared by hardware and the SSPxIF bit is set Falling edge of 9th clock TBRG SCLx SDAx ACK P TBRG TBRG TBRG SCLx brought high after TBRG SDAx asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period. 21.6.
PIC16(L)F1526/7 FIGURE 21-32: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCLx = 0 SDAx line pulled low by another source SDAx released by master Sample SDAx. While SCLx is high, data does not match what is driven by the master. Bus collision has occurred. SDAx SCLx Set bus collision interrupt (BCLxIF) BCLxIF 2011-2013 Microchip Technology Inc.
PIC16(L)F1526/7 21.6.13.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDAx or SCLx are sampled low at the beginning of the Start condition (Figure 21-33). SCLx is sampled low before SDAx is asserted low (Figure 21-34). SDAx pin, the SDAx pin is asserted low at the end of the BRG count. The Baud Rate Generator is then reloaded and counts down to zero; if the SCLx pin is sampled as ‘0’ during this time, a bus collision does not occur.
PIC16(L)F1526/7 FIGURE 21-34: BUS COLLISION DURING START CONDITION (SCLX = 0) SDAx = 0, SCLx = 1 TBRG TBRG SDAx Set SEN, enable Start sequence if SDAx = 1, SCLx = 1 SCLx SCLx = 0 before SDAx = 0, bus collision occurs. Set BCLxIF. SEN SCLx = 0 before BRG time-out, bus collision occurs. Set BCLxIF.
PIC16(L)F1526/7 21.6.13.2 Bus Collision During a Repeated Start Condition If SDAx is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, Figure 21-36). If SDAx is sampled high, the BRG is reloaded and begins counting. If SDAx goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDAx at exactly the same time.
PIC16(L)F1526/7 21.6.13.3 Bus Collision During a Stop Condition The Stop condition begins with SDAx asserted low. When SDAx is sampled low, the SCLx pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPxADD and counts down to 0. After the BRG times out, SDAx is sampled. If SDAx is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 21-38).
PIC16(L)F1526/7 TABLE 21-3: Name INTCON SUMMARY OF REGISTERS ASSOCIATED WITH I2C™ OPERATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 78 PIE1 TMR1GIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 79 PIE2 OSFIE TMR5GIE TMR3GIE — BCL1IE TMR10IE TMR8IE CCP2IE 80 PIE4 CCP10IE CCP9IE RC2IE TX2IE CCP8IE CCP7IE BCL2IE SSP2IE 82 PIR1 TMR1GIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF
PIC16(L)F1526/7 21.7 BAUD RATE GENERATOR The MSSPx module has a Baud Rate Generator available for clock generation in both I2C and SPI Master modes. The Baud Rate Generator (BRG) reload value is placed in the SSPxADD register (Register 21-6). When a write occurs to SSPxBUF, the Baud Rate Generator will automatically begin counting down. Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state. module clock line.
PIC16(L)F1526/7 21.
PIC16(L)F1526/7 REGISTER 21-1: bit 0 SSPxSTAT: SSPx STATUS REGISTER (CONTINUED) BF: Buffer Full Status bit Receive (SPI and I2 C modes): 1 = Receive complete, SSPxBUF is full 0 = Receive not complete, SSPxBUF is empty Transmit (I2 C mode only): 1 = Data transmit in progress (does not include the ACK and Stop bits), SSPxBUF is full 0 = Data transmit complete (does not include the ACK and Stop bits), SSPxBUF is empty 2011-2013 Microchip Technology Inc.
PIC16(L)F1526/7 REGISTER 21-2: SSPxCON1: SSPx CONTROL REGISTER 1 R/C/HS-0/0 R/C/HS-0/0 R/W-0/0 R/W-0/0 WCOL SSPxOV SSPEN CKP R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SSPM<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared bit 7 WCOL: Write Collision Detect bit Master mode
PIC16(L)F1526/7 REGISTER 21-3: SSPxCON2: SSPx CONTROL REGISTER 2 R/W-0/0 R-0/0 R/W-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/W/HS-0/0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware S = User set bit 7 GCEN: General Call Enable bit
PIC16(L)F1526/7 REGISTER 21-4: SSPxCON3: SSPx CONTROL REGISTER 3 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only)(3) 1 = Indicates the I2C bus is
PIC16(L)F1526/7 REGISTER 21-5: R/W-1/1 SSPxMSK: SSPx MASK REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 MSK<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 MSK<7:1>: Mask bits 1 = The received address bit n is compared to SSPxADD to detect I2C address match 0 = The received address
PIC16(L)F1526/7 22.0 Note: ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) These devices typically do not have internal clocks for baud rate generation and require the external clock signal provided by a master synchronous device. The EUSART module includes the following capabilities: • • • • • • • • • • The PIC16(L)F1526/7 devices have two EUSARTs. Therefore, all information in this section refers to both EUSART 1 and EUSART 2.
PIC16(L)F1526/7 FIGURE 22-2: EUSART RECEIVE BLOCK DIAGRAM CREN RXx/DTx pin Baud Rate Generator Data Recovery FOSC BRG16 +1 SPxBRGH SPxBRGL RSR Register MSb Pin Buffer and Control Multiplier x4 x16 x64 SYNC 1 X 0 0 0 BRGH X 1 1 0 0 BRG16 X 1 0 1 0 Stop RCIDL OERR (8) ••• 7 1 LSb 0 START RX9 ÷n n FERR RX9D RCxREG Register 8 FIFO Data Bus RCxIF RCxIE Interrupt The operation of the EUSART module is controlled through three registers: • Transmit Status and Control (TXxSTA) •
PIC16(L)F1526/7 22.1 EUSART Asynchronous Mode The EUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a VOH mark state which represents a ‘1’ data bit, and a VOL space state which represents a ‘0’ data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission.
PIC16(L)F1526/7 22.1.1.5 TSR Status 22.1.1.7 The TRMT bit of the TXxSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXxREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied to this bit, so the user needs to poll this bit to determine the TSR status. Note: 22.1.1.
PIC16(L)F1526/7 FIGURE 22-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXxREG Word 1 BRG Output (Shift Clock) TXx/CKx pin Word 2 Start bit bit 0 bit 1 Word 1 1 TCY TXxIF bit (Interrupt Reg. Flag) bit 7/8 Stop bit Start bit Word 2 bit 0 1 TCY TRMT bit (Transmit Shift Reg. Empty Flag) Word 1 Transmit Shift Reg Word 2 Transmit Shift Reg This timing diagram shows two consecutive transmissions.
PIC16(L)F1526/7 22.1.2 EUSART ASYNCHRONOUS RECEIVER The Asynchronous mode would typically be used in RS-232 systems. The receiver block diagram is shown in Figure 22-2. The data is received on the RXx/DTx pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate.
PIC16(L)F1526/7 22.1.2.3 Receive Interrupts The RCxIF interrupt flag bit of the PIR1/PIR4 register is set whenever the EUSART receiver is enabled and there is an unread character in the receive FIFO. The RCxIF interrupt flag bit is read-only, it cannot be set or cleared by software.
PIC16(L)F1526/7 22.1.2.8 Asynchronous Reception Set-up: 22.1.2.9 1. Initialize the SPxBRGH:SPxBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 22.4 “EUSART Baud Rate Generator (BRG)”). 2. Set the RXx/DTx and TXx/CKx TRIS controls to ‘1’. 3. Enable the serial port by setting the SPEN bit and the RXx/DTx pin TRIS bit. The SYNC bit must be clear for asynchronous operation. 4.
PIC16(L)F1526/7 TABLE 22-2: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BAUD1CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 267 BAUD2CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 267 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 92 INTCON PIE1 TMR1GIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 93 PIE4 CCP10IE CCP9IE RC2IE TX2IE CCP8IE CCP7IE BCL2IE SSP2IE 96 PIR1 TMR1GI
PIC16(L)F1526/7 22.2 Clock Accuracy with Asynchronous Operation The factory calibrates the internal oscillator block output (HFINTOSC). However, the HFINTOSC frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. DS41458C-page 264 The first (preferred) method uses the OSCTUNE register to adjust the HFINTOSC output.
PIC16(L)F1526/7 22.
PIC16(L)F1526/7 REGISTER 22-2: RCxSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RXx/DTx and TXx/CKx pins as serial port pins) 0 = Serial port disabled (held in Reset) bit
PIC16(L)F1526/7 REGISTER 22-3: BAUDxCON: BAUD RATE CONTROL REGISTER R-0/0 R-1/1 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-
PIC16(L)F1526/7 22.4 EUSART Baud Rate Generator (BRG) The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit of the BAUDxCON register selects 16-bit mode. The SPxBRGH:SPxBRGL register pair determines the period of the free running baud rate timer.
PIC16(L)F1526/7 TABLE 22-4: SUMMARY OF REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page BAUD1CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 267 BAUD2CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 267 RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 266 RC2STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 266 SP1BRGL EUSART1 Baud Rate Generator, Low Byte 268* SP1BRGH EUSART1 Baud Rate Generator, H
PIC16(L)F1526/7 TABLE 22-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 20.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 18.432 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 16.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 — — — — — — — — — — — — 1200 1221 1.73 255 1200 0.00 239 1202 0.16 207 1200 0.00 143 2400 2404 0.16 129 2400 0.
PIC16(L)F1526/7 TABLE 22-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 8.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 4.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 3.6864 MHz Actual Rate FOSC = 1.000 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 300 1200 — — — — — — — 1202 — 0.16 — 207 — 1200 — 0.00 — 191 300 1202 0.16 0.16 207 51 2400 2404 0.16 207 2404 0.
PIC16(L)F1526/7 TABLE 22-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 1200 300.0 1200 0.00 -0.01 16665 4166 300.0 1200 0.00 0.00 15359 3839 300.0 1200.1 0.00 0.01 13332 3332 300.0 1200 0.00 0.00 9215 2303 2400 2400 0.02 2082 2400 0.00 1919 2399.5 -0.02 1666 2400 0.00 1151 9600 9597 -0.
PIC16(L)F1526/7 22.4.1 AUTO-BAUD DETECT The EUSART module supports automatic detection and calibration of the baud rate. In the Auto-Baud Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RXx signal, the RXx signal is timing the BRG. The Baud Rate Generator is used to time the period of a received 55h (ASCII “U”) which is the Sync character for the LIN bus. The unique feature of this character is that it has five rising edges including the Stop bit edge.
PIC16(L)F1526/7 22.4.2 AUTO-BAUD OVERFLOW During the course of automatic baud detection, the ABDOVF bit of the BAUDxCON register will be set if the baud rate counter overflows before the fifth rising edge is detected on the RX pin. The ABDOVF bit indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the SPxBRGH:SPxBRGL register pair. After the ABDOVF bit has been set, the counter continues to count until the fifth rising edge is detected on the RXx/DTx pin.
PIC16(L)F1526/7 FIGURE 22-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Auto Cleared Bit set by user WUE bit RXx/DTx Line RCxIF Note 1: Cleared due to User Read of RCxREG The EUSART remains in Idle while the WUE bit is set.
PIC16(L)F1526/7 22.4.4 BREAK CHARACTER SEQUENCE The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. A Break character consists of a Start bit, followed by 12 ‘0’ bits and a Stop bit. To send a Break character, set the SENDB and TXEN bits of the TXxSTA register. The Break character transmission is then initiated by a write to the TXxREG. The value of data written to TXxREG will be ignored and all ‘0’s will be transmitted.
PIC16(L)F1526/7 22.5 EUSART Synchronous Mode Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line.
PIC16(L)F1526/7 22.5.1.4 1. 2. 3. Synchronous Master Transmission Set-up: 4. Initialize the SPxBRGH, SPxBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 22.4 “EUSART Baud Rate Generator (BRG)”). Set the RXx/DTx and TXx/CKx TRIS controls to ‘1’. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. Set the TRIS bits corresponding to the RXx/DTx and TXx/CKx I/O pins. 5. 6. 7. FIGURE 22-10: 8. 9.
PIC16(L)F1526/7 TABLE 22-7: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BAUD1CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 267 BAUD2CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 267 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 92 93 INTCON PIE1 TMR1GIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE PIE4 CCP10IE CCP9IE RC2IE TX2IE CCP8IE CCP7IE BCL2IE SSP2IE 96 PIR1
PIC16(L)F1526/7 22.5.1.5 Synchronous Master Reception Data is received at the RXx/DTx pin. The RXx/DTx pin output driver must be disabled by setting the corresponding TRIS bits when the EUSART is configured for synchronous master receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCxSTA register) or the Continuous Receive Enable bit (CREN of the RCxSTA register).
PIC16(L)F1526/7 FIGURE 22-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RXx/DTx pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TXx/CKx pin (SCKP = 0) TXx/CKx pin (SCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCxIF bit (Interrupt) Read RCxREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
PIC16(L)F1526/7 22.5.2 SYNCHRONOUS SLAVE MODE The following bits are used to configure the EUSART for Synchronous slave operation: • • • • • SYNC = 1 CSRC = 0 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 Setting the SYNC bit of the TXxSTA register configures the device for synchronous operation. Clearing the CSRC bit of the TXxSTA register configures the device as a slave.
PIC16(L)F1526/7 TABLE 22-9: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BAUD1CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 267 BAUD2CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 267 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 92 93 INTCON PIE1 TMR1GIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE PIE4 CCP10IE CCP9IE RC2IE TX2IE CCP8IE CCP7IE BCL2IE SSP2IE 96 PIR1
PIC16(L)F1526/7 22.5.2.3 EUSART Synchronous Slave Reception 22.5.2.4 The operation of the Synchronous Master and Slave modes is identical (Section 22.5.1.5 “Synchronous Master Reception”), with the following exceptions: • Sleep • CREN bit is always set, therefore the receiver is never Idle • SREN bit, which is a “don’t care” in Slave mode 1. 2. 3. A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep.
PIC16(L)F1526/7 23.0 IN-CIRCUIT SERIAL PROGRAMMING™ (ICSP™) ICSP™ programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can be done after the assembly process, allowing the device to be programmed with the most recent firmware or a custom firmware. Five pins are needed for ICSP™ programming: • ICSPCLK • ICSPDAT • MCLR/VPP • VDD • VSS In Program/Verify mode the program memory, user IDs and the Configuration Words are programmed through serial communications.
PIC16(L)F1526/7 FIGURE 23-2: PICkit™ PROGRAMMER STYLE CONNECTOR INTERFACE Pin 1 Indicator Pin Description* 1 = VPP/MCLR 1 2 3 4 5 6 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT 5 = ICSPCLK 6 = No Connect * The 6-pin header (0.100" spacing) accepts 0.025" square pins. For additional interface recommendations, refer to your specific device programmer manual prior to PCB design. It is recommended that isolation devices be used to separate the programming pins from other circuitry.
PIC16(L)F1526/7 24.0 INSTRUCTION SET SUMMARY 24.1 Read-Modify-Write Operations • Byte Oriented • Bit Oriented • Literal and Control Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction, or the destination designator ‘d’. A read operation is performed on a register even if the instruction writes to that register.
PIC16(L)F1526/7 FIGURE 24-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 OPCODE d f (FILE #) 0 d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 OPCODE b (BIT #) f (FILE #) 0 b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE 8 7 0 k (literal) k = 8-bit immediate value CALL and GOTO instructions only 13 11 10 OPCODE 0 k (literal
PIC16(L)F1526/7 TABLE 24-3: INSTRUCTION SET Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ADDWFC ANDWF ASRF LSLF LSRF CLRF CLRW COMF DECF INCF IORWF MOVF MOVWF RLF RRF SUBWF SUBWFB SWAPF XORWF f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d f, d Add W and f Add with Carry W and f AND W with f Arithmetic Right Shift Logical Left Shift Logical Right Shift Clear f Clear W Complemen
PIC16(L)F1526/7 TABLE 24-3: INSTRUCTION SET (CONTINUED) Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes CONTROL OPERATIONS 2 2 2 2 2 2 2 2 BRA BRW CALL CALLW GOTO RETFIE RETLW RETURN k – k – k k k – Relative Branch Relative Branch with W Call Subroutine Call Subroutine with W Go to address Return from interrupt Return with literal in W Return from Subroutine CLRWDT NOP OPTION RESET SLEEP TRIS – – – – – f Clear Watchdog Timer No Operation Load OPTION_REG regi
PIC16(L)F1526/7 24.2 Instruction Descriptions ADDFSR Add Literal to FSRn ANDLW AND literal with W Syntax: [ label ] ADDFSR FSRn, k Syntax: [ label ] ANDLW Operands: -32 k 31 n [ 0, 1] Operands: 0 k 255 Operation: FSR(n) + k FSR(n) Status Affected: None Description: The signed 6-bit literal ‘k’ is added to the contents of the FSRnH:FSRnL register pair. k Operation: (W) .AND.
PIC16(L)F1526/7 BCF Bit Clear f Syntax: [ label ] BCF f,b BTFSC Bit Test f, Skip if Clear Syntax: [ label ] BTFSC f,b 0 f 127 0b7 Operands: 0 f 127 0b7 Operands: Operation: 0 (f) Operation: skip if (f) = 0 Status Affected: None Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared. Description: If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed.
PIC16(L)F1526/7 CALL Call Subroutine CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0 k 2047 Operands: None Operation: (PC)+ 1 TOS, k PC<10:0>, (PCLATH<6:3>) PC<14:11> Operation: Status Affected: None 00h WDT 0 WDT prescaler, 1 TO 1 PD Description: Call Subroutine. First, return address (PC + 1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH.
PIC16(L)F1526/7 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f) - 1 (destination); skip if result = 0 Operation: (f) + 1 (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in the W register.
PIC16(L)F1526/7 LSLF Logical Left Shift f {,d} MOVF Move f Syntax: [ label ] LSLF Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f<7>) C (f<6:0>) dest<7:1> 0 dest<0> Operation: (f) (dest) Status Affected: C, Z Description: The contents of register ‘f’ are shifted one bit to the left through the Carry flag. A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’.
PIC16(L)F1526/7 MOVIW Move INDFn to W Syntax: [ label ] MOVIW ++FSRn [ label ] MOVIW --FSRn [ label ] MOVIW FSRn++ [ label ] MOVIW FSRn-[ label ] MOVIW k[FSRn] Operands: n [0,1] mm [00,01, 10, 11] -32 k 31 Operation: INDFn W Effective address is determined by • FSR + 1 (preincrement) • FSR - 1 (predecrement) • FSR + k (relative offset) After the Move, the FSR value will be either: • FSR + 1 (all increments) • FSR - 1 (all decrements) • Unchanged Status Affected: MOVLP Move literal to PCL
PIC16(L)F1526/7 MOVWI Move W to INDFn Syntax: [ label ] MOVWI ++FSRn [ label ] MOVWI --FSRn [ label ] MOVWI FSRn++ [ label ] MOVWI FSRn-[ label ] MOVWI k[FSRn] Operands: Operation: Status Affected: n [0,1] mm [00,01, 10, 11] -32 k 31 W INDFn Effective address is determined by • FSR + 1 (preincrement) • FSR - 1 (predecrement) • FSR + k (relative offset) After the Move, the FSR value will be either: • FSR + 1 (all increments) • FSR - 1 (all decrements) Unchanged None No Operation Syntax: [
PIC16(L)F1526/7 RETFIE Return from Interrupt Syntax: [ label ] RETFIE RETURN Return from Subroutine Syntax: [ label ] None RETURN Operands: None Operands: Operation: TOS PC, 1 GIE Operation: TOS PC Status Affected: None Status Affected: None Description: Description: Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction.
PIC16(L)F1526/7 SUBLW Subtract W from literal Syntax: [ label ] RRF Rotate Right f through Carry Syntax: [ label ] Operands: 0 f 127 d [0,1] Operation: See description below Status Affected: C, DC, Z Status Affected: C Description: Description: The contents of register ‘f’ are rotated one bit to the right through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’.
PIC16(L)F1526/7 SWAPF Swap Nibbles in f XORLW Exclusive OR literal with W Syntax: [ label ] Syntax: [ label ] Operands: 0 f 127 d [0,1] Operation: SWAPF f,d (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) XORLW k Operands: 0 k 255 Operation: (W) .XOR. k W) Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register.
PIC16(L)F1526/7 25.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings(†) Ambient temperature under bias....................................................................................................... -40°C to +125°C Storage temperature ........................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS, PIC16F1526/7 .......................................................................... -0.
PIC16(L)F1526/7 PIC16F1526/7 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C FIGURE 25-1: VDD (V) 5.5 2.5 2.3 0 4 10 16 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 25-1 for each Oscillator mode’s supported frequencies. PIC16LF1526/7 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C VDD (V) FIGURE 25-2: 3.6 2.5 1.
PIC16(L)F1526/7 FIGURE 25-3: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE 125 -15% to +12.5% Temperature (°C) 85 60 ± 8% ± 6.5% 25 0 -15% to +12.5% -40 1.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) 2011-2013 Microchip Technology Inc.
PIC16(L)F1526/7 25.1 DC Characteristics: Supply Voltage PIC16LF1526/7 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F1526/7 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param. No. Sym. Characteristic Min. Typ† Max. Units Conditions 1.8 2.5 — — 3.6 3.6 V V FOSC 16 MHz FOSC 20 MHz 2.
PIC16(L)F1526/7 25.2 DC Characteristics: Supply Current (IDD) PIC16LF1526/7 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F1526/7 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Min. Conditions Typ† Max.
PIC16(L)F1526/7 25.2 DC Characteristics: Supply Current (IDD) (Continued) PIC16LF1526/7 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F1526/7 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Min. Typ† Max.
PIC16(L)F1526/7 25.2 DC Characteristics: Supply Current (IDD) (Continued) PIC16LF1526/7 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F1526/7 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Min. Typ† Max.
PIC16(L)F1526/7 25.3 DC Characteristics: Power-Down Currents (IPD) PIC16LF1526/7 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F1526/7 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Min. Power-down Currents D022 Base IPD D022 Base IPD D023 D023 Typ† Max.
PIC16(L)F1526/7 25.3 DC Characteristics: Power-Down Currents (IPD) (Continued) PIC16LF1526/7 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F1526/7 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Min.
PIC16(L)F1526/7 25.4 DC Characteristics: I/O Ports DC CHARACTERISTICS Param No. Sym. VIL Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Min. Typ† Max. Units Conditions Input Low Voltage I/O PORT: D030 — — 0.8 V 4.5V VDD 5.5V — — 0.15 VDD V 1.8V VDD 4.5V with Schmitt Trigger buffer — — 0.2 VDD V 2.0V VDD 5.5V with I2C™ levels — — 0.
PIC16(L)F1526/7 25.4 DC Characteristics: I/O Ports (Continued) DC CHARACTERISTICS Param No. Sym. Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Min. Typ† Max.
PIC16(L)F1526/7 25.5 Memory Programming Requirements Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended DC CHARACTERISTICS Param No. Sym. Characteristic Min. Typ† Max. Units Conditions Program Memory Programming Specifications D110 VIHH Voltage on MCLR/VPP pin 8.0 — 9.0 V D111 IDDP Supply Current during Programming — — 10 mA D112 VBE VDD for Bulk Erase 2.
PIC16(L)F1526/7 25.6 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. Sym. Characteristic Typ. Units C/W C/W C/W C/W C TH01 JA Thermal Resistance Junction to Ambient TH02 JC Thermal Resistance Junction to Case 48.3 28.0 26.1 Maximum Junction Temperature 1.
PIC16(L)F1526/7 25.7 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2.
PIC16(L)F1526/7 25.8 AC Characteristics: PIC16(L)F1526/7-I/E FIGURE 25-6: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1/CLKIN OS02 OS04 OS04 OS03 OSC2/CLKOUT (LP,XT,HS Modes) OSC2/CLKOUT (CLKOUT Mode) TABLE 25-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. OS01 Sym.
PIC16(L)F1526/7 TABLE 25-2: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. Sym. Characteristic Freq. Tolerance Min. Typ† Max. Units Conditions OS08 HFOSC Internal Calibrated HFINTOSC Frequency (Note 1) 6.5% — 16.0 — MHz VDD = 3.
PIC16(L)F1526/7 FIGURE 25-7: CLKOUT AND I/O TIMING Cycle Write Fetch Read Execute Q4 Q1 Q2 Q3 FOSC OS12 OS11 OS20 OS21 CLKOUT OS19 OS18 OS16 OS13 OS17 I/O pin (Input) OS14 OS15 I/O pin (Output) New Value Old Value OS18, OS19 TABLE 25-3: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. OS11 OS12 Sym. TosH2ckL Characteristic Min. Typ† Max.
PIC16(L)F1526/7 FIGURE 25-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Start-Up Time Internal Reset(1) Watchdog Timer Reset(1) 31 34 34 I/O pins Note 1: Asserted low.
PIC16(L)F1526/7 TABLE 25-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. Sym. Characteristic MCLR Pulse Width (low) Min. Typ† Max.
PIC16(L)F1526/7 FIGURE 25-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 49 47 TMR0 or TMR1 TABLE 25-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. Sym. Characteristic Min. Typ† Max. Units — — — — ns ns 40* TT0H T0CKI High Pulse Width No Prescaler With Prescaler 0.5 TCY + 20 10 41* TT0L T0CKI Low Pulse Width No Prescaler 0.
PIC16(L)F1526/7 FIGURE 25-11: CAPTURE/COMPARE/PWM TIMINGS (CCP) CCP (Capture mode) CC01 CC02 CC03 Note: Refer to Figure 25-5 for load conditions. TABLE 25-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP) Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param Sym. No. CC01* TccL CC02* TccH CC03* TccP * † Characteristic CCP Input Low Time CCP Input High Time CCP Input Period Min. Typ† Max. Units No Prescaler 0.
PIC16(L)F1526/7 TABLE 25-7: ANALOG-TO-DIGITAL CONVERTER (ADC) CHARACTERISTICS(1,2,3) Standard Operating Conditions (unless otherwise stated) Operating Temperature Tested at 25°C Param Sym. No. Characteristic Min. Typ† Max. Units Conditions AD01 NR Resolution — — 10 AD02 EIL Integral Error — ±1 ±1.7 AD03 EDL Differential Error — ±1 ±1 AD04 EOFF Offset Error — ±1 ±2.5 LSb VREF = 3.0V AD05 EGN LSb VREF = 3.
PIC16(L)F1526/7 FIGURE 25-12: ADC CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO AD134 1 TCY (TOSC/2(1)) AD131 Q4 AD130 ADC CLK 7 ADC Data 6 5 4 3 2 1 0 NEW_DATA OLD_DATA ADRES 1 TCY ADIF GO Sample DONE Sampling Stopped AD132 Note 1: If the ADC clock source is selected as RC, a time of TCY is added before the ADC clock starts. This allows the SLEEP instruction to be executed.
PIC16(L)F1526/7 TABLE 25-9: LOW DROPOUT (LDO) REGULATOR CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param Sym. No. Characteristic Min. Typ† Max. Units LDO01 LDO Regulation Voltage — 3.0 — V LDO02 LDO External Capacitor 0.1 — 1 F † Conditions Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
PIC16(L)F1526/7 FIGURE 25-15: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING CK US125 DT US126 Note: Refer to Figure 25-5 for load conditions. TABLE 25-11: USART SYNCHRONOUS RECEIVE REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param. No. Symbol Characteristic US125 TDTV2CKL SYNC RCV (Master and Slave) Data-hold before CK (DT hold time) US126 TCKL2DTL Data-hold after CK (DT hold time) 2011-2013 Microchip Technology Inc. Min.
PIC16(L)F1526/7 FIGURE 25-16: SPI MASTER MODE TIMING (CKE = 0, SMP = 0) SSx SP70 SCKx (CKP = 0) SP71 SP72 SP78 SP79 SP79 SP78 SCKx (CKP = 1) SP80 bit 6 - - - - - -1 MSb SDOx LSb SP75, SP76 SDIx MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 25-5 for load conditions.
PIC16(L)F1526/7 FIGURE 25-18: SPI SLAVE MODE TIMING (CKE = 0) SSx SP70 SCKx (CKP = 0) SP83 SP71 SP72 SP78 SP79 SP79 SP78 SCKx (CKP = 1) SP80 MSb SDOx LSb bit 6 - - - - - -1 SP77 SP75, SP76 SDIx MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 25-5 for load conditions.
PIC16(L)F1526/7 TABLE 25-12: SPI MODE REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. Symbol Characteristic Min. Typ† Max.
PIC16(L)F1526/7 FIGURE 25-20: I2C™ BUS START/STOP BITS TIMING SCLx SP93 SP91 SP90 SP92 SDAx Stop Condition Start Condition Note: Refer to Figure 25-5 for load conditions. TABLE 25-13: I2C™ BUS START/STOP BITS REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param. No. Symbol SP90* TSU:STA SP91* THD:STA SP92* TSU:STO SP93 THD:STO Characteristic Start condition 100 kHz mode Min. Typ. Max.
PIC16(L)F1526/7 TABLE 25-14: I2C™ BUS DATA REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param. No. Symbol SP100* THIGH Characteristic Clock high time Min. Max. Units Conditions 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz 1.5TCY — — 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.
PIC16(L)F1526/7 26.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range.
PIC16(L)F1526/7 FIGURE 26-1: IDD, LP OSCILLATOR, FOSC = 32 kHz, PIC16LF1526 ONLY 30 Max: 85°C + 3 Typical: 25°C 25 Max. IDD (μA) 20 Typical 15 10 5 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) IDD, LP OSCILLATOR, FOSC = 32 kHz, PIC16F1526/7 ONLY FIGURE 26-2: 45 Max. Max: 85°C + 3 Typical: 25°C 40 35 Typical IDD (μA) 30 25 20 15 10 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) DS41458C-page 332 2011-2013 Microchip Technology Inc.
PIC16(L)F1526/7 FIGURE 26-3: IDD TYPICAL, XT AND EXTRC OSCILLATOR, PIC16LF1526 ONLY 400 Typical: 25°C 350 4 MHz XT 300 IDD (μA) 250 200 150 1 MHz XT 100 50 1 MHz EXTRC 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 26-4: IDD MAXIMUM, XT AND EXTRC OSCILLATOR, PIC16LF1526 ONLY 450 400 Max: 85°C + 3 4 MHz XT 350 IDD (μA) 300 250 200 1 MHz XT 150 100 50 1 MHz EXTRC 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.
PIC16(L)F1526/7 FIGURE 26-5: IDD TYPICAL, XT AND EXTRC OSCILLATOR, PIC16F1526/7 ONLY 500 4 MHz XT Typical: 25°C 450 400 4 MHz EXTRC 350 IDD (μA) 300 250 1 MHz XT 200 150 1 MHz EXTRC 100 50 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) IDD MAXIMUM, XT AND EXTRC OSCILLATOR, PIC16F1526/7 ONLY FIGURE 26-6: 600 4 MHz XT Max: 85°C + 3 500 4 MHz EXTRC IDD (μA) 400 1 MHz XT 300 200 1 MHz EXTRC 100 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.
PIC16(L)F1526/7 FIGURE 26-7: IDD, EXTERNAL CLOCK (ECL), LOW-POWER MODE, FOSC = 32 kHz, PIC16LF1526 ONLY 30 Max: 85°C + 3 Typical: 25°C 25 Max. IDD (μA) 20 15 Typical 10 5 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 26-8: IDD, EXTERNAL CLOCK (ECL), LOW-POWER MODE, FOSC = 32 kHz, PIC16F1526/7 ONLY 40 Max: 85°C + 3 Typical: 25°C 35 Max. 30 IDD (μA) Typical 25 20 15 10 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.
PIC16(L)F1526/7 FIGURE 26-9: IDD, EXTERNAL CLOCK (ECL), LOW-POWER MODE, FOSC = 500 kHz, PIC16LF1526 ONLY 70 Max: 85°C + 3 Typical: 25°C 60 Max. IDD (μA) 50 40 Typical 30 20 10 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 26-10: IDD, EXTERNAL CLOCK (ECL), LOW-POWER MODE, FOSC = 500 kHz, PIC16F1526/7 ONLY 80 70 Max. 60 IDD (μA) Typical 50 40 30 20 Max: 85°C + 3 Typical: 25°C 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.
PIC16(L)F1526/7 FIGURE 26-11: IDD TYPICAL, EXTERNAL CLOCK (ECM), MEDIUM-POWER MODE, PIC16LF1526 ONLY 400 Typical: 25°C 350 4 MHz 300 IDD (μA) 250 200 150 100 1 MHz 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 26-12: IDD MAXIMUM, EXTERNAL CLOCK (ECM), MEDIUM-POWER MODE, PIC16LF1526 ONLY 450 Max: 85°C + 3 400 4 MHz 350 IDD (μA) 300 250 200 150 1 MHz 100 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.
PIC16(L)F1526/7 FIGURE 26-13: IDD TYPICAL, EXTERNAL CLOCK (ECM), MEDIUM-POWER MODE, PIC16F1526/7 ONLY 450 Typical: 25°C 400 4 MHz 350 IDD (μA) 300 250 200 1 MHz 150 100 50 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 26-14: IDD MAXIMUM, EXTERNAL CLOCK (ECM), MEDIUM-POWER MODE, PIC16F1526/7 ONLY 500 Max: 85°C + 3 450 400 4 MHz IDD (μA) 350 300 250 1 MHz 200 150 100 50 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.
PIC16(L)F1526/7 FIGURE 26-15: IDD TYPICAL, EXTERNAL CLOCK (ECH), HIGH-POWER MODE, PIC16LF1526 ONLY 1.8 1.6 20 MHz Typical: 25°C 1.4 16 MHz IDD (mA) 1.2 1.0 0.8 0.6 8 MHz 0.4 0.2 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 26-16: IDD MAXIMUM, EXTERNAL CLOCK (ECH), HIGH-POWER MODE, PIC16LF1526 ONLY 2.0 1.8 20 MHz Max: 85°C + 3 1.6 IDD (mA) 1.4 16 MHz 1.2 1.0 0.8 8 MHz 0.6 0.4 0.2 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.
PIC16(L)F1526/7 FIGURE 26-17: IDD TYPICAL, EXTERNAL CLOCK (ECH), HIGH-POWER MODE, PIC16F1526/7 ONLY 1.8 Typical: 25°C 1.6 20 MHz 1.4 IDD (mA) 1.2 16 MHz 1.0 0.8 0.6 8 MHz 0.4 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 26-18: IDD MAXIMUM, EXTERNAL CLOCK (ECH), HIGH-POWER MODE, PIC16F1526/7 ONLY 2.0 1.8 Max: 85°C + 3 20 MHz 1.6 1.4 IDD (mA) 16 MHz 1.2 1.0 0.8 8 MHz 0.6 0.4 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.
PIC16(L)F1526/7 FIGURE 26-19: IDD, LFINTOSC, FOSC = 31 kHz, PIC16LF1526 ONLY 30 Max: 85°C + 3 Typical: 25°C 25 Max. IDD (μA) 20 15 Typical 10 5 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 26-20: IDD, LFINTOSC, FOSC = 31 kHz, PIC16F1526/7 ONLY 35 Max. 30 IDD (μA) 25 Typical 20 15 10 Max: 85°C + 3 Typical: 25°C 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) 2011-2013 Microchip Technology Inc.
PIC16(L)F1526/7 FIGURE 26-21: IDD, MFINTOSC, FOSC = 500 kHz, PIC16LF1526 ONLY 400 Max. Max: 85°C + 3 Typical: 25°C 350 IDD (μA) 300 Typical 250 200 150 100 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) IDD, MFINTOSC, FOSC = 500 kHz, PIC16F1526/7 ONLY FIGURE 26-22: 500 Max. Max: 85°C + 3 Typical: 25°C 450 Typical 400 IDD (μA) 350 300 250 200 150 100 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) DS41458C-page 342 2011-2013 Microchip Technology Inc.
PIC16(L)F1526/7 FIGURE 26-23: IDD TYPICAL, HFINTOSC, PIC16LF1526 ONLY 1.8 16 MHz Typical: 25°C 1.6 1.4 IDD (mA) 1.2 8 MHz 1.0 0.8 4 MHz 0.6 0.4 0.2 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 26-24: IDD MAXIMUM, HFINTOSC, PIC16LF1526 ONLY 2.0 16 MHz 1.8 Max: 85°C + 3 1.6 IDD (mA) 1.4 1.2 8 MHz 1.0 4 MHz 0.8 0.6 0.4 0.2 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) 2011-2013 Microchip Technology Inc.
PIC16(L)F1526/7 FIGURE 26-25: IDD TYPICAL, HFINTOSC, PIC16F1526/7 ONLY 1.8 16 MHz 1.6 Typical: 25°C 1.4 IDD (mA) 1.2 8 MHz 1.0 4 MHz 0.8 0.6 0.4 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 26-26: IDD MAXIMUM, HFINTOSC, PIC16F1526/7 ONLY 2.0 16 MHz Max: 85°C + 3 1.8 1.6 1.4 8 MHz IDD (mA) 1.2 1.0 4 MHz 0.8 0.6 0.4 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) DS41458C-page 344 2011-2013 Microchip Technology Inc.
PIC16(L)F1526/7 FIGURE 26-27: IDD TYPICAL, HS OSCILLATOR, PIC16LF1526 ONLY 2.5 Typical: 25°C 20 MHz 2.0 IDD (mA) 1.5 1.0 8 MHz 4 MHz 0.5 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 3.6 3.8 VDD (V) FIGURE 26-28: IDD MAXIMUM, HS OSCILLATOR, PIC16LF1526 ONLY 2.5 20 MHz Max: 85°C + 3 2.0 IDD (mA) 1.5 8 MHz 1.0 4 MHz 0.5 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 VDD (V) 2011-2013 Microchip Technology Inc.
PIC16(L)F1526/7 FIGURE 26-29: IDD TYPICAL, HS OSCILLATOR, PIC16F1526/7 ONLY 2.5 20 MHz Typical: 25°C 2.0 IDD (mA) 1.5 8 MHz 1.0 4 MHz 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 5.5 6.0 VDD (V) FIGURE 26-30: IDD MAXIMUM, HS OSCILLATOR, PIC16F1526/7 ONLY 3.0 20 MHz Max: 85°C + 3 2.5 IDD (mA) 2.0 1.5 8 MHz 1.0 4 MHz 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VDD (V) DS41458C-page 346 2011-2013 Microchip Technology Inc.
PIC16(L)F1526/7 FIGURE 26-31: IPD BASE, SLEEP MODE, PIC16LF1526 ONLY 450 Max: 85°C + 3 M 3 Typical: 25°C 400 Max. 350 IPD D (nA) 300 250 200 150 100 Typical 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 26-32: IPD BASE, LOW-POWER SLEEP MODE, VREGPM = 1, PIC16F1526/7 ONLY 600 Max. Max: 85°C + 3 Typical: 25°C 500 IPD (nA) 400 300 Typical 200 100 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) 2011-2013 Microchip Technology Inc.
PIC16(L)F1526/7 FIGURE 26-33: IPD, WATCHDOG TIMER (WDT), PIC16LF1526 ONLY 1.4 Max: 85°C + 3 Typical: 25°C 1.2 Max. 1.0 IPD (μA (μA) 0 8 0.8 Typical 0.6 0.4 0.2 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 26-34: IPD, WATCHDOG TIMER (WDT), PIC16F1526/7 ONLY 1.2 Max: 85°C + 3 Typical: 25°C 1.0 Max. IPD (μA A) 0.8 Typical 0.6 0.4 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) DS41458C-page 348 2011-2013 Microchip Technology Inc.
PIC16(L)F1526/7 FIGURE 26-35: IPD, FIXED VOLTAGE REFERENCE (FVR), PIC16LF1526 ONLY 25 Max. Typical 20 IPD (μA A) 15 10 Max: 85°C + 3 Typical: 25°C 5 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 26-36: IPD, FIXED VOLTAGE REFERENCE (FVR), PIC16F1526/7 ONLY 30 Max. 25 IPD (μA) 20 Typical 15 10 Max: 85°C + 3 Typical: 25°C 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) 2011-2013 Microchip Technology Inc.
PIC16(L)F1526/7 FIGURE 26-37: IPD, BROWN-OUT RESET (BOR), BORV = 1, PIC16LF1526 ONLY 12 Max. Max: 85°C + 3 Typical: 25°C 10 8 IPD D (μA) Typical 6 4 2 0 1 6 1.6 1 8 1.8 2 0 2.0 2 2 2.2 2 4 2.4 2 6 2.6 2 8 2.8 3 0 3.0 3 2 3.2 3 4 3.4 3 6 3.6 3 8 3.8 VDD (V) FIGURE 26-38: IPD, BROWN-OUT RESET (BOR), BORV = 1, PIC16F1526/7 ONLY 14 Max Max. Max: 85°C + 3 Ma Typical: 25°C 12 IPD (μA) 10 Typical 8 6 4 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.
PIC16(L)F1526/7 FIGURE 26-39: IPD, SECONDARY OSCILLATOR, FOSC = 32 kHz, PIC16LF1526 ONLY 6.0 Max: 85°C + 3 Typical: 25°C 5.0 Max. IPD (μA A) 4.0 3.0 Typical 2.0 1.0 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 26-40: IPD, SECONDARY OSCILLATOR, FOSC = 32 kHz, PIC16F1526/7 ONLY 12 Max: 85°C + 3 Typical: 25°C 10 Max. IPD (μA) 8 Typical 6 4 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) 2011-2013 Microchip Technology Inc.
PIC16(L)F1526/7 FIGURE 26-41: VOH vs. IOH OVER TEMPERATURE, VDD = 5.5V, PIC16F1526/7 ONLY 6 5 VOH (V) 4 3 125°C Typical 2 -40°C Graph represents 3 Limits 1 0 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 IOH (mA) FIGURE 26-42: VOL vs. IOL OVER TEMPERATURE, VDD = 5.5V, PIC16F1526/7 ONLY 5 4 VOL (V) 125°C Graph represents 3 Limits 3 Typical 2 -40°C 1 0 0 DS41458C-page 352 10 20 30 40 50 IOL (mA) 60 70 80 90 100 2011-2013 Microchip Technology Inc.
PIC16(L)F1526/7 FIGURE 26-43: VOH vs. IOH OVER TEMPERATURE, VDD = 3.0V 3.5 Graph represents 3 Limits 3.0 VOH (V) 2.5 2.0 125°C 1.5 Typical 1.0 -40°C 0.5 0.0 -15 -13 -11 -9 -7 -5 -3 -1 IOH (mA) FIGURE 26-44: VOL vs. IOL OVER TEMPERATURE, VDD = 3.0V 3.0 125°C Graph represents 3 Limits 2.5 Typical VOL (V) 2.0 -40°C 1.5 1.0 0.5 0.0 0 5 10 15 20 25 30 35 40 IOL (mA) 2011-2013 Microchip Technology Inc.
PIC16(L)F1526/7 FIGURE 26-45: VOH vs. IOH OVER TEMPERATURE, VDD = 1.8V, PIC16LF1526 ONLY 2.0 Graph represents 3 Limits 1.8 1.6 VOH (V) 1.4 125°C 1.2 1.0 Typical 0.8 0.6 -40°C 0.4 0.2 0.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 IOH (mA) FIGURE 26-46: VOL vs. IOL OVER TEMPERATURE, VDD = 1.8V, PIC16LF1526 ONLY 1.8 Graph represents 3 Limits 1.6 1.4 125°C 1.2 VOL (V) Typical 1.0 -40°C 0.8 0.6 0.4 0.2 0.
PIC16(L)F1526/7 FIGURE 26-47: POR RELEASE VOLTAGE 1.70 1.68 Max. 1.66 Voltage (V) 1.64 Typical 1.62 Min. 1.60 1.58 1.56 Max: Typical + 3 Typical: 25°C Min: Typical - 3 1.54 1.52 1.50 -60 -40 -20 0 20 40 60 80 100 120 140 120 140 Temperature (°C) FIGURE 26-48: POR REARM VOLTAGE, PIC16F1526/7 ONLY 1.54 Max: Typical + 3 Typical: 25°C Min: Typical - 3 1.52 1.50 Max. Voltage (V) 1.48 1.46 1.44 Typical 1.42 1.40 Min. 1.38 1.36 1.
PIC16(L)F1526/7 FIGURE 26-49: BROWN-OUT RESET VOLTAGE, BORV = 1, PIC16LF1526 ONLY 2.00 Max. Voltage (V) 1.95 Typical 1.90 1.85 Min. Max: Typical + 3 Min: Typical - 3 1.80 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 26-50: BROWN-OUT RESET HYSTERESIS, BORV = 1, PIC16LF1526 ONLY 60 50 Max. Max: Typical + 3 Typical: 25°C Min: Typical - 3 Voltage (mV) 40 Typical 30 20 Min.
PIC16(L)F1526/7 FIGURE 26-51: BROWN-OUT RESET VOLTAGE, BORV = 1, PIC16F1526/7 ONLY 2.60 Max. 2.55 Voltage (V) 2.50 Typical 2.45 Min. 2.40 Max: Typical + 3 Min: Typical - 3 2.35 2.30 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 26-52: BROWN-OUT RESET HYSTERESIS, BORV = 1, PIC16F1526/7 ONLY 70 Max. 60 Max: Typical + 3 Typical: 25°C Min: Typical - 3 Voltage (mV) 50 40 Typical 30 20 Min.
PIC16(L)F1526/7 FIGURE 26-53: BROWN-OUT RESET VOLTAGE, BORV = 0 2.80 2.75 Voltage (V) Max. 2.70 Typical 2.65 Min. Max: Typical + 3 Min: Typical - 3 2.60 2.55 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 26-54: BROWN-OUT RESET HYSTERESIS, BORV = 0 90 80 Min. 70 Voltage (mV) 60 Typical 50 40 Max: Typical + 3 Typical: 25°C Min: Typical - 3 30 20 Max.
PIC16(L)F1526/7 FIGURE 26-55: LOW-POWER BROWN-OUT RESET VOLTAGE, LPBOR = 0 2.50 Max. Max: Typical + 3 Min: Typical - 3 2.40 Voltage (V) 2.30 Typical 2.20 2.10 2.00 Min. 1.90 1.80 -60 -40 -20 0 20 40 60 80 100 120 140 120 140 Temperature (°C) FIGURE 26-56: LOW-POWER BROWN-OUT RESET HYSTERESIS, LPBOR = 0 45 Max: Typical + 3 Typical: 25°C Min: Typical - 3 40 35 Max. Typical Voltage (mV) 30 25 Min.
PIC16(L)F1526/7 FIGURE 26-57: WDT TIME-OUT PERIOD 24 22 Max. Time (ms) 20 18 Typical 16 Min. 14 Max: Typical + 3 (-40°C to +125°C) Typical: statistical mean @ 25°C Min: Typical - 3 (-40°C to +125°C) 12 10 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 5.0 5.5 6.0 VDD (V) FIGURE 26-58: PWRT PERIOD 100 Max: Typical + 3 (-40°C to +125°C) Typical: statistical mean @ 25°C Min: Typical - 3 (-40°C to +125°C) 90 Max. Time (ms) 80 70 Typical 60 Min. 50 40 1.5 2.0 2.5 3.0 3.5 4.
PIC16(L)F1526/7 FIGURE 26-59: FVR STABILIZATION PERIOD 40 35 Max: Typical + 3 Typical: statistical mean @ 25°C Max. Time (us) 30 Typical 25 20 15 Note: The FVR Stabilization Period applies when: 1) coming out of Reset or exiting Sleep mode for PIC12/16LFxxxx devices. 2) when exiting Sleep mode with VREGPM = 1 for PIC12/16Fxxxx devices In all other cases, the FVR is stable when released from Reset. 10 5 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.
PIC16(L)F1526/7 FIGURE 26-60: LFINTOSC FREQUENCY OVER VDD AND TEMPERATURE, PIC16LF1526 ONLY 36 34 Max. Frequency (kHz) 32 30 Typical 28 Min. 26 24 Max: Typical + 3 (-40°C to +125°C) Typical: statistical mean @ 25°C Min: Typical - 3 (-40°C to +125°C) 22 20 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 26-61: LFINTOSC FREQUENCY OVER VDD AND TEMPERATURE, PIC16F1526/7 ONLY 36 34 Max. Frequency (kHz) 32 30 Typical 28 26 Min.
PIC16(L)F1526/7 FIGURE 26-62: SLEEP MODE, WAKE PERIOD WITH HFINTOSC SOURCE, PIC16LF1526/7 ONLY 5.0 4.5 Max. 4.0 Time (us) 3.5 Typical 3.0 2.5 2.0 1.5 Max: 85°C + 3 Typical: 25°C 1.0 0.5 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) 2011-2013 Microchip Technology Inc.
PIC16(L)F1526/7 FIGURE 26-63: LOW-POWER SLEEP MODE, WAKE PERIOD WITH HFINTOSC SOURCE, VREGPM = 1, PIC16F1526/7 ONLY 35 Max. 30 Typical Time (us) 25 20 15 10 Max: 85°C + 3 Typical: 25°C 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 5.5 6.0 VDD (V) FIGURE 26-64: SLEEP MODE, WAKE PERIOD WITH HFINTOSC SOURCE, VREGPM = 0, PIC16F1526/7 ONLY 12 Max. 10 Time (us) 8 Typical 6 4 Max: 85°C + 3 Typical: 25°C 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.
PIC16(L)F1526/7 27.
PIC16(L)F1526/7 27.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 27.
PIC16(L)F1526/7 27.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC16(L)F1526/7 27.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 27.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
PIC16(L)F1526/7 28.0 PACKAGING INFORMATION 28.1 Package Marking Information 64-Lead TQFP (10x10x1mm) XXXXXXXXXXX XXXXXXXXXXX XXXXXXXXXXX YYWWNNN PIC16LF1527 -E/PT e3 1245253 64-Lead QFN (9X9X0.9mm) XXXXXXXXXXX XXXXXXXXXXX XXXXXXXXXXX YYWWNNN Legend: XX...
PIC16(L)F1526/7 28.2 Package Details The following sections give the technical details of the packages.
PIC16(L)F1526/7 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011-2013 Microchip Technology Inc.
PIC16(L)F1526/7 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41458C-page 372 2011-2013 Microchip Technology Inc.
PIC16(L)F1526/7 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011-2013 Microchip Technology Inc.
PIC16(L)F1526/7 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41458C-page 374 2011-2013 Microchip Technology Inc.
PIC16(L)F1526/7 APPENDIX A: DATA SHEET REVISION HISTORY Revision A (01/2011) Original release. Revision B (05/2011) Electrical Spec updates. Revision C (01/2013) Updated Electrical Spec and added Characterization Data Graphs. 2011-2013 Microchip Technology Inc.
PIC16(L)F1526/7 NOTES: DS41458C-page 376 2011-2013 Microchip Technology Inc.
PIC16(L)F1526/7 INDEX A Absolute Maximum Ratings .............................................. 301 AC Characteristics Industrial and Extended ............................................ 315 Load Conditions ........................................................ 314 ACKSTAT ......................................................................... 235 ACKSTAT Status Flag ...................................................... 235 ADC ..........................................................................
PIC16(L)F1526/7 External Modes ........................................................... 51 EC ....................................................................... 51 HS ....................................................................... 51 LP........................................................................ 51 OST..................................................................... 52 RC....................................................................... 53 XT ............................
PIC16(L)F1526/7 ADDWF..................................................................... 291 ADDWFC .................................................................. 291 ANDLW ..................................................................... 291 ANDWF..................................................................... 291 BRA........................................................................... 292 CALL ......................................................................... 293 CALLW.........
PIC16(L)F1526/7 PCL and PCLATH ............................................................... 15 PCL Register....................................................................... 27 PCLATH Register................................................................ 27 PCON Register ............................................................. 28, 71 PIE1 Register ................................................................ 28, 79 PIE2 Register .............................................................
PIC16(L)F1526/7 PORTF...................................................................... 133 PORTG ..................................................................... 136 RCxSTA (Receive Status and Control)..................... 266 Special Function, Summary ........................................ 28 SSPxADD (MSSPx Address and Baud Rate, I2C Mode) ......................................................... 254 SSPxCON1 (MSSPx Control 1) ................................ 251 SSPxCON2 (SSPx Control 2) .....
PIC16(L)F1526/7 I2C Bus Data ............................................................. 329 I2C Bus Start/Stop Bits.............................................. 329 I2C Master Mode (7 or 10-Bit Transmission) ............ 236 I2C Master Mode (7-Bit Reception) ........................... 238 I2C Stop Condition Receive or Transmit Mode ......... 240 INT Pin Interrupt.......................................................... 76 Internal Oscillator Switch Timing.................................
PIC16(L)F1526/7 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC16(L)F1526/7 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PIC16(L)F1526/7 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. [X](1) PART NO.
PIC16(L)F1526/7 NOTES: DS41458C-page 386 2011-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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