Datasheet

PIC16(L)F1516/7/8/9
DS41452C-page 80  2010-2012 Microchip Technology Inc.
TABLE 7-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
REGISTER 7-5: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
R/W-0/0 U-0 U-0 U-0 R/W-0/0 U-0 U-0 R/W-0/0
OSFIF
— — —BCLIF — — CCP2IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 OSFIF: Oscillator Fail Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 6-4 Unimplemented: Read as ‘0’
bit 3 BCLIF: MSSP Bus Collision Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 2-1 Unimplemented: Read as ‘0’
bit 0 CCP2IF: CCP2 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 76
OPTION_REG
WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 151
PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 77
PIE2
OSFIE
— — —BCLIE— — CCP2IE
78
PIR1
TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
79
PIR2
OSFIF
— — —BCLIF— — CCP2IF
80
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by Interrupts.