Datasheet

 2010-2012 Microchip Technology Inc. DS41452C-page 65
PIC16(L)F1516/7/8/9
FIGURE 6-2: BROWN-OUT SITUATIONS
6.3 Register Definitions: BOR Control
REGISTER 6-1: BORCON: BROWN-OUT RESET CONTROL REGISTER
R/W-1/u R/W-0/u U-0 U-0 U-0 U-0 U-0 R-q/u
SBOREN BORFS — — — — — BORRDY
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 7 SBOREN: Software Brown-out Reset Enable bit
(1)
If BOREN <1:0> in Configuration Words  01:
SBOREN is read/write, but has no effect on the BOR
If BOREN <1:0>
in Configuration Words = 01:
1 =BOR Enabled
0 =BOR Disabled
bit 6 BORFS: Brown-out Reset Fast Start bit
(1)
If BOREN<1:0> = 11 (Always on) or BOREN<1:0> = 00 (Always off)
BORFS is Read/Write, but has no effect.
If BOREN <1:0> =
10 (Disabled in Sleep) or BOREN<1:0> = 01 (Under software control):
1 = Band gap is forced on always (covers sleep/wake-up/operating cases)
0 = Band gap operates normally, and may turn off
bit 5-1 Unimplemented: Read as ‘0’
bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit
1 = The Brown-out Reset circuit is active
0 = The Brown-out Reset circuit is inactive
Note 1: BOREN<1:0> bits are located in Configuration Words.
TPWRT
(1)
VBOR
V
DD
Internal
Reset
VBOR
V
DD
Internal
Reset
TPWRT
(1)
< TPWRT
TPWRT
(1)
VBOR
V
DD
Internal
Reset
Note 1: TPWRT delay only if PWRTE bit is programmed to ‘0’.