Datasheet

PIC16(L)F1516/7/8/9 DS41452C-page 28  2010-2012 Microchip Technology Inc.
TABLE 3-6: PIC16(L)F1518/9 MEMORY MAP (CONTINUED)
Legend: = Unimplemented data memory locations, read as ‘0’.
BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30
C00h
C0Bh
Core Registers
(Tab le 3 -2 )
C80h
C8Bh
Core Registers
(Tab le 3 -2 )
D00h
D0Bh
Core Registers
(Tab le 3 -2 )
D80h
D8Bh
Core Registers
(Tab le 3 -2 )
E00h
E0Bh
Core Registers
(Tab le 3 -2 )
E80h
E8Bh
Core Registers
(Tab le 3 -2 )
F00h
F0Bh
Core Registers
(Tab le 3 -2 )
C0Ch
Unimplemented
Read as ‘0’
C8Ch
Unimplemented
Read as ‘0’
D0Ch
Unimplemented
Read as ‘0’
D8Ch
Unimplemented
Read as ‘0’
E0Ch
Unimplemented
Read as ‘0’
E8Ch
Unimplemented
Read as ‘0’
F0Ch
Unimplemented
Read as ‘0’
C6Fh CEFh D6Fh DEFh E6Fh EEFh F6Fh
C70h
Common RAM
(Accesses
70h – 7Fh)
CF0h
Common RAM
(Accesses
70h – 7Fh)
D70h
Common RAM
(Accesses
70h – 7Fh)
DF0h
Common RAM
(Accesses
70h – 7Fh)
E70h
Common RAM
(Accesses
70h – 7Fh)
EF0h
Common RAM
(Accesses
70h – 7Fh)
F70h
Common RAM
(Accesses
70h – 7Fh)
C7Fh
CFFh D7Fh DFFh E7Fh EFFh F7Fh
Bank 31
F80h
F8Bh
Core Registers
(Tab le 3 -2 )
F8Ch
FE3h
Unimplemented
Read as ‘0’
FE4h
STATUS_SHAD
FE5h
WREG_SHAD
FE6h
BSR_SHAD
FE7h
PCLATH_SHAD
FE8h
FSR0L_SHAD
FE9h
FSR0H_SHAD
FEAh
FSR1L_SHAD
FEBh
FSR1H_SHAD
FECh
—
FEDh
STKPTR
FEEh
TOSL
FEFh
TOSH
FF0h
Common RAM
(Accesses
70h – 7Fh)
FFFh