Datasheet

PIC16(L)F1516/7/8/9
DS41452C-page 272  2010-2012 Microchip Technology Inc.
DECFSZ Decrement f, Skip if 0
Syntax: [ label ] DECFSZ f,d
Operands: 0
 f  127
d
 [0,1]
Operation: (f) - 1
 (destination);
skip if result =
0
Status Affected: None
Description: The contents of register ‘f’ are decre-
mented. If ‘d’ is ‘
0’, the result is placed
in the W register. If ‘d’ is ‘
1’, the result
is placed back in register ‘f’.
If the result is ‘
1’, the next instruction is
executed. If the result is ‘
0’, then a
NOP is executed instead, making it a
2-cycle instruction.
GOTO Unconditional Branch
Syntax: [ label ] GOTO k
Operands: 0
 k  2047
Operation: k
 PC<10:0>
PCLATH<6:3>
 PC<14:11>
Status Affected: None
Description:
GOTO is an unconditional branch. The
eleven-bit immediate value is loaded
into PC bits <10:0>. The upper bits of
PC are loaded from PCLATH<4:3>.
GOTO is a two-cycle instruction.
INCF Increment f
Syntax: [ label ] INCF f,d
Operands: 0
 f  127
d
 [0,1]
Operation: (f) + 1
 (destination)
Status Affected: Z
Description: The contents of register ‘f’ are incre-
mented. If ‘d’ is ‘
0’, the result is placed
in the W register. If ‘d’ is ‘
1’, the result
is placed back in register ‘f’.
INCFSZ Increment f, Skip if 0
Syntax: [ label ] INCFSZ f,d
Operands: 0
 f  127
d
 [0,1]
Operation: (f) + 1
 (destination),
skip if result =
0
Status Affected: None
Description: The contents of register ‘f’ are incre-
mented. If ‘d’ is ‘
0’, the result is placed
in the W register. If ‘d’ is ‘
1’, the result
is placed back in register ‘f’.
If the result is ‘
1’, the next instruction is
executed. If the result is ‘
0’, a NOP is
executed instead, making it a
2-cycle
instruction.
IORLW Inclusive OR literal with W
Syntax: [ label ] IORLW k
Operands: 0
 k  255
Operation: (W) .OR. k
 (W)
Status Affected: Z
Description: The contents of the W register are
OR’ed with the eight-bit literal ‘k’. The
result is placed in the W register.
IORWF Inclusive OR W with f
Syntax: [ label ] IORWF f,d
Operands: 0
 f  127
d
 [0,1]
Operation: (W) .OR. (f)
 (destination)
Status Affected: Z
Description: Inclusive OR the W register with regis-
ter ‘f’. If ‘d’ is ‘
0’, the result is placed in
the W register. If ‘d’ is ‘
1’, the result is
placed back in register ‘f’.