Datasheet

 2010-2012 Microchip Technology Inc. DS41452C-page 125
PIC16(L)F1516/7/8/9
TABLE 12-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
TABLE 12-11: SUMMARY OF CONFIGURATION WORD WITH PORTE
REGISTER 12-23: WPUE: WEAK PULL-UP PORTE REGISTER
U-0 U-0 U-0 U-0 R/W-1/1 U-0 U-0 U-0
— — — —
WPUE3
— — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-4 Unimplemented: Read as ‘0’
bit 3 WPUE: Weak Pull-up Register bit
1 = Pull-up enabled
0 = Pull-up disabled
bit 2-0 Unimplemented: Read as ‘0’
Note 1: Global WPUEN
bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in configured as an output.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
ADCON0
—
CHS<4:0>
GO/DONE ADON
141
ANSELE
(1)
— — — — — ANSE2 ANSE1 ANSE0 124
CCPxCON
— — DCxB<1:0> CCPxM<3:0> 178
LATE
— — — —
—
LATE2
(1)
LATE1
(1)
LATE0
(1)
124
PORTE
— — — —RE3RE2
(1)
RE1
(1)
RE0
(1)
123
TRISE
— — — —‘1’TRISE2
(1)
TRISE1
(1)
TRISE0
(1)
123
WPUE
— — — — WPUE3 — — — 125
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by
PORTE.
Note 1: These bits are not implemented on the PIC16(L)F1516/8 devices, read as ‘0’.
Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0
Register
on Page
CONFIG1
13:8
FCMEN IESO CLKOUTEN BOREN<1:0>
—
42
7:0
CP MCLRE PWRTE WDTE<1:0> FOSC<2:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTE.