Datasheet

PIC16(L)F1516/7/8/9

DS40001452D-page 178  2010-2013 Microchip Technology Inc.

20.4 Register Definitions: CCPx Control

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

— — DCxB<1:0> CCPxM<3:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4

DCxB<1:0>: PWM Duty Cycle Least Significant bits

Capture mode:

Unused

Compare mode:

Unused

PWM mode:

These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.

bit 3-0

CCPxM<3:0>: CCPx Mode Select bits

0000 = Capture/Compare/PWM off (resets CCPx module)

0001 = Reserved

0010 = Compare mode: toggle output on match

0011 = Reserved

0100 = Capture mode: every falling edge

0101 = Capture mode: every rising edge

0110 = Capture mode: every 4th rising edge

0111 = Capture mode: every 16th rising edge

1000 = Compare mode: set output on compare match (set CCPxIF)

1001 = Compare mode: clear output on compare match (set CCPxIF)

1010 = Compare mode: generate software interrupt only

1011 = Compare mode: the CCPxIF bit is set, CCPx pin is unaffected, CCPx resets TMR1

[Special Event Trigger also starts an ADC conversion if the ADC module is enabled and the

CCP module in Table 20-2 is selected (see Section 20.2.4, Special Event Trigger)]

11xx =PWM mode