PIC16(L)F1516/7/8/9 28/40/44-Pin Flash Microcontrollers with XLP Technology Devices Included In This Data Sheet: • PIC16F1516 • PIC16LF1516 • PIC16F1517 • PIC16LF1517 • PIC16F1518 • PIC16LF1518 • PIC16F1519 • PIC16LF1519 Extreme Low-Power Management PIC16LF1516/7/8/9 with XLP: • • • • Sleep mode: 20 nA @ 1.8V, typical Watchdog Timer: 300 nA @ 1.8V, typical Secondary Oscillator: 600 nA @ 32 kHz Operating Current: 30 A/MHz @ 1.
PIC16(L)F1516/7/8/9 Note: Debug(1) XLP PIC16(L)F1512 (1) 2048 128 25 17 Y 2/1 1 1 PIC16(L)F1513 (1) 4096 256 25 17 Y 2/1 1 1 PIC16(L)F1516 (2) 8192 512 25 17 N 2/1 1 1 PIC16(L)F1517 (2) 8192 512 36 28 N 2/1 1 1 PIC16(L)F1518 (2) 16384 1024 25 17 N 2/1 1 1 PIC16(L)F1519 (2) 16384 1024 36 28 N 2/1 1 1 PIC16(L)F1526 (3) 8192 768 54 30 N 6/3 2 2 PIC16(L)F1527 (3) 16384 1536 54 30 N 6/3 2 2 Note 1: I - Debugging, Integrated on Chip; H - Debugging, available using Debug Header. 2: One pin is input-only.
PIC16(L)F1516/7/8/9 FIGURE 1: 28-PIN SPDIP, SOIC, SSOP PACKAGE DIAGRAM FOR PIC16(L)F1516/1518 28-Pin SPDIP, SOIC, SSOP 1 28 RB7/ICSPDAT RA0 2 27 RB6/ICSPCLK RA1 3 26 RB5 RA2 4 25 RB4 RA3 5 24 RB3 RA4 6 23 RB2 RA5 7 RB1 VSS 8 22 21 RA7 9 20 VDD RA6 10 19 VSS RC0 11 18 RC7 RC1 12 17 RC6 RC2 13 16 RC5 RC3 14 15 RC4 PIC16F1516/1518 PIC16LF1516/1518 VPP/MCLR/RE3 RB0 Note: See Table 1 for location of all peripheral functions.
PIC16(L)F1516/7/8/9 FIGURE 3: 40-PIN PDIP PACKAGE DIAGRAM FOR PIC16(L)F1517/1519 40-Pin PDIP 1 40 RB7/ICSPDAT RA0 2 39 RB6/ICSPCLK RA1 3 38 RB5 RA2 4 37 RB4 RA3 5 36 RB3 RA4 6 35 RB2 RA5 7 34 RB1 RE0 8 33 RB0 RE1 9 32 VDD RE2 10 31 VSS VDD 11 30 RD7 VSS 12 29 RD6 RA7 13 28 RD5 RA6 14 27 RD4 RC0 15 26 RC7 RC1 16 25 RC6 RC2 17 24 RC5 RC3 18 23 RC4 RD0 19 22 RD3 21 RD2 RD1 Note 1: 20 PIC16F1517/1519 PIC16LF1517/1519 VPP/MCLR/RE
PIC16(L)F1516/7/8/9 FIGURE 4: 40-PIN UQFN (5X5) PACKAGE DIAGRAM FOR PIC16(L)F1517/1519 40 39 38 37 36 35 34 33 32 31 RC6 RC5 RC4 RD3 RD2 RD1 RD0 RC3 RC2 RC1 40-Pin UQFN 1 2 3 4 5 6 7 8 9 10 PIC16F1517/1519 PIC16LF1517/1519 30 29 28 27 26 25 24 23 22 21 RC0 RA6 RA7 VSS VDD RE2 RE1 RE0 RA5 RA4 RB3 RB4 RB5 ICSPCLK/RB6 ICSPDAT/RB7 VPP/MCLR/RE3 RA0 RA1 RA2 RA3 11 12 13 14 15 16 17 18 19 20 RC7 RD4 RD5 RD6 RD7 VSS VDD RB0 RB1 RB2 Note 1: 2: See Table 1 for location of all peripheral functions.
PIC16(L)F1516/7/8/9 40-Pin UQFN 44-Pin TQFP ADC Timers CCP EUSART MSSP 27 2 17 19 AN0 — — — SS(2) — — — RA1 3 28 3 18 20 AN1 — — — — — — — Basic 40-Pin PDIP 2 Pull-up 28-Pin UQFN RA0 Interrupt 28-Pin SPDIP, SOIC, SSOP 28/40/44-PIN ALLOCATION TABLE I/O TABLE 1: RA2 4 1 4 19 21 AN2 — — — — — — — RA3 5 2 5 20 22 AN3/VREF+ — — — — — — — RA4 6 3 6 21 23 — T0CKI — — — — — — RA5 7 4 7 22 24 AN4 — — — SS(1) — — VCAP
PIC16(L)F1516/7/8/9 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 Enhanced Mid-range CPU ......................................................................................................................................................... 15 3.0 Memory Organization .........................................................................
PIC16(L)F1516/7/8/9 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.
PIC16(L)F1516/7/8/9 1.0 DEVICE OVERVIEW The PIC16(L)F1516/7/8/9 are described within this data sheet. Figure 1-1 shows a block diagram of the PIC16(L)F1516/7/8/9 devices. Table 1-2 shows the pinout descriptions. Reference Table 1-1 for peripherals available per device.
PIC16(L)F1516/7/8/9 FIGURE 1-1: PIC16(L)F1516/7/8/9 BLOCK DIAGRAM Program Flash Memory RAM OSC2/CLKOUT OSC1/CLKIN PORTA PORTB Timing Generation CPU INTRC Oscillator PORTC (Figure 2-1) PORTD(3) MCLR PORTE(4) Note 1: 2: 3: 4: DS40001452D-page 10 CCP1 Timer0 Temp. Indicator ADC 10-Bit FVR CCP2 MSSP Timer1 Timer2 EUSART See applicable chapters for more information on peripherals. See Table 1-1 for peripherals available on specific devices. PIC16(L)F1517/9 only.
PIC16(L)F1516/7/8/9 TABLE 1-2: PINOUT DESCRIPTION Name RA0/AN0/SS(2) Function Input Type RA0 TTL AN0 AN SS ST RA1/AN1 RA1 TTL AN1 AN RA2/AN2 RA2 TTL AN2 AN RA3/AN3/VREF+ RA3 TTL RA4/T0CKI (1) RA5/AN4/SS /VCAP RA6/OSC2/CLKOUT RA7/OSC1/CLKIN RB0/AN12/INT RB1/AN10 RB2/AN8 RB3/AN9/CCP2(2) RB4/AN11 RB5/AN13/T1G RB6/ICSPCLK RB7/ICSPDAT Output Type Description CMOS General purpose I/O. — ADC Channel 0 input. — Slave Select input. CMOS General purpose I/O.
PIC16(L)F1516/7/8/9 TABLE 1-2: PINOUT DESCRIPTION (CONTINUED) Name RC0/SOSCO/T1CKI RC1/SOSCI/CCP2(1) RC2/AN14/CCP1 RC3/AN15/SCK/SCL RC4/AN16/SDI/SDA RC5/AN17/SDO RC6/AN18/TX/CK RC7/AN19/RX/DT RD0(3)/AN20 RD1(3)/AN21 RD2(3)/AN22 RD3(3)/AN23 RD4(3)/AN24 RD5(3)/AN25 RD6(3)/AN26 Function Input Type RC0 ST Output Type Description CMOS General purpose I/O. SOSCO — XTAL T1CKI ST — RC1 ST SOSCI — Secondary oscillator connection. Timer1 clock input. CMOS General purpose I/O.
PIC16(L)F1516/7/8/9 TABLE 1-2: PINOUT DESCRIPTION (CONTINUED) Name RD7(3)/AN27 Function Input Type RD7 ST Output Type Description CMOS General purpose I/O. AN27 AN RE0(3)/AN5 RE0 ST — ADC Channel 27 input. AN5 AN RE1(3)/AN6 RE1 ST AN6 AN RE2(3)/AN7 RE2 ST AN7 AN — ADC Channel 7 input. RE3/MCLR/VPP RE3 ST — General purpose input with WPU. CMOS General purpose I/O. — ADC Channel 5 input. CMOS General purpose I/O. — ADC Channel 6 input. CMOS General purpose I/O.
PIC16(L)F1516/7/8/9 NOTES: DS40001452D-page 14 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 2.0 ENHANCED MID-RANGE CPU Relative addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory. This family of devices contain an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability.
PIC16(L)F1516/7/8/9 2.1 Automatic Interrupt Context Saving During interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. This saves stack space and user code. See Section 7.5 “Automatic Context Saving”, for more information. 2.2 16-Level Stack with Overflow and Underflow These devices have an external stack memory 15 bits wide and 16 words deep.
PIC16(L)F1516/7/8/9 3.0 MEMORY ORGANIZATION These devices contain the following types of memory: • Program Memory - Configuration Words - Device ID - User ID - Flash Program Memory • Data Memory - Core Registers - Special Function Registers - General Purpose RAM - Common RAM 3.1 Program Memory Organization The enhanced mid-range core has a 15-bit program counter capable of addressing a 32K x 14 program memory space. Table 3-1 shows the memory sizes implemented for these devices.
PIC16(L)F1516/7/8/9 FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR PIC16(L)F1516/7 FIGURE 3-2: PC<14:0> CALL, CALLW RETURN, RETLW Interrupt, RETFIE PROGRAM MEMORY MAP AND STACK FOR PIC16(L)F1518/9 PC<14:0> 15 Stack Level 0 Stack Level 1 CALL, CALLW 15 RETURN, RETLW Interrupt, RETFIE Stack Level 0 Stack Level 1 Stack Level 15 Stack Level 15 Reset Vector 0000h Reset Vector 0000h Interrupt Vector 0004h 0005h Interrupt Vector 0004h 0005h Page 0 Page 0 07FFh 0800h 07FFh 0800h Page 1 On-chip
PIC16(L)F1516/7/8/9 3.1.1 READING PROGRAM MEMORY AS DATA There are two methods of accessing constants in program memory. The first method is to use tables of RETLW instructions. The second method is to set an FSR to point to the program memory. 3.1.1.1 RETLW Instruction The RETLW instruction can be used to provide access to tables of constants. The recommended way to create such a table is shown in Example 3-1.
PIC16(L)F1516/7/8/9 3.2 Data Memory Organization The data memory is partitioned in 32 memory banks with 128 bytes in a bank. Each bank consists of (Figure 3-3): • • • • 12 core registers 20 Special Function Registers (SFR) Up to 80 bytes of General Purpose RAM (GPR) 16 bytes of common RAM The active bank is selected by writing the bank number into the Bank Select Register (BSR). Unimplemented memory will read as ‘0’.
PIC16(L)F1516/7/8/9 3.2.1.1 STATUS Register The STATUS register, shown in Register 3-1, contains: • the arithmetic status of the ALU • the Reset status The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable.
PIC16(L)F1516/7/8/9 3.3.1 SPECIAL FUNCTION REGISTER The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). The registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet. 3.3.
2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7 MEMORY MAP (CONTINUED) BANK 8 400h BANK 9 480h Core Registers (Table 3-2) 40Bh 40Ch Unimplemented Read as ‘0’ 46Fh 470h Common RAM (Accesses 70h – 7Fh) 47Fh Core Registers (Table 3-2) 48Bh 48Ch 4EFh 4F0h 4FFh BANK 16 Unimplemented Read as ‘0’ Common RAM (Accesses 70h – 7Fh) Unimplemented Read as ‘0’ 86Fh 870h 87Fh Common RAM (Accesses 70h – 7Fh) 8EFh 8F0h 8FFh 2010-2013 Microchip Technology Inc.
2010-2013 Microchip Technology Inc.
PIC16(L)F1518/9 MEMORY MAP BANK 0 000h BANK 1 080h Core Registers (Table 3-2) BANK 2 100h Core Registers (Table 3-2) BANK 3 180h Core Registers (Table 3-2) BANK 4 200h Core Registers (Table 3-2) Core Registers (Table 3-2) 00Bh 00Ch 00Dh 00Eh PORTA PORTB PORTC 08Bh 08Ch 08Dh 08Eh TRISA TRISB TRISC 10Bh 10Ch 10Dh 10Eh LATA LATB LATC 18Bh 18Ch 18Dh 18Eh ANSELA ANSELB ANSELC 20Bh 20Ch 20Dh 20Eh 00Fh PORTD(1) 08Fh TRISD(1) 10Fh LATD(1) 18Fh ANSELD(1) 010h 011h 012h 013h 014h 015h 016h
2010-2013 Microchip Technology Inc.
PIC16(L)F1518/9 MEMORY MAP (CONTINUED) BANK 24 C00h BANK 25 C80h Core Registers (Table 3-2) C0Bh C0Ch Core Registers (Table 3-2) C8Bh C8Ch Unimplemented Read as ‘0’ C6Fh C70h C7Fh Common RAM (Accesses 70h – 7Fh) BANK 26 D00h Core Registers (Table 3-2) D0Bh D0Ch Unimplemented Read as ‘0’ CEFh CF0h CFFh Common RAM (Accesses 70h – 7Fh) D7Fh Common RAM (Accesses 70h – 7Fh) Bank 31 Core Registers (Table 3-2) F8Bh F8Ch Unimplemented Read as ‘0’ 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 3.3.5 CORE FUNCTION REGISTERS SUMMARY The Core Function registers listed in Table 3-7 can be addressed from any Bank.
PIC16(L)F1516/7/8/9 3.3.
PIC16(L)F1516/7/8/9 TABLE 3-8: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 2 10Ch LATA PORTA Data Latch xxxx xxxx uuuu uuuu 10Dh LATB PORTB Data Latch xxxx xxxx uuuu uuuu 10Eh LATC PORTC Data Latch xxxx xxxx uuuu uuuu 10Fh LATD(2) PORTD Data Latch 110h LATE(2) — — xxxx xxxx uuuu uuuu — — — LATE2 LATE1 LATE0 111h to — 115h Unimplemented 116h BORCON SBOREN BORFS —
PIC16(L)F1516/7/8/9 TABLE 3-8: Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 Value on POR, BOR Value on all other Resets — — Bank 4 20Ch — Unimplemented 20Dh WPUB WPUB7 WPUB6 1111 1111 1111 1111 20Eh — Unimplemented — — 20Fh — Unimplemented — — 210h WPUE 211h SSPBUF — — — — WPUE3 — — — ---- 1--- ---- 1--- Synchronous Serial Port Receive Buffer/Transmit Register xxxx xx
PIC16(L)F1516/7/8/9 TABLE 3-8: Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets — — Bank 31 F8Ch to — FE3h Unimplemented FE4h STATUS_SHAD FE5h WREG_SHAD FE6h BSR_SHAD FE7h PCLATH_SHAD — — — — — Z DC C Working Register Shadow — — — ---- -xxx ---- -uuu xxxx xxxx uuuu uuuu — Bank Select Register Shadow Program Counter Latch High Register Shadow ---x xxxx ---u uuuu -xxx xxxx uuuu uu
PIC16(L)F1516/7/8/9 3.4 PCL and PCLATH 3.4.2 The Program Counter (PC) is 15 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<14:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 3-4 shows the five situations for the loading of the PC.
PIC16(L)F1516/7/8/9 3.5 Stack 3.5.1 The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack. Both registers are read/writable. TOS is split into TOSH and TOSL due to the 15-bit size of the PC. To access the stack, adjust the value of STKPTR, which will position TOSH:TOSL, then read/write to TOSH:TOSL. STKPTR is five bits to allow detection of overflow and underflow.
PIC16(L)F1516/7/8/9 FIGURE 3-6: ACCESSING THE STACK EXAMPLE 2 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 This figure shows the stack configuration after the first CALL or a single interrupt. If a RETURN instruction is executed, the return address will be placed in the Program Counter and the Stack Pointer decremented to the empty state (0x1F).
PIC16(L)F1516/7/8/9 FIGURE 3-8: ACCESSING THE STACK EXAMPLE 4 TOSH:TOSL 3.5.
PIC16(L)F1516/7/8/9 FIGURE 3-9: INDIRECT ADDRESSING 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x1000 0x1FFF 0x0FFF Reserved 0x2000 Linear Data Memory 0x29AF 0x29B0 FSR Address Range 0x7FFF 0x8000 Reserved 0x0000 Program Flash Memory 0xFFFF Note: 0x7FFF Not all memory regions are completely implemented. Consult device memory tables for memory limits. DS40001452D-page 38 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 3.6.1 TRADITIONAL DATA MEMORY The traditional data memory is a region from FSR address 0x000 to FSR address 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers.
PIC16(L)F1516/7/8/9 3.6.2 3.6.3 LINEAR DATA MEMORY The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the banks. Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the FSR beyond one bank will go directly to the GPR memory of the next bank.
PIC16(L)F1516/7/8/9 4.0 DEVICE CONFIGURATION Device configuration consists of Configuration Words, Code Protection and Device ID. 4.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h. Note: The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers and programmers.
PIC16(L)F1516/7/8/9 4.
PIC16(L)F1516/7/8/9 REGISTER 4-1: bit 2-0 CONFIG1: CONFIGURATION WORD 1 (CONTINUED) FOSC<2:0>: Oscillator Selection bits 111 = ECH: External Clock, High-Power mode (4-20 MHz): device clock supplied to CLKIN pin 110 = ECM: External Clock, Medium-Power mode (0.5-4 MHz): device clock supplied to CLKIN pin 101 = ECL: External Clock, Low-Power mode (0-0.
PIC16(L)F1516/7/8/9 REGISTER 4-2: CONFIG2: CONFIGURATION WORD 2 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 U-1 LVP DEBUG LPBOR BORV STVREN — bit 13 U-1 U-1 — — bit 8 U-1 — R/P-1 (1) VCAPEN U-1 U-1 — — R/P-1 R/P-1 WRT<1:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase bit 13 LVP: Low-Voltage Programming Enable bit 1 = Low-voltage programming enabled 0 = High-v
PIC16(L)F1516/7/8/9 4.3 Code Protection Code protection allows the device to be protected from unauthorized access. Program memory protection is controlled independently. Internal access to the program memory is unaffected by any code protection setting. 4.3.1 PROGRAM MEMORY PROTECTION The entire program memory space is protected from external reads and writes by the CP bit in Configuration Words. When CP = 0, external reads and writes of program memory are inhibited and a read will return all ‘0’s.
PIC16(L)F1516/7/8/9 4.6 Device ID and Revision ID The memory location 8006h is where the Device ID and Revision ID are stored. The upper nine bits hold the Device ID. The lower five bits hold the Revision ID. See Section 11.4 “User ID, Device ID and Configuration Word Access” for more information on accessing these memory locations. Development tools, such as device programmers and debuggers, may be used to read the Device ID and Revision ID. 4.
PIC16(L)F1516/7/8/9 5.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR) 5.1 Overview The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 5-1 illustrates a block diagram of the oscillator module. Clock sources can be supplied from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits.
PIC16(L)F1516/7/8/9 SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM FIGURE 5-1: Low-Power Mode Event Switch (SCS<1:0>) Primary Oscillator OSC2 Primary Oscillator (OSC) 2 OSC1 Primary Clock 00 SOSCO/ T1CKI SOSCI Secondary Oscillator (SOSC) Secondary Clock INTOSC 01 1x Clock Switch MUX Secondary Oscillator Internal Oscillator IRCF<3:0> 4 Start-Up Osc LF-INTOSC (31.
PIC16(L)F1516/7/8/9 5.2 Clock Source Types Clock sources can be classified as external or internal. External clock sources rely on external circuitry for the clock source to function. Examples are: oscillator modules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC) mode circuits. Internal clock sources are contained within the oscillator module.
PIC16(L)F1516/7/8/9 FIGURE 5-3: QUARTZ CRYSTAL OPERATION (LP, XT OR HS MODE) FIGURE 5-4: CERAMIC RESONATOR OPERATION (XT OR HS MODE) PIC® MCU PIC® MCU OSC1/CLKIN C1 To Internal Logic Quartz Crystal C2 OSC1/CLKIN RS(1) RF(2) Sleep OSC2/CLKOUT Note 1: A series resistor (RS) may be required for quartz crystals with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M.
PIC16(L)F1516/7/8/9 5.2.1.4 5.2.1.5 Secondary Oscillator External RC Mode The secondary oscillator is a separate crystal oscillator that is associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the SOSCO and SOSCI device pins. The external Resistor-Capacitor (RC) modes support the use of an external RC circuit.
PIC16(L)F1516/7/8/9 5.2.2 INTERNAL CLOCK SOURCES The device may be configured to use the internal oscillator block as the system clock by performing one of the following actions: • Program the FOSC<2:0> bits in Configuration Words to select the INTOSC clock source, which will be used as the default system clock upon a device Reset. • Write the SCS<1:0> bits in the OSCCON register to switch the system clock source to the internal oscillator during run-time. See Section 5.
PIC16(L)F1516/7/8/9 5.2.2.3 Internal Oscillator Frequency Selection The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register. The outputs of the 16 MHz HFINTOSC postscaler and the LFINTOSC connects to a multiplexer (see Figure 5-1). The Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register select the frequency output of the internal oscillators.
PIC16(L)F1516/7/8/9 FIGURE 5-7: HFINTOSC INTERNAL OSCILLATOR SWITCH TIMING LFINTOSC (FSCM and WDT disabled) HFINTOSC Start-up Time 2-cycle Sync Running LFINTOSC 0 IRCF <3:0> 0 System Clock HFINTOSC LFINTOSC (Either FSCM or WDT enabled) HFINTOSC 2-cycle Sync Running LFINTOSC 0 IRCF <3:0> 0 System Clock LFINTOSC HFINTOSC LFINTOSC turns off unless WDT or FSCM is enabled LFINTOSC Start-up Time 2-cycle Sync Running HFINTOSC IRCF <3:0> =0 0 System Clock DS40001452D-page 54
PIC16(L)F1516/7/8/9 5.3 Clock Switching 5.3.3 SECONDARY OSCILLATOR The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bits of the OSCCON register. The following clock sources can be selected using the SCS bits: The secondary oscillator is a separate crystal oscillator associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.
PIC16(L)F1516/7/8/9 5.4 Two-Speed Clock Start-up Mode Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device.
PIC16(L)F1516/7/8/9 5.4.2 1. 2. 3. 4. 5. 6. 7. TWO-SPEED START-UP SEQUENCE 5.4.3 Wake-up from Power-on Reset or Sleep. Instructions begin execution by the internal oscillator at the frequency set in the IRCF<3:0> bits of the OSCCON register. OST enabled to count 1024 clock cycles. OST timed out, wait for falling edge of the internal oscillator. OSTS is set. System clock held low until the next falling edge of new clock (LP, XT or HS mode). System clock is switched to external clock source.
PIC16(L)F1516/7/8/9 5.5 Fail-Safe Clock Monitor 5.5.3 The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the Configuration Words. The FSCM is applicable to all external Oscillator modes (LP, XT, HS, EC, RC and secondary oscillator).
PIC16(L)F1516/7/8/9 FIGURE 5-10: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure System Clock Output Clock Monitor Output (Q) Failure Detected OSCFIF Test Note: Test Test The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 5.
PIC16(L)F1516/7/8/9 REGISTER 5-2: OSCSTAT: OSCILLATOR STATUS REGISTER R-1/q U-0 R-q/q R-0/q U-0 U-0 R-0/q R-0/q SOSCR — OSTS HFIOFR — — LFIOFR HFIOFS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Conditional bit 7 SOSCR: Secondary Oscillator Ready bit If T1OSCEN = 1: 1 = Secondary oscillator is ready 0
PIC16(L)F1516/7/8/9 NOTES: DS40001452D-page 62 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 6.0 RESETS A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 6-1. There are multiple ways to reset this device: • • • • • • • • • Power-On Reset (POR) Brown-Out Reset (BOR) Low-Power Brown-Out Reset (LPBOR) MCLR Reset WDT Reset RESET instruction Stack Overflow Stack Underflow Programming mode exit To allow VDD to stabilize, an optional power-up timer can be enabled to extend the Reset time after a BOR or POR event.
PIC16(L)F1516/7/8/9 6.1 Power-On Reset (POR) 6.2 Brown-Out Reset (BOR) The POR circuit holds the device in Reset until VDD has reached an acceptable level for minimum operation. Slow rising VDD, fast operating speeds or analog performance may require greater than minimum VDD. The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met. The BOR circuit holds the device in Reset when VDD reaches a selectable minimum level.
PIC16(L)F1516/7/8/9 FIGURE 6-2: BROWN-OUT SITUATIONS VDD VBOR Internal Reset TPWRT(1) VDD VBOR Internal Reset < TPWRT TPWRT(1) VDD VBOR Internal Reset Note 1: 6.3 TPWRT(1) TPWRT delay only if PWRTE bit is programmed to ‘0’.
PIC16(L)F1516/7/8/9 6.4 Low Power Brown-Out Reset (LPBOR) The Low-Power Brown-Out Reset (LPBOR) is an essential part of the Reset subsystem. Refer to Figure 6-1 to see how the BOR interacts with other modules. The LPBOR is used to monitor the external VDD pin. When too low of a voltage is detected, the device is held in Reset. When this occurs, a register bit (BOR) is changed to indicate that a BOR Reset has occurred. The same bit is set for both the BOR and the LPBOR. Refer to Register 6-2. 6.4.
PIC16(L)F1516/7/8/9 FIGURE 6-3: RESET START-UP SEQUENCE VDD Internal POR TPWRT Power-Up Timer MCLR TMCLR Internal RESET Oscillator Modes External Crystal TOST Oscillator Start-Up Timer Oscillator FOSC Internal Oscillator Oscillator FOSC External Clock (EC) CLKIN FOSC 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 6.12 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON register are updated to indicate the cause of the Reset. Table 6-3 and Table 6-4 show the Reset conditions of these registers.
PIC16(L)F1516/7/8/9 6.13 Power Control (PCON) Register The Power Control (PCON) register contains flag bits to differentiate between a: • • • • • • • Power-on Reset (POR) Brown-out Reset (BOR) Reset Instruction Reset (RI) MCLR Reset (RMCLR) Watchdog Timer Reset (RWDT) Stack Underflow Reset (STKUNF) Stack Overflow Reset (STKOVF) The PCON register bits are shown in Register 6-2. 6.
PIC16(L)F1516/7/8/9 TABLE 6-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BORCON SBOREN BORFS — — — — — BORRDY 65 PCON STKOVF STKUNF — RWDT RMCLR RI POR BOR 69 STATUS — — — TO PD Z DC C 21 WDTCON — — SWDTEN 89 WDTPS<4:0> Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Resets.
PIC16(L)F1516/7/8/9 7.0 INTERRUPTS The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode. This chapter contains the following information for Interrupts: • • • • • Operation Interrupt Latency Interrupts During Sleep INT Pin Automatic Context Saving Many peripherals produce interrupts. Refer to the corresponding chapters for details.
PIC16(L)F1516/7/8/9 7.1 Operation Interrupts are disabled upon any device Reset. They are enabled by setting the following bits: • GIE bit of the INTCON register • Interrupt Enable bit(s) for the specific interrupt event(s) • PEIE bit of the INTCON register (if the Interrupt Enable bit of the interrupt event is contained in the PIEx register) 7.2 Interrupt Latency Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins.
PIC16(L)F1516/7/8/9 FIGURE 7-2: INTERRUPT LATENCY OSC1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKOUT Interrupt Sampled during Q1 Interrupt GIE PC Execute PC-1 PC 1 Cycle Instruction at PC PC+1 0004h 0005h NOP NOP Inst(0004h) PC+1/FSR ADDR New PC/ PC+1 0004h 0005h Inst(PC) NOP NOP Inst(0004h) FSR ADDR PC+1 PC+2 0004h 0005h INST(PC) NOP NOP NOP Inst(0004h) Inst(0005h) FSR ADDR PC+1 0004h 0005h INST(PC) NOP NOP I
PIC16(L)F1516/7/8/9 FIGURE 7-3: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT (3) (4) INT pin (1) (1) INTF Interrupt Latency (2) (5) GIE INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: PC Inst (PC) Inst (PC – 1) PC + 1 Inst (PC + 1) Inst (PC) PC + 1 — Dummy Cycle 0004h 0005h Inst (0004h) Inst (0005h) Dummy Cycle Inst (0004h) INTF flag is sampled here (every Q1).
PIC16(L)F1516/7/8/9 7.3 Interrupts During Sleep Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction.
PIC16(L)F1516/7/8/9 7.
PIC16(L)F1516/7/8/9 REGISTER 7-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit 1 = Enables the Timer
PIC16(L)F1516/7/8/9 REGISTER 7-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0/0 U-0 U-0 U-0 R/W-0/0 U-0 U-0 R/W-0/0 OSFIE — — — BCLIE — — CCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSFIE: Oscillator Fail Interrupt Enable bit 1 = Enables the Oscillator Fail interrupt 0 = Disables the O
PIC16(L)F1516/7/8/9 REGISTER 7-4: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit 1 = Interrupt is pending 0
PIC16(L)F1516/7/8/9 REGISTER 7-5: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2 R/W-0/0 U-0 U-0 U-0 R/W-0/0 U-0 U-0 R/W-0/0 OSFIF — — — BCLIF — — CCP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSFIF: Oscillator Fail Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 6-
PIC16(L)F1516/7/8/9 8.0 POWER-DOWN MODE (SLEEP) 8.1 Wake-up from Sleep The Power-down mode is entered by executing a SLEEP instruction. The device can wake-up from Sleep through one of the following events: Upon entering Sleep mode, the following conditions exist: 1. 2. 3. 4. 5. 6. 1. 2. 3. 4. 5. 6. 7. 8. 9. WDT will be cleared but keeps running, if enabled for operation during Sleep. PD bit of the STATUS register is cleared. TO bit of the STATUS register is set. CPU clock is disabled.
PIC16(L)F1516/7/8/9 8.1.
PIC16(L)F1516/7/8/9 8.2 Low-Power Sleep Mode The PIC16F1516/7/8/9 device contains an internal Low Dropout (LDO) voltage regulator, which allows the device I/O pins to operate at voltages up to 5.5V while the internal device logic operates at a lower voltage. The LDO and its associated reference circuitry must remain active when the device is in Sleep mode. The PIC16F1516/7/8/9 allows the user to optimize the operating current in Sleep, depending on the application requirements.
PIC16(L)F1516/7/8/9 8.
PIC16(L)F1516/7/8/9 9.0 LOW DROPOUT (LDO) VOLTAGE REGULATOR The PIC16F1516/7/8/9 has an internal Low Dropout Regulator (LDO) which provides operation above 3.6V. The LDO regulates a voltage for the internal device logic while permitting the VDD and I/O pins to operate at a higher voltage. There is no user enable/disable control available for the LDO, it is always active. The PIC16LF1516/7/8/9 operates at a maximum VDD of 3.6V and does not incorporate an LDO.
PIC16(L)F1516/7/8/9 NOTES: DS40001452D-page 86 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 10.0 WATCHDOG TIMER (WDT) The Watchdog Timer is a system timer that generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The Watchdog Timer is typically used to recover the system from unexpected events.
PIC16(L)F1516/7/8/9 10.1 Independent Clock Source 10.3 The WDT derives its time base from the 31 kHz LFINTOSC internal oscillator. Time intervals in this chapter are based on a nominal interval of 1 ms. See Section 25.0 “Electrical Specifications” for the LFINTOSC tolerances. 10.2 The Watchdog Timer module has four operating modes controlled by the WDTE<1:0> bits in Configuration Words. See Table 10-1. 10.2.
PIC16(L)F1516/7/8/9 10.
PIC16(L)F1516/7/8/9 TABLE 10-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER Bit 7 Bit 6 OSCCON — STATUS — — WDTCON — — Legend: CONFIG1 Legend: Bit 4 Bit 3 IRCF<3:0> — Bit 2 Bit 1 — TO PD Bit 0 SCS<1:0> Z DC WDTPS<4:0> Register on Page 60 C 21 SWDTEN 89 x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Watchdog Timer.
PIC16(L)F1516/7/8/9 11.0 FLASH PROGRAM MEMORY CONTROL The Flash program memory is readable and writable during normal operation over the full VDD range. Program memory is indirectly addressed using Special Function Registers (SFRs).
PIC16(L)F1516/7/8/9 TABLE 11-1: FLASH MEMORY ORGANIZATION BY DEVICE Device Row Erase (words) Write Latches (words) 32 32 PIC16(L)F1516 PIC16(L)F1517 PIC16(L)F1518 PIC16(L)F1519 11.2.1 READING THE FLASH PROGRAM MEMORY To read a program memory location, the user must: 1. 2. 3. Write the desired address to the PMADRH:PMADRL register pair. Clear the CFGS bit of the PMCON1 register. Then, set control bit RD of the PMCON1 register.
PIC16(L)F1516/7/8/9 FIGURE 11-2: FLASH PROGRAM MEMORY READ CYCLE EXECUTION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC Flash ADDR Flash Data PC + 1 INSTR (PC) INSTR(PC - 1) executed here PMADRH,PMADRL INSTR (PC + 1) BSF PMCON1,RD executed here PC +3 PC+3 PMDATH,PMDATL INSTR(PC + 1) instruction ignored Forced NOP executed here PC + 5 PC + 4 INSTR (PC + 3) INSTR(PC + 2) instruction ignored Forced NOP executed here INSTR (PC + 4) INSTR(PC + 3) executed here I
PIC16(L)F1516/7/8/9 11.2.2 FLASH MEMORY UNLOCK SEQUENCE The unlock sequence is a mechanism that protects the Flash program memory from unintended self-write programming or erasing.
PIC16(L)F1516/7/8/9 11.2.3 ERASING FLASH PROGRAM MEMORY While executing code, program memory can only be erased by rows. To erase a row: 1. 2. 3. 4. 5. Load the PMADRH:PMADRL register pair with any address within the row to be erased. Clear the CFGS bit of the PMCON1 register. Set the FREE and WREN bits of the PMCON1 register. Write 55h, then AAh, to PMCON2 (Flash programming unlock sequence). Set control bit WR of the PMCON1 register to begin the erase operation. See Example 11-2.
PIC16(L)F1516/7/8/9 EXAMPLE 11-2: ERASING ONE ROW OF PROGRAM MEMORY Required Sequence ; This row erase routine assumes the following: ; 1. A valid address within the erase row is loaded in ADDRH:ADDRL ; 2.
PIC16(L)F1516/7/8/9 11.2.4 WRITING TO FLASH PROGRAM MEMORY Program memory is programmed using the following steps: 1. 2. 3. 4. Load the address in PMADRH:PMADRL of the row to be programmed. Load each write latch with data. Initiate a programming operation. Repeat steps 1 through 3 until all data is written. The following steps should be completed to load the write latches and program a row of program memory. These steps are divided into two parts.
7 BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES 6 0 7 5 4 PMADRH - r9 r8 r7 r6 r5 7 0 PMADRL r4 r3 r2 r1 r0 c4 c3 c2 c1 c0 5 - 0 7 PMDATH 6 0 PMDATL 8 14 10 Program Memory Write Latches 5 14 Write Latch #0 00h PMADRL<4:0> 14 CFGS = 0 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 FIGURE 11-6: FLASH PROGRAM MEMORY WRITE FLOWCHART Start Write Operation Determine number of words to be written into Program or Configuration Memory. The number of words cannot exceed the number of words per row. (word_cnt) Disable Interrupts (GIE = 0) Select Program or Config.
PIC16(L)F1516/7/8/9 EXAMPLE 11-3: ; ; ; ; ; ; ; WRITING TO FLASH PROGRAM MEMORY This write routine assumes the following: 1. 64 bytes of data are loaded, starting at the address in DATA_ADDR 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR, stored in little endian format 3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL 4.
PIC16(L)F1516/7/8/9 11.3 Modifying Flash Program Memory When modifying existing data in a program memory row, and data within that row must be preserved, it must first be read and saved in a RAM image. Program memory is modified using the following steps: 1. 2. 3. 4. 5. 6. 7. Load the starting address of the row to be modified. Read the existing data from the row into a RAM image. Modify the RAM image to contain the new data to be written into program memory.
PIC16(L)F1516/7/8/9 11.4 User ID, Device ID and Configuration Word Access Instead of accessing program memory, the User ID’s, Device ID/Revision ID and Configuration Words can be accessed when CFGS = 1 in the PMCON1 register. This is the region that would be pointed to by PC<15> = 1, but not all addresses are accessible. Different access may exist for reads and writes. Refer to Table 11-2.
PIC16(L)F1516/7/8/9 11.5 Write Verify It is considered good programming practice to verify that program memory writes agree with the intended value. Since program memory is stored as a full page then the stored program memory contents are compared with the intended data stored in RAM after the last write is complete. FIGURE 11-8: FLASH PROGRAM MEMORY VERIFY FLOWCHART Start Verify Operation This routine assumes that the last row of data written was from an image saved in RAM.
PIC16(L)F1516/7/8/9 11.
PIC16(L)F1516/7/8/9 REGISTER 11-5: PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER U-1 R/W-0/0 R/W-0/0 R/W/HC-0/0 R/W/HC-x/q(2) R/W-0/0 R/S/HC-0/0 R/S/HC-0/0 —(1) CFGS LWLO FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 Unimplemented: Read as ‘1’ bi
PIC16(L)F1516/7/8/9 REGISTER 11-6: W-0/0 PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 Program Memory Control Register 2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Flash Memory Unlock Pattern bits To unlock writes, a 55h must be written first, followed by an AAh, be
PIC16(L)F1516/7/8/9 12.0 I/O PORTS FIGURE 12-1: GENERIC I/O PORT OPERATION Each port has three standard registers for its operation. These registers are: • TRISx registers (data direction) • PORTx registers (reads the levels on the pins of the device) • LATx registers (output latch) Read LATx D Some ports may have one or more of the following additional registers.
PIC16(L)F1516/7/8/9 12.1 Alternate Pin Function The Alternate Pin Function Control (APFCON) registers are used to steer specific peripheral input and output functions between different pins. The APFCON registers are shown in Register 12-1. For this device family, the following functions can be moved between different pins. • SS (Slave Select) • CCP2 These bits have no effect on the values of any TRIS register. PORT and TRIS overrides will be routed to the correct pin.
PIC16(L)F1516/7/8/9 12.2 12.2.1 PORTA Registers DATA REGISTER PORTA is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 12-3). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). Example 12-1 shows how to initialize an I/O port.
PIC16(L)F1516/7/8/9 REGISTER 12-2: PORTA: PORTA REGISTER R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared RA<7:0>: PORTA I/O Value bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL bit 7-0 Note 1: Writes to PORTA
PIC16(L)F1516/7/8/9 REGISTER 12-4: LATA: PORTA DATA LATCH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared LATA<7:0>: PORTA Output Latch Value bits(1) bit 7-4 Note 1: Writes to PORTA are act
PIC16(L)F1516/7/8/9 TABLE 12-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Register on Page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ANSELA — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 111 APFCON — — — — — — SSSEL CCP2SEL 108 LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 WPUEN INTEDG TMR0CS TMR0SE PSA PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 110 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 110 LATA OPTION_REG Legend: CONFIG1
PIC16(L)F1516/7/8/9 12.3 12.3.1 PORTB Registers DATA REGISTER PORTB is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISB (Register 12-7). Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin).
PIC16(L)F1516/7/8/9 REGISTER 12-6: PORTB: PORTB REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared RB<7:0>: PORTB General Purpose I/O Pin bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL bit 7-0 Note 1: W
PIC16(L)F1516/7/8/9 REGISTER 12-9: ANSELB: PORTB ANALOG SELECT REGISTER U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 ANSB<5:0>: Analog Select between Analog or Digit
PIC16(L)F1516/7/8/9 12.4 12.4.1 PORTC Registers DATA REGISTER PORTC is a 8-bit wide bidirectional port. The corresponding data direction register is TRISC (Register 12-12). Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin).
PIC16(L)F1516/7/8/9 REGISTER 12-11: PORTC: PORTC REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared RC<7:0>: PORTC General Purpose I/O Pin bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL bit 7-0 Note 1: Wr
PIC16(L)F1516/7/8/9 REGISTER 12-14: ANSELC: PORTC ANALOG SELECT REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 U-0 U-0 ANSC7 ANSC6 ANSC3 ANSC3 ANSC3 ANSC2 — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 ANSC<7:2>: Analog Select between Analog or Digital Function on pins RC<7:2>, respective
PIC16(L)F1516/7/8/9 12.5 12.5.1 PORTD Registers (PIC16F1517/1519 only) DATA REGISTER 12.5.4 PORTD FUNCTIONS AND OUTPUT PRIORITIES PORTD has no peripheral outputs, so the PORTD output has no priority function. PORTD is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISD (Register 12-16). Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a High-Impedance mode).
PIC16(L)F1516/7/8/9 REGISTER 12-15: PORTD: PORTD REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared RD<7:0>: PORTD General Purpose I/O Pin bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL bit 7-0 Note 1: Wr
PIC16(L)F1516/7/8/9 REGISTER 12-18: ANSELD: PORTD ANALOG SELECT REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: ANSD<7:0>: Analog Select between Analog or Digital Function o
PIC16(L)F1516/7/8/9 12.6 12.6.1 PORTE Registers 12.6.3 DATA REGISTER PORTE is a 4-bit wide, bidirectional port. The corresponding data direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin).
PIC16(L)F1516/7/8/9 REGISTER 12-19: PORTE: PORTE REGISTER U-0 U-0 — U-0 — — U-0 R-x/u R/W-x/u R/W-x/u R/W-x/u — RE3 RE2(1) RE1(1) RE0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 RE<3:0>: PORTE I/O Pin bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL Note 1
PIC16(L)F1516/7/8/9 REGISTER 12-21: LATE: PORTE DATA LATCH REGISTER(2) U-0 U-0 U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u — — — — — LATE2 LATE1 LATE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 LATE<2:0>: PORTE Output Latch Value bits(1) Note 1: 2: Writes to PORTE are
PIC16(L)F1516/7/8/9 REGISTER 12-23: WPUE: WEAK PULL-UP PORTE REGISTER U-0 U-0 U-0 U-0 R/W-1/1 U-0 U-0 U-0 — — — — WPUE3 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 WPUE: Weak Pull-up Register bit 1 = Pull-up enabled 0 = Pull-up disabled bit 2-0 Unimplemente
PIC16(L)F1516/7/8/9 NOTES: DS40001452D-page 126 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 13.0 INTERRUPT-ON-CHANGE The PORTB pins can be configured to operate as Interrupt-On-Change (IOC) pins. An interrupt can be generated by detecting a signal that has either a rising edge or a falling edge. Any individual PORTB pin, or combination of PORTB pins, can be configured to generate an interrupt.
PIC16(L)F1516/7/8/9 FIGURE 13-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM IOCBNx D Q4Q1 Q CK Edge Detect R RBx IOCBPx D Data Bus = 0 or 1 Q write IOCBFx CK D S Q To Data Bus IOCBFx CK IOCIE R Q2 From all other IOCBFx individual Pin Detectors Q1 Q2 Q3 Q4 Q4Q1 DS40001452D-page 128 Q1 Q1 Q2 Q2 Q3 Q4 Q4Q1 IOC Interrupt to CPU core Q3 Q4 Q4 Q4Q1 Q4Q1 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 13.
PIC16(L)F1516/7/8/9 TABLE 13-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELB ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 115 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 76 Name IOCBF IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 129 IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 129 IOCBP IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 I
PIC16(L)F1516/7/8/9 14.0 FIXED VOLTAGE REFERENCE (FVR) 14.1 Independent Gain Amplifiers The output of the FVR supplied to the ADC module is routed through a programmable gain amplifier. The amplifier can be configured to amplify the reference voltage by 1x, 2x or 4x, to produce the three possible voltage levels. The Fixed Voltage Reference, or FVR, is a stable voltage reference, independent of VDD, with 1.024V, 2.048V or 4.096V selectable output levels.
PIC16(L)F1516/7/8/9 14.
PIC16(L)F1516/7/8/9 15.0 TEMPERATURE INDICATOR MODULE FIGURE 15-1: This family of devices is equipped with a temperature circuit designed to measure the operating temperature of the silicon die. The circuit’s range of operating temperature falls between -40°C and +85°C. The output is a voltage that is proportional to the device temperature. The output of the temperature indicator is internally connected to the device ADC.
PIC16(L)F1516/7/8/9 TABLE 15-2: Name FVRCON Legend: SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 FVREN FVRRDY TSEN TSRNG — — Bit 1 Bit 0 ADFVR<1:0> Register on page 132 Shaded cells are unused by the temperature indicator module. DS40001452D-page 134 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 16.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter.
PIC16(L)F1516/7/8/9 16.1 ADC Configuration When configuring and using the ADC the following functions must be considered: • • • • • • Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Result formatting 16.1.1 PORT CONFIGURATION The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits. Refer to Section 12.
PIC16(L)F1516/7/8/9 TABLE 16-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES ADC Clock Period (TAD) Device Frequency (FOSC) ADC Clock Source ADCS<2:0> 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz Fosc/2 000 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s 100 200 ns (2) (2) (2) 1.0 s 4.0 s 400 ns (2) 1.0 s 2.0 s 8.0 s(3) Fosc/4 250 ns (2) 0.5 s 500 ns Fosc/8 001 Fosc/16 101 800 ns 1.0 s 2.0 s 4.0 s 16.0 s(3) Fosc/32 010 1.6 s 2.0 s 4.0 s 8.
PIC16(L)F1516/7/8/9 16.1.5 INTERRUPTS 16.1.6 The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. RESULT FORMATTING The 10-bit ADC conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON1 register controls the output format.
PIC16(L)F1516/7/8/9 16.2 16.2.1 ADC Operation STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a ‘1’. Setting the GO/ DONE bit of the ADCON0 register to a ‘1’ will start the Analog-to-Digital conversion. Note: 16.2.2 The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 16.2.6 “ADC Conversion Procedure”.
PIC16(L)F1516/7/8/9 16.2.6 ADC CONVERSION PROCEDURE This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. 2. 3. 4. 5. 6. 7. 8.
PIC16(L)F1516/7/8/9 16.
PIC16(L)F1516/7/8/9 REGISTER 16-2: R/W-0/0 ADCON1: ADC CONTROL REGISTER 1 R/W-0/0 ADFM R/W-0/0 R/W-0/0 ADCS<2:0> U-0 U-0 — — R/W-0/0 R/W-0/0 ADPREF<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: ADC Result Format Select bit 1 = Right justified.
PIC16(L)F1516/7/8/9 REGISTER 16-3: R/W-x/u ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ADRES<9:2>: ADC Result Register bits Upper eight bits of 10-bit conversion result REGISTER 16-4: R/W
PIC16(L)F1516/7/8/9 REGISTER 16-5: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — — — — — R/W-x/u R/W-x/u ADRES<9:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Reserved: Do not use.
PIC16(L)F1516/7/8/9 16.4 ADC Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 16-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), refer to Figure 16-4.
PIC16(L)F1516/7/8/9 Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification. FIGURE 16-4: ANALOG INPUT MODEL VDD Analog Input pin Rs VT 0.6V CPIN 5 pF VA RIC 1k Sampling Switch SS Rss I LEAKAGE(1) VT 0.
PIC16(L)F1516/7/8/9 TABLE 16-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH ADC Bit 7 ADCON0 — ADCON1 ADFM Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 — — CHS<4:0> ADCS<2:0> ADRESH ADC Result Register High ADRESL ADC Result Register Low Bit 1 Bit 0 GO/DONE ADON ADPREF<1:0> Register on Page 141 142 143, 144 143, 144 ANSELA — — ANSA5 — ANSA3 ANSA2 ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 118 ANSELD(1) ANSD7 ANSD6 ANSD5 ANSD4 ANSD3
PIC16(L)F1516/7/8/9 NOTES: DS40001452D-page 148 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 17.0 TIMER0 MODULE 17.1.2 8-BIT COUNTER MODE The Timer0 module is an 8-bit timer/counter with the following features: In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin. • • • • • • 8-Bit Counter mode, using the T0CKI pin, is selected by setting the TMR0CS bit in the OPTION_REG register to ‘1’.
PIC16(L)F1516/7/8/9 17.1.3 SOFTWARE PROGRAMMABLE PRESCALER A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION_REG register. Note: The Watchdog Timer (WDT) uses its own independent prescaler. There are eight prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION_REG register.
PIC16(L)F1516/7/8/9 17.
PIC16(L)F1516/7/8/9 NOTES: DS40001452D-page 152 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 18.0 TIMER1 MODULE WITH GATE CONTROL • • • • The Timer1 module is a 16-bit timer/counter with the following features: Figure 18-1 is a block diagram of the Timer1 module.
PIC16(L)F1516/7/8/9 18.1 Timer1 Operation 18.2 The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. The TMR1CS<1:0> and T1OSCEN bits of the T1CON register are used to select the clock source for Timer1. Table 18-2 displays the clock source selections. 18.2.1 When used with an internal clock source, the module is a timer and increments on every instruction cycle.
PIC16(L)F1516/7/8/9 18.3 Timer1 Prescaler Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L. 18.4 Secondary Oscillator Timer1 uses the low-power secondary oscillator circuit on pins SOSCI and SOSCO. The secondary oscillator is designed to use an external 32.
PIC16(L)F1516/7/8/9 18.6.2.1 T1G Pin Gate Operation The T1G pin is one source for Timer1 gate control. It can be used to supply an external source to the Timer1 gate circuitry. 18.6.2.2 Timer0 Overflow Gate Operation When Timer0 increments from FFh to 00h, a low-to-high pulse will automatically be generated and internally supplied to the Timer1 gate circuitry. 18.6.2.
PIC16(L)F1516/7/8/9 18.7 Timer1 Interrupt The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: • • • • TMR1ON bit of the T1CON register TMR1IE bit of the PIE1 register PEIE bit of the INTCON register GIE bit of the INTCON register The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine.
PIC16(L)F1516/7/8/9 FIGURE 18-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL Timer1 N FIGURE 18-4: N+1 N+2 N+3 N+4 TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM T1G_IN T1CKI T1GVAL Timer1 N DS40001452D-page 158 N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 FIGURE 18-5: TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 TMR1GIF N Cleared by software 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 FIGURE 18-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 TMR1GIF DS40001452D-page 160 N Cleared by software N+1 N+2 N+3 N+4 Set by hardware on falling edge of T1GVAL Cleared by software 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 18.
PIC16(L)F1516/7/8/9 REGISTER 18-2: T1GCON: TIMER1 GATE CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ DONE T1GVAL R/W-0/u R/W-0/u T1GSS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 TMR1GE: Timer1 Gate Enable bi
PIC16(L)F1516/7/8/9 TABLE 18-5: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 115 CCP1CON — — Name CCP2CON DC1B<1:0> CCP1M<3:0> — — GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 76 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 77 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 79 INTCON DC2B<1:0> 178 CCP2M<3:0> TMR1H Holdi
PIC16(L)F1516/7/8/9 NOTES: DS40001452D-page 164 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 19.0 TIMER2 MODULE The Timer2 module incorporates the following features: • 8-bit Timer and Period registers (TMR2 and PR2, respectively) • Readable and writable (both registers) • Software programmable prescaler (1:1, 1:4, 1:16, and 1:64) • Software programmable postscaler (1:1 to 1:16) • Interrupt on TMR2 match with PR2, respectively • Optional use as the shift clock for the MSSP modules See Figure 19-1 for a block diagram of Timer2.
PIC16(L)F1516/7/8/9 19.1 Timer2 Operation The clock input to the Timer2 modules is the system instruction clock (FOSC/4). TMR2 increments from 00h on each clock edge. A 4-bit counter/prescaler on the clock input allows direct input, divide-by-4 and divide-by-16 prescale options. These options are selected by the prescaler control bits, T2CKPS<1:0> of the T2CON register. The value of TMR2 is compared to that of the Period register, PR2, on each clock cycle.
PIC16(L)F1516/7/8/9 19.
PIC16(L)F1516/7/8/9 TABLE 19-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2 Bit 7 Bit 6 CCP1CON — — DC1B<1:0> CCP1M<3:0> 178 CCP2CON — — DC2B<1:0> CCP2M<3:0> 178 INTCON Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page Name GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 76 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 77 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 79 PR2 Timer2 Module Period Register T2CON TMR2 — T2OUTPS<3:0> 165
PIC16(L)F1516/7/8/9 20.0 CAPTURE/COMPARE/PWM MODULES The Capture/Compare/PWM module is a peripheral which allows the user to time and control different events, and to generate Pulse-Width Modulation (PWM) signals. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate Pulse-Width Modulated signals of varying frequency and duty cycle.
PIC16(L)F1516/7/8/9 20.1 Capture Mode 20.1.2 The Capture mode function described in this section is available and identical for CCP modules CCP1 and CCP2. Capture mode makes use of the 16-bit Timer1 resource. When an event occurs on the CCPx pin, the 16-bit CCPRxH:CCPRxL register pair captures and stores the 16-bit value of the TMR1H:TMR1L register pair, respectively.
PIC16(L)F1516/7/8/9 20.1.5 CAPTURE DURING SLEEP Capture mode depends upon the Timer1 module for proper operation. There are two options for driving the Timer1 module in Capture mode. It can be driven by the instruction clock (FOSC/4), or by an external clock source. When Timer1 is clocked by FOSC/4, Timer1 will not increment during Sleep. When the device wakes from Sleep, Timer1 will continue from its previous state.
PIC16(L)F1516/7/8/9 20.2 Compare Mode 20.2.2 The Compare mode function described in this section is available and identical for CCP modules CCP1 and CCP2. Compare mode makes use of the 16-bit Timer1 resource. The 16-bit value of the CCPRxH:CCPRxL register pair is constantly compared against the 16-bit value of the TMR1H:TMR1L register pair. When a match occurs, one of the following events can occur: • • • • • In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode.
PIC16(L)F1516/7/8/9 20.2.5 COMPARE DURING SLEEP The Compare mode is dependent upon the system clock (FOSC) for proper operation. Since FOSC is shut down during Sleep mode, the Compare mode will not function properly during Sleep. 20.2.6 ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register APFCON. To determine which pins can be moved and what their default locations are upon a Reset, see Section 12.
PIC16(L)F1516/7/8/9 20.3 PWM Overview Pulse-Width Modulation (PWM) is a scheme that provides power to a load by switching quickly between fully on and fully off states. The PWM signal resembles a square wave where the high portion of the signal is considered the on state and the low portion of the signal is considered the off state. The high portion, also known as the pulse width, can vary in time and is defined in steps.
PIC16(L)F1516/7/8/9 20.3.2 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for standard PWM operation: 1. 2. 3. 4. 5. 6. Disable the CCPx pin output driver by setting the associated TRIS bit. Load the PR2 register with the PWM period value. Configure the CCP module for the PWM mode by loading the CCPxCON register with the appropriate values. Load the CCPRxL register and the DCxBx bits of the CCPxCON register, with the PWM duty cycle value.
PIC16(L)F1516/7/8/9 20.3.6 PWM RESOLUTION EQUATION 20-4: The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is 10 bits when PR2 is 255. The resolution is a function of the PR2 register value as shown by Equation 20-4.
PIC16(L)F1516/7/8/9 20.3.7 OPERATION IN SLEEP MODE 20.3.10 In Sleep mode, the TMR2 register will not increment and the state of the module will not change. If the CCPx pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state. 20.3.8 CHANGES IN SYSTEM CLOCK FREQUENCY ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register APFCON.
PIC16(L)F1516/7/8/9 20.
PIC16(L)F1516/7/8/9 21.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE 21.1 Master SSP (MSSP) Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc.
PIC16(L)F1516/7/8/9 The I2C interface supports the following modes and features: • • • • • • • • • • • • • Master mode Slave mode Byte NACKing (Slave mode) Limited Multi-master support 7-bit and 10-bit addressing Start and Stop interrupts Interrupt masking Clock stretching Bus collision detection General call address matching Address masking Address Hold and Data Hold modes Selectable SDA hold times Figure 21-2 is a block diagram of the I2C interface module in Master mode.
PIC16(L)F1516/7/8/9 FIGURE 21-3: MSSP BLOCK DIAGRAM (I2C™ SLAVE MODE) Internal Data Bus Read Write SSPBUF Reg SCL Shift Clock SSPSR Reg SDA MSb LSb SSPMSK Reg Match Detect Addr Match SSPADD Reg Start and Stop bit Detect 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 21.2 SPI Mode Overview The Serial Peripheral Interface (SPI) bus is a synchronous serial data communication bus that operates in Full-Duplex mode. Devices communicate in a master/slave environment where the master device initiates the communication. A slave device is controlled through a Chip Select known as Slave Select.
PIC16(L)F1516/7/8/9 FIGURE 21-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION SPI Master SCK SCK SDO SDI SDI SDO General I/O General I/O SS General I/O SCK SDI SDO SPI Slave #1 SPI Slave #2 SS SCK SDI SDO SPI Slave #3 SS 21.2.1 SPI MODE REGISTERS The MSSP module has five registers for SPI mode operation.
PIC16(L)F1516/7/8/9 The MSSP consists of a transmit/receive shift register (SSPSR) and a buffer register (SSPBUF). The SSPSR shifts the data in and out of the device, MSb first. The SSPBUF holds the data that was written to the SSPSR until the received data is ready. Once the eight bits of data have been received, that byte is moved to the SSPBUF register. Then, the Buffer Full Detect bit, BF of the SSPSTAT register, and the interrupt flag bit, SSPIF, are set.
PIC16(L)F1516/7/8/9 21.2.3 SPI MASTER MODE The master can initiate the data transfer at any time because it controls the SCK line. The master determines when the slave (Processor 2, Figure 21-5) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input).
PIC16(L)F1516/7/8/9 21.2.4 SPI SLAVE MODE In Slave mode, the data is transmitted and received as external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCK pin. The Idle state is determined by the CKP bit of the SSPCON1 register.
PIC16(L)F1516/7/8/9 FIGURE 21-7: SPI DAISY-CHAIN CONNECTION SPI Master SCK SCK SDO SDI SDI SPI Slave #1 SDO General I/O SS SCK SDI SPI Slave #2 SDO SS SCK SDI SPI Slave #3 SDO SS FIGURE 21-8: SLAVE SELECT SYNCHRONOUS WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF Shift register SSPSR and bit count are reset SSPBUF to SSPSR SDO bit 7 bit 6 bit 7 SDI bit 6 bit 0 bit 0 bit 7 bit 7 Input Sample SSPIF Interrupt Flag SSPSR to SSPBUF 2010-2013 Microchip Tech
PIC16(L)F1516/7/8/9 FIGURE 21-9: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 0 bit 7 Input Sample SSPIF Interrupt Flag SSPSR to SSPBUF Write Collision detection active FIGURE 21-10: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit
PIC16(L)F1516/7/8/9 21.2.6 SPI OPERATION IN SLEEP MODE In SPI Master mode, module clocks may be operating at a different speed than when in Full-Power mode; in the case of the Sleep mode, all clocks are halted. Special care must be taken by the user when the MSSP clock is much faster than the system clock. In Slave mode, when MSSP interrupts are enabled, after the master completes sending data, an MSSP interrupt will wake the controller from Sleep.
PIC16(L)F1516/7/8/9 21.3 I2C MODE OVERVIEW The Inter-Integrated Circuit Bus (I2C) is a multi-master serial data communication bus. Devices communicate in a master/slave environment where the master devices initiate the communication. A Slave device is controlled through addressing. VDD SCL The I2C bus specifies two signal connections: • Serial Clock (SCL) • Serial Data (SDA) Figure 21-1 shows the block diagram of the MSSP module when operating in I2C mode.
PIC16(L)F1516/7/8/9 When one device is transmitting a logical one, or letting the line float, and a second device is transmitting a logical zero, or holding the line low, the first device can detect that the line is not a logical one. This detection, when used on the SCL line, is called clock stretching. Clock stretching gives slave devices a mechanism to control the flow of data. When this detection is used on the SDA line, it is called arbitration.
PIC16(L)F1516/7/8/9 21.4 I2C MODE OPERATION All MSSP I2C communication is byte oriented and shifted out MSb first. Six SFR registers and two interrupt flags interface the module with the PIC® microcontroller and user software. Two pins, SDA and SCL, are exercised by the module to communicate with other external I2C devices. 21.4.1 BYTE FORMAT All communication in I2C is done in 9-bit segments. A byte is sent from a master to a slave or vice-versa, followed by an Acknowledge bit sent back.
PIC16(L)F1516/7/8/9 21.4.5 START CONDITION 21.4.7 2 The I C specification defines a Start condition as a transition of SDA from a high to a low state while SCL line is high. A Start condition is always generated by the master and signifies the transition of the bus from an Idle to an Active state. Figure 21-12 shows wave forms for Start and Stop conditions. A Restart is valid any time that a Stop would be valid.
PIC16(L)F1516/7/8/9 21.4.9 ACKNOWLEDGE SEQUENCE The 9th SCL pulse for any transferred byte in I2C is dedicated as an Acknowledge. It allows receiving devices to respond back to the transmitter by pulling the SDA line low. The transmitter must release control of the line during this time to shift in the response. The Acknowledge (ACK) is an active-low signal, pulling the SDA line low indicated to the transmitter that the device has received the transmitted data and is ready to receive more.
PIC16(L)F1516/7/8/9 21.5.2 SLAVE RECEPTION When the R/W bit of a matching received address byte is clear, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register and acknowledged. When the overflow condition exists for a received address, then not Acknowledge is given. An overflow condition is defined as either bit BF of the SSPSTAT register is set, or bit SSPOV of the SSPCON1 register is set. The BOEN bit of the SSPCON3 register modifies this operation.
DS40001452D-page 196 SSPOV BF SSPIF S 1 A7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 9 ACK 1 D7 2 D6 4 D4 5 D3 6 D2 7 D1 SSPBUF is read Cleared by software 3 D5 Receiving Data 8 9 2 D6 First byte of data is available in SSPBUF 1 D0 ACK D7 4 D4 5 D3 6 D2 7 D1 SSPOV set because SSPBUF is still full. ACK is not sent.
2010-2013 Microchip Technology Inc. CKP SSPOV BF SSPIF 1 SCL S A7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 9 R/W=0 ACK SEN 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 CKP is written to ‘1’ in software, releasing SCL SSPBUF is read Cleared by software Clock is held low until CKP is set to ‘1’ 1 D7 Receive Data 9 ACK SEN 3 D5 4 D4 5 D3 First byte of data is available in SSPBUF 6 D2 7 D1 SSPOV set because SSPBUF is still full. ACK is not sent.
DS40001452D-page 198 P S ACKTIM CKP ACKDT BF SSPIF S Receiving Address 1 3 5 6 7 8 ACK the received byte Slave software clears ACKDT to Address is read from SSBUF If AHEN = 1: SSPIF is set 4 ACKTIM set by hardware on 8th falling edge of SCL When AHEN=1: CKP is cleared by hardware and SCL is stretched 2 A7 A6 A5 A4 A3 A2 A1 Receiving Data 9 2 3 4 5 6 7 ACKTIM cleared by hardware in 9th rising edge of SCL When DHEN=1: CKP is cleared by hardware on 8th falling edge of SCL SSPI
2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 21.5.3 SLAVE TRANSMISSION 21.5.3.2 7-bit Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register, and an ACK pulse is sent by the slave on the 9th bit. A master device can transmit a read request to a slave, and then clock data out of the slave.
2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 21.5.3.3 7-bit Transmission with Address Hold Enabled Setting the AHEN bit of the SSPCON3 register enables additional clock stretching and interrupt generation after the 8th falling edge of a received matching address. Once a matching address has been clocked in, CKP is cleared and the SSPIF interrupt is set. Figure 21-19 displays a standard waveform of a 7-bit Address Slave Transmission with AHEN enabled. 1. 2. Bus starts Idle.
2010-2013 Microchip Technology Inc. D/A R/W ACKTIM CKP ACKSTAT ACKDT BF SSPIF S Receiving Address 2 4 5 6 7 8 Slave clears ACKDT to ACK address ACKTIM is set on 8th falling edge of SCL 9 ACK When R/W = 1; CKP is always cleared after ACK R/W = 1 Received address is read from SSPBUF 3 When AHEN = 1; CKP is cleared by hardware after receiving matching address.
PIC16(L)F1516/7/8/9 21.5.4 SLAVE MODE 10-BIT ADDRESS RECEPTION This section describes a standard sequence of events for the MSSP module configured as an I2C slave in 10-bit Addressing mode. Figure 21-20 is used as a visual reference for this description. This is a step by step process of what must be done by slave software to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. Bus starts Idle. Master sends Start condition; S bit of SSPSTAT is set; SSPIF is set if interrupt on Start detect is enabled.
2010-2013 Microchip Technology Inc.
DS40001452D-page 206 ACKTIM CKP UA ACKDT BF 2 1 5 0 6 A9 7 A8 Set by hardware on 9th falling edge 4 1 ACKTIM is set by hardware on 8th falling edge of SCL If when AHEN = 1; on the 8th falling edge of SCL of an address byte, CKP is cleared Slave software clears ACKDT to ACK the received byte 3 1 8 R/W = 0 9 ACK UA 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 Update to SSPADD is not allowed until 9th falling edge of SCL SSPBUF can be read anytime before the next received byte Cleared
2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 21.5.6 CLOCK STRETCHING 21.5.6.2 Clock stretching occurs when a device on the bus holds the SCL line low effectively pausing communication. The slave may stretch the clock to allow more time to handle data or prepare a response for the master device. A master device is not concerned with stretching as anytime it is active on the bus and not transferring data it is stretching.
PIC16(L)F1516/7/8/9 21.5.8 GENERAL CALL ADDRESS SUPPORT the R/W bit clear, an interrupt is generated and slave software can read SSPBUF and respond. Figure 21-24 shows a General Call reception sequence. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master device. The exception is the general call address which can address all devices.
PIC16(L)F1516/7/8/9 21.6 I2C MASTER MODE Master mode is enabled by setting and clearing the appropriate SSPM bits in the SSPCON1 register and by setting the SSPEN bit. In Master mode, the SDA and SCK pins must be configured as inputs. The MSSP peripheral hardware will override the output driver TRIS controls when necessary to drive the pins low. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions.
PIC16(L)F1516/7/8/9 21.6.2 CLOCK ARBITRATION Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, releases the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<7:0> and begins counting.
PIC16(L)F1516/7/8/9 21.6.4 I2C MASTER MODE START CONDITION TIMING To initiate a Start condition (Figure 21-26), the user sets the Start Enable bit, SEN bit of the SSPCON2 register. If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<7:0> and starts its count. If SCL and SDA are both sampled high when the Baud Rate Generator times out (TBRG), the SDA pin is driven low.
PIC16(L)F1516/7/8/9 21.6.5 I2C MASTER MODE REPEATED START CONDITION TIMING A Repeated Start condition (Figure 21-27) occurs when the RSEN bit of the SSPCON2 register is programmed high and the master state machine is no longer active. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded and begins counting. The SDA pin is released (brought high) for one Baud Rate Generator count (TBRG).
PIC16(L)F1516/7/8/9 21.6.6 I2C MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPBUF register. This action will set the Buffer Full flag bit, BF and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted.
2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 21.6.7 I2C MASTER MODE RECEPTION Master mode reception (Figure 21-29) is enabled by programming the Receive Enable bit, RCEN bit of the SSPCON2 register. Note: The MSSP module must be in an Idle state before the RCEN bit is set or the RCEN bit will be disregarded. The Baud Rate Generator begins counting and on each rollover, the state of the SCL pin changes (high-to-low/low-to-high) and data is shifted into the SSPSR.
2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 21.6.8 ACKNOWLEDGE SEQUENCE TIMING 21.6.9 A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN bit of the SSPCON2 register. At the end of a receive/transmit, the SCL line is held low after the falling edge of the 9th clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and counts down to ‘0’.
PIC16(L)F1516/7/8/9 21.6.10 SLEEP OPERATION 21.6.13 2 While in Sleep mode, the I C slave module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 21.6.11 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. 21.6.
PIC16(L)F1516/7/8/9 21.6.13.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDA or SCL are sampled low at the beginning of the Start condition (Figure 21-33). SCL is sampled low before SDA is asserted low (Figure 21-34). During a Start condition, both the SDA and the SCL pins are monitored. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 21-35).
PIC16(L)F1516/7/8/9 FIGURE 21-34: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF.
PIC16(L)F1516/7/8/9 21.6.13.2 Bus Collision During a Repeated Start Condition If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, Figure 21-36. If SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time.
PIC16(L)F1516/7/8/9 21.6.13.3 Bus Collision During a Stop Condition The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPADD and counts down to 0. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 21-38).
PIC16(L)F1516/7/8/9 TABLE 21-3: SUMMARY OF REGISTERS ASSOCIATED WITH I2C™ OPERATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 76 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 77 PIE2 OSFIE — — — BCLIE — — CCP2IE 78 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 79 PIR2 OSFIF — — — BCLIF — — CCP2IF 80 Name INTCON SSPADD ADD<7:0> SSPBUF Synchronous Serial Por
PIC16(L)F1516/7/8/9 21.7 BAUD RATE GENERATOR The MSSP module has a Baud Rate Generator available for clock generation in both I2C and SPI Master modes. The Baud Rate Generator (BRG) reload value is placed in the SSPADD register (Register 21-6). When a write occurs to SSPBUF, the Baud Rate Generator will automatically begin counting down. Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state. clock line.
PIC16(L)F1516/7/8/9 21.
PIC16(L)F1516/7/8/9 REGISTER 21-2: SSPCON1: SSP CONTROL REGISTER 1 R/C/HS-0/0 R/C/HS-0/0 R/W-0/0 R/W-0/0 WCOL SSPOV SSPEN CKP R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SSPM<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared bit 7 WCOL: Write Collision Detect bit Master mode
PIC16(L)F1516/7/8/9 REGISTER 21-3: SSPCON2: SSP CONTROL REGISTER 2 R/W-0/0 R-0/0 R/W-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/W/HS-0/0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware S = User set bit 7 GCEN: General Call Enable bi
PIC16(L)F1516/7/8/9 REGISTER 21-4: SSPCON3: SSP CONTROL REGISTER 3 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only)(3) 1 = Indicates the I2C bus i
PIC16(L)F1516/7/8/9 REGISTER 21-5: R/W-1/1 SSPMSK: SSP MASK REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 MSK<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 MSK<7:1>: Mask bits 1 = The received address bit n is compared to SSPADD to detect I2C address match 0 = The received address
PIC16(L)F1516/7/8/9 22.
PIC16(L)F1516/7/8/9 FIGURE 22-2: EUSART RECEIVE BLOCK DIAGRAM SPEN CREN RX/DT pin Baud Rate Generator Data Recovery FOSC BRG16 +1 SPBRGH SPBRGL RSR Register MSb Pin Buffer and Control Multiplier x4 x16 x64 SYNC 1 X 0 0 0 BRGH X 1 1 0 0 BRG16 X 1 0 1 0 Stop RCIDL OERR (8) ••• 7 1 LSb 0 Start RX9 ÷n n FERR RX9D RCREG Register 8 FIFO Data Bus RCIF RCIE Interrupt The operation of the EUSART module is controlled through three registers: • Transmit Status and Control (TXSTA)
PIC16(L)F1516/7/8/9 22.1 EUSART Asynchronous Mode The EUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a VOH mark state which represents a ‘1’ data bit, and a VOL space state which represents a ‘0’ data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission.
PIC16(L)F1516/7/8/9 22.1.1.5 TSR Status 22.1.1.7 The TRMT bit of the TXSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied to this bit, so the user has to poll this bit to determine the TSR status. Note: 22.1.1.6 1. 2. 3.
PIC16(L)F1516/7/8/9 TABLE 22-1: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 243 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 76 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 77 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 79 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 242 Name BAUDCON INTCON RCSTA SPBRGL BRG<7:0>
PIC16(L)F1516/7/8/9 22.1.2 EUSART ASYNCHRONOUS RECEIVER The Asynchronous mode is typically used in RS-232 systems. The receiver block diagram is shown in Figure 22-2. The data is received on the RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate.
PIC16(L)F1516/7/8/9 22.1.2.4 Receive Framing Error Each character in the receive FIFO buffer has a corresponding framing error Status bit. A framing error indicates that a Stop bit was not seen at the expected time. The framing error status is accessed via the FERR bit of the RCSTA register. The FERR bit represents the status of the top unread character in the receive FIFO. Therefore, the FERR bit must be read before reading the RCREG.
PIC16(L)F1516/7/8/9 22.1.2.8 Asynchronous Reception Setup: 22.1.2.9 1. Initialize the SPBRGH, SPBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 22.4 “EUSART Baud Rate Generator (BRG)”). 2. Clear the ANSEL bit for the RX pin (if applicable). 3. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. 4.
PIC16(L)F1516/7/8/9 TABLE 22-2: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 243 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 76 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 77 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF Name BAUDCON INTCON RCREG RCSTA EUSART Receive Data Register SPEN RX9 SREN SPBRGL CREN ADDEN FER
PIC16(L)F1516/7/8/9 22.2 Clock Accuracy with Asynchronous Operation The factory calibrates the internal oscillator block output (INTOSC). However, the INTOSC frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. The Auto-Baud Detect feature (see Section 22.4.1, Auto-Baud Detect) can be used to compensate for changes in the INTOSC frequency.
PIC16(L)F1516/7/8/9 22.
PIC16(L)F1516/7/8/9 REGISTER 22-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/C
PIC16(L)F1516/7/8/9 REGISTER 22-3: BAUDCON: BAUD RATE CONTROL REGISTER R-0/0 R-1/1 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Au
PIC16(L)F1516/7/8/9 22.4 EUSART Baud Rate Generator (BRG) The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit of the BAUDCON register selects 16-bit mode. The SPBRGH, SPBRGL register pair determines the period of the free running baud rate timer.
PIC16(L)F1516/7/8/9 TABLE 22-3: BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula 0 8-bit/Asynchronous FOSC/[64 (n+1)] 0 1 8-bit/Asynchronous 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous 1 1 x 16-bit/Synchronous SYNC BRG16 BRGH 0 0 0 FOSC/[16 (n+1)] FOSC/[4 (n+1)] Legend: x = Don’t care, n = value of SPBRGH, SPBRGL register pair.
PIC16(L)F1516/7/8/9 TABLE 22-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 1200 — 1221 — 1.73 — 255 — 1200 — 0.00 — 239 — 1202 — 0.16 — 207 — 1200 — 0.00 — 143 2400 2404 0.16 129 2400 0.00 119 2404 0.16 103 2400 0.00 71 9600 9470 -1.36 32 9600 0.00 29 9615 0.16 25 9600 0.00 17 10417 10417 0.00 29 10286 -1.
PIC16(L)F1516/7/8/9 TABLE 22-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 8.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 4.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 3.6864 MHz Actual Rate FOSC = 1.000 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 300 1200 — — — — — — — 1202 — 0.16 — 207 — 1200 — 0.00 — 191 300 1202 0.16 0.16 207 51 2400 2404 0.16 207 2404 0.
PIC16(L)F1516/7/8/9 TABLE 22-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 1200 300.0 1200 0.00 -0.01 16665 4166 300.0 1200 0.00 0.00 15359 3839 300.0 1200.1 0.00 0.01 13332 3332 300.0 1200 0.00 0.00 9215 2303 2400 2400 0.02 2082 2400 0.00 1919 2399.5 -0.02 1666 2400 0.
PIC16(L)F1516/7/8/9 22.4.1 AUTO-BAUD DETECT The EUSART module supports automatic detection and calibration of the baud rate. In the Auto-Baud Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RX signal, the RX signal is timing the BRG. The Baud Rate Generator is used to time the period of a received 55h (ASCII “U”) which is the Sync character for the LIN bus. The unique feature of this character is that it has five rising edges including the Stop bit edge.
PIC16(L)F1516/7/8/9 22.4.2 AUTO-BAUD OVERFLOW During the course of automatic baud detection, the ABDOVF bit of the BAUDCON register will be set if the baud rate counter overflows before the fifth rising edge is detected on the RX pin. The ABDOVF bit indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the SPBRGH:SPBRGL register pair. After the ABDOVF bit has been set, the counter continues to count until the fifth rising edge is detected on the RX pin.
PIC16(L)F1516/7/8/9 FIGURE 22-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Auto Cleared Bit set by user WUE bit RX/DT Line RCIF Note 1: Cleared due to User Read of RCREG The EUSART remains in Idle while the WUE bit is set.
PIC16(L)F1516/7/8/9 22.4.4 BREAK CHARACTER SEQUENCE The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. A Break character consists of a Start bit, followed by 12 ‘0’ bits and a Stop bit. To send a Break character, set the SENDB and TXEN bits of the TXSTA register. The Break character transmission is then initiated by a write to the TXREG. The value of data written to TXREG will be ignored and all ‘0’s will be transmitted.
PIC16(L)F1516/7/8/9 22.5 EUSART Synchronous Mode Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line.
PIC16(L)F1516/7/8/9 FIGURE 22-10: SYNCHRONOUS TRANSMISSION RX/DT pin bit 0 bit 1 Word 1 bit 2 bit 7 bit 0 bit 1 Word 2 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit TXEN bit ‘1’ Note: ‘1’ Sync Master mode, SPBRGL = 0, continuous transmission of two 8-bit words.
PIC16(L)F1516/7/8/9 22.5.1.5 Synchronous Master Reception Data is received at the RX/DT pin. The RX/DT pin output driver is automatically disabled when the EUSART is configured for synchronous master receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCSTA register) or the Continuous Receive Enable bit (CREN of the RCSTA register).
PIC16(L)F1516/7/8/9 FIGURE 22-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RCREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
PIC16(L)F1516/7/8/9 22.5.2 SYNCHRONOUS SLAVE MODE The following bits are used to configure the EUSART for Synchronous slave operation: • • • • • SYNC = 1 CSRC = 0 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 1. 2. 3. 4. Setting the SYNC bit of the TXSTA register configures the device for synchronous operation. Clearing the CSRC bit of the TXSTA register configures the device as a slave.
PIC16(L)F1516/7/8/9 22.5.2.3 EUSART Synchronous Slave Reception 22.5.2.4 The operation of the Synchronous Master and Slave modes is identical (Section 22.5.1.5 “Synchronous Master Reception”), with the following exceptions: • Sleep • CREN bit is always set, therefore the receiver is never idle • SREN bit, which is a “don’t care” in Slave mode 1. 2. 3. A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep.
PIC16(L)F1516/7/8/9 22.6 EUSART Operation During Sleep The EUSART will remain active during Sleep only in the Synchronous Slave mode. All other modes require the system clock and therefore cannot generate the necessary signals to run the Transmit or Receive Shift registers during Sleep. Synchronous Slave mode uses an externally generated clock to run the Transmit and Receive Shift registers. 22.6.
PIC16(L)F1516/7/8/9 NOTES: DS40001452D-page 260 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 23.0 IN-CIRCUIT SERIAL PROGRAMMING™ (ICSP™) ICSP™ programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can be done after the assembly process, allowing the device to be programmed with the most recent firmware or a custom firmware. Five pins are needed for ICSP™ programming: • ICSPCLK • ICSPDAT • MCLR/VPP • VDD • VSS In Program/Verify mode the program memory, user IDs and the Configuration Words are programmed through serial communications.
PIC16(L)F1516/7/8/9 FIGURE 23-2: PICkit™ PROGRAMMER STYLE CONNECTOR INTERFACE Pin 1 Indicator Pin Description* 1 = VPP/MCLR 1 2 3 4 5 6 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT 5 = ICSPCLK 6 = No Connect * FIGURE 23-3: The 6-pin header (0.100" spacing) accepts 0.025" square pins.
PIC16(L)F1516/7/8/9 24.0 INSTRUCTION SET SUMMARY 24.1 Read-Modify-Write Operations • Byte Oriented • Bit Oriented • Literal and Control Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction, or the destination designator ‘d’. A read operation is performed on a register even if the instruction writes to that register.
PIC16(L)F1516/7/8/9 FIGURE 24-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 OPCODE d f (FILE #) 0 d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 OPCODE b (BIT #) f (FILE #) 0 b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE 8 7 0 k (literal) k = 8-bit immediate value CALL and GOTO instructions only 13 11 10 OPCODE 0 k (lit
PIC16(L)F1516/7/8/9 TABLE 24-3: INSTRUCTION SET Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ADDWFC ANDWF ASRF LSLF LSRF CLRF CLRW COMF DECF INCF IORWF MOVF MOVWF RLF RRF SUBWF SUBWFB SWAPF XORWF f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d f, d Add W and f Add with Carry W and f AND W with f Arithmetic Right Shift Logical Left Shift Logical Right Shift Clear f Clear W Compl
PIC16(L)F1516/7/8/9 TABLE 24-3: INSTRUCTION SET (CONTINUED) Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes CONTROL OPERATIONS BRA BRW CALL CALLW GOTO RETFIE RETLW RETURN k – k – k k k – CLRWDT NOP OPTION RESET SLEEP TRIS – – – – – f Relative Branch Relative Branch with W Call Subroutine Call Subroutine with W Go to address Return from interrupt Return with literal in W Return from Subroutine 2 2 2 2 2 2 2 2 INHERENT OPERATIONS 11 00 10 00 10 00 11 00 001k
PIC16(L)F1516/7/8/9 24.2 Instruction Descriptions ADDFSR Add Literal to FSRn ANDLW AND literal with W Syntax: [ label ] ADDFSR FSRn, k Syntax: [ label ] ANDLW Operands: -32 k 31 n [ 0, 1] Operands: 0 k 255 Operation: (W) .AND. (k) (W) Operation: FSR(n) + k FSR(n) Status Affected: Z Status Affected: None Description: Description: The signed 6-bit literal ‘k’ is added to the contents of the FSRnH:FSRnL register pair.
PIC16(L)F1516/7/8/9 BCF Bit Clear f Syntax: [ label ] BCF BTFSC f,b Bit Test f, Skip if Clear Syntax: [ label ] BTFSC f,b 0 f 127 0b7 Operands: 0 f 127 0b7 Operands: Operation: 0 (f) Operation: skip if (f) = 0 Status Affected: None Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared. Description: If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed.
PIC16(L)F1516/7/8/9 CALL Call Subroutine CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0 k 2047 Operands: None Operation: (PC)+ 1 TOS, k PC<10:0>, (PCLATH<6:3>) PC<14:11> Operation: Status Affected: None 00h WDT 0 WDT prescaler, 1 TO 1 PD Description: Call Subroutine. First, return address (PC + 1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>.
PIC16(L)F1516/7/8/9 DECFSZ Decrement f, Skip if 0 INCFSZ Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f) - 1 (destination); skip if result = 0 Operation: (f) + 1 (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in the W register.
PIC16(L)F1516/7/8/9 LSLF Logical Left Shift MOVF Syntax: [ label ] LSLF Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f<7>) C (f<6:0>) dest<7:1> 0 dest<0> Operation: (f) (dest) f {,d} Status Affected: C, Z Description: The contents of register ‘f’ are shifted one bit to the left through the Carry flag. A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’.
PIC16(L)F1516/7/8/9 MOVIW Move INDFn to W MOVLP Syntax: [ label ] MOVIW ++FSRn [ label ] MOVIW --FSRn [ label ] MOVIW FSRn++ [ label ] MOVIW FSRn-[ label ] MOVIW k[FSRn] Syntax: [ label ] MOVLP k Operands: 0 k 127 Operation: k PCLATH Status Affected: None Operands: n [0,1] mm [00,01, 10, 11] -32 k 31 Description: The seven-bit literal ‘k’ is loaded into the PCLATH register.
PIC16(L)F1516/7/8/9 MOVWI Move W to INDFn NOP No Operation Syntax: [ label ] MOVWI ++FSRn [ label ] MOVWI --FSRn [ label ] MOVWI FSRn++ [ label ] MOVWI FSRn-[ label ] MOVWI k[FSRn] Syntax: [ label ] Operands: None Operation: No operation Status Affected: None n [0,1] mm [00,01, 10, 11] -32 k 31 Description: No operation.
PIC16(L)F1516/7/8/9 RETFIE Return from Interrupt RETURN Return from Subroutine Syntax: [ label ] Syntax: [ label ] None RETFIE RETURN Operands: None Operands: Operation: TOS PC, 1 GIE Operation: TOS PC Status Affected: None Status Affected: None Description: Description: Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a 2-cycle instruction.
PIC16(L)F1516/7/8/9 SUBLW Subtract W from literal Syntax: [ label ] RRF Rotate Right f through Carry Syntax: [ label ] Operands: 0 f 127 d [0,1] Operation: See description below Status Affected: C, DC, Z Status Affected: C Description: Description: The contents of register ‘f’ are rotated one bit to the right through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’.
PIC16(L)F1516/7/8/9 SWAPF Swap Nibbles in f XORLW Exclusive OR literal with W Syntax: [ label ] Syntax: [ label ] Operands: 0 f 127 d [0,1] Operation: SWAPF f,d (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) XORLW k Operands: 0 k 255 Operation: (W) .XOR. k W) Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register.
PIC16(L)F1516/7/8/9 25.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings(†) Ambient temperature under bias....................................................................................................... -40°C to +125°C Storage temperature ........................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS, PIC16F1516/7/8/9 ....................................................................
PIC16(L)F1516/7/8/9 PIC16F1516/7/8/9 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C FIGURE 25-1: VDD (V) 5.5 2.5 2.3 0 4 10 16 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 25-1 for each Oscillator mode’s supported frequencies. PIC16LF1516/7/8/9 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C VDD (V) FIGURE 25-2: 3.6 2.5 1.
PIC16(L)F1516/7/8/9 FIGURE 25-3: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE 125 -15% to +12.5% Temperature (°C) 85 60 ± 8% ± 6.5% 25 0 -20 -40 1.8 -15% to +12.5% 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 25.1 DC Characteristics: Supply Voltage PIC16LF1516/7/8/9 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F1516/7/8/9 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param. No. D001 Sym. VDD Characteristic VDR Typ† Max. Units Conditions 1.8 2.5 — — 3.6 3.
PIC16(L)F1516/7/8/9 FIGURE 25-4: POR AND POR REARM WITH SLOW RISING VDD VDD VPOR VPORR VSS NPOR POR REARM VSS TVLOW(2) Note 1: 2: 3: TPOR(3) When NPOR is low, the device is held in Reset. TPOR 1 s typical. TVLOW 2.7 s typical. 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 25.2 DC Characteristics: Supply Current (IDD) PIC16LF1516/7/8/9 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F1516/7/8/9 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Min. Conditions Typ† Max. Units — 8.0 14 A 1.8 — 12.0 31 A 3.
PIC16(L)F1516/7/8/9 25.2 DC Characteristics: Supply Current (IDD) (Continued) PIC16LF1516/7/8/9 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F1516/7/8/9 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Min. Conditions Typ† Max. Units — 1.0 1.5 mA 3.0 — 1.
PIC16(L)F1516/7/8/9 25.2 DC Characteristics: Supply Current (IDD) (Continued) PIC16LF1516/7/8/9 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F1516/7/8/9 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Min. Conditions Typ† Max. Units — 1.0 1.80 mA 3.0 — 1.
PIC16(L)F1516/7/8/9 25.3 DC Characteristics: Power-Down Currents (IPD) PIC16LF1516/7/8/9 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F1516/7/8/9 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Power-down Currents Min. Conditions Typ† Max. +85°C Max.
PIC16(L)F1516/7/8/9 25.3 DC Characteristics: Power-Down Currents (IPD) (Continued) PIC16LF1516/7/8/9 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F1516/7/8/9 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No.
PIC16(L)F1516/7/8/9 25.4 DC Characteristics: I/O Ports DC CHARACTERISTICS Param No. Sym.
PIC16(L)F1516/7/8/9 25.4 DC Characteristics: I/O Ports (Continued) DC CHARACTERISTICS Param No. D101* Sym. Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Min. Capacitive Loading Specs on Output Pins COSC2 OSC2 pin — Typ† Max.
PIC16(L)F1516/7/8/9 25.5 Memory Programming Requirements Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C DC CHARACTERISTICS Param No. Sym. Characteristic Min. Typ† Max. Units Conditions Program Memory Programming Specifications D110 VIHH Voltage on MCLR/VPP pin 8.0 — 9.0 V D111 IDDP Supply Current during Programming — — 10 mA D112 VBE VDD for Bulk Erase 2.
PIC16(L)F1516/7/8/9 25.6 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. TH01 TH02 Sym. Characteristic Typ. Units JA Thermal Resistance Junction to Ambient 69.7 60.0 71.0 27.5 47.2 41.0 49.8 18.9 C/W JC Thermal Resistance Junction to Case C/W C/W C/W C/W C/W C/W C/W 29.0 C/W 24.0 C/W 24.0 C/W 24.7 C/W 5.5 C/W 26.
PIC16(L)F1516/7/8/9 25.7 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2.
PIC16(L)F1516/7/8/9 25.8 AC Characteristics: FIGURE 25-6: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1/CLKIN OS02 OS04 OS04 OS03 OSC2/CLKOUT (LP,XT,HS Modes) OSC2/CLKOUT (CLKOUT Mode) TABLE 25-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. OS01 Sym. FOSC Characteristic Min. Typ† Max. Units Conditions External CLKIN Frequency(1) DC — 0.
PIC16(L)F1516/7/8/9 TABLE 25-2: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. Sym. Characteristic Freq. Tolerance Min. Typ† Max. Units Conditions OS08 HFOSC Internal Calibrated HFINTOSC Frequency(1) 6.5% — 16.0 — MHz VDD = 3.
PIC16(L)F1516/7/8/9 TABLE 25-3: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. OS11 OS12 Sym. TosH2ckL Characteristic Min. Typ† Max. Units Conditions — — 70 ns VDD = 3.3-5.0V — — 72 ns VDD = 3.3-5.
PIC16(L)F1516/7/8/9 FIGURE 25-9: BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD VBOR and VHYST VBOR (Device in Brown-out Reset) (Device not in Brown-out Reset) 37 Reset (due to BOR) 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 TABLE 25-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. Sym. Characteristic Min. Typ† Max.
PIC16(L)F1516/7/8/9 TABLE 25-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. Sym.
PIC16(L)F1516/7/8/9 FIGURE 25-11: CAPTURE/COMPARE/PWM TIMINGS (CCP) CCP (Capture mode) CC01 CC02 CC03 Note: Refer to Figure 25-5 for load conditions. TABLE 25-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP) Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param Sym. No. Characteristic CC01* TccL CCP Input Low Time CC02* TccH CCP Input High Time CC03* TccP * † CCP Input Period Min. Typ† Max. Units 0.
PIC16(L)F1516/7/8/9 TABLE 25-7: ANALOG-TO-DIGITAL CONVERTER (ADC) CHARACTERISTICS:(1,2,3) Standard Operating Conditions (unless otherwise stated) Operating temperature Tested at +25°C Param Sym. No. Characteristic Min. Typ† Max. Units Conditions AD01 NR Resolution — — 10 AD02 EIL Integral Error — ±1 ±1.7 AD03 EDL Differential Error — ±1 ±1 AD04 EOFF Offset Error — ±1 ±2.5 LSb VREF = 3.0V AD05 EGN — ±1 ±2.0 LSb VREF = 3.0V AD06 VREF Reference Voltage(4) 1.
PIC16(L)F1516/7/8/9 FIGURE 25-12: ADC CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO AD134 1 TCY (TOSC/2(1)) AD131 Q4 AD130 ADC CLK 7 ADC Data 6 4 5 3 2 1 0 NEW_DATA OLD_DATA ADRES 1 TCY ADIF GO Sample DONE Sampling Stopped AD132 Note 1: If the ADC clock source is selected as FRC oscillator, a time of TCY is added before the ADC clock starts. This allows the SLEEP instruction to be executed.
PIC16(L)F1516/7/8/9 TABLE 25-9: LOW DROPOUT (LDO) REGULATOR CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param Sym. No. Characteristic Min. Typ† Max. Units LDO01 LDO Regulation Voltage — 3.0 — V LDO02 LDO External Capacitor 0.1 — 1 F † Conditions Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
PIC16(L)F1516/7/8/9 FIGURE 25-15: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING CK US125 DT US126 Note: Refer to Figure 25-5 for load conditions. TABLE 25-11: USART SYNCHRONOUS RECEIVE REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param. No. Symbol Characteristic US125 TDTV2CKL SYNC RCV (Master and Slave) Data-hold before CK (DT hold time) US126 TCKL2DTL Data-hold after CK (DT hold time) DS40001452D-page 302 Min. Max.
PIC16(L)F1516/7/8/9 FIGURE 25-16: SPI MASTER MODE TIMING (CKE = 0, SMP = 0) SSx SP70 SCKx (CKP = 0) SP71 SP72 SP78 SP79 SP79 SP78 SCKx (CKP = 1) SP80 bit 6 - - - - - -1 MSb SDOx LSb SP75, SP76 SDIx MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 25-5 for load conditions.
PIC16(L)F1516/7/8/9 FIGURE 25-18: SPI SLAVE MODE TIMING (CKE = 0) SSx SP70 SCKx (CKP = 0) SP83 SP71 SP72 SP78 SP79 SP79 SP78 SCKx (CKP = 1) SP80 MSb SDOx LSb bit 6 - - - - - -1 SP77 SP75, SP76 SDIx MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 25-5 for load conditions.
PIC16(L)F1516/7/8/9 TABLE 25-12: SPI MODE REQUIREMENTS Param No. Symbol Characteristic Min. Typ† Max. Units Conditions SP70* TSSL2SCH, SSx to SCKx or SCKx input TSSL2SCL TCY — — ns SP71* TSCH SCKx input high time (Slave mode) TCY + 20 — — ns SP72* TSCL SCKx input low time (Slave mode) TCY + 20 — — ns 100 — — ns 100 — — ns 3.0-5.5V — 10 25 ns 1.8-5.
PIC16(L)F1516/7/8/9 I2C™ BUS START/STOP BITS TIMING FIGURE 25-20: SCLx SP93 SP91 SP90 SP92 SDAx Stop Condition Start Condition Note: Refer to Figure 25-5 for load conditions. TABLE 25-13: I2C™ BUS START/STOP BITS REQUIREMENTS Param No. SP90* SP91* SP92* SP93 Symbol TSU:STA THD:STA TSU:STO Characteristic Typ Max.
PIC16(L)F1516/7/8/9 FIGURE 25-21: I2C™ BUS DATA TIMING SP103 SCLx SP100 SP90 SP102 SP101 SP106 SP107 SP91 SP92 SDAx In SP110 SP109 SP109 SDAx Out Note: Refer to Figure 25-5 for load conditions. TABLE 25-14: I2C™ BUS DATA REQUIREMENTS Param. No. Symbol SP100* THIGH Characteristic Clock high time Min. Max. Units 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz 1.5TCY — — 100 kHz mode 4.
PIC16(L)F1516/7/8/9 NOTES: DS40001452D-page 308 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 26.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range.
PIC16(L)F1516/7/8/9 FIGURE 26-1: IDD, LP OSCILLATOR MODE, FOSC = 32 kHz, PIC16LF1516/7/8/9 ONLY 30 Max: 85°C + 3ı Typical: 25°C 25 Max. IDD (μA) 20 15 Typical 10 5 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 26-2: IDD, LP OSCILLATOR MODE, FOSC = 32 kHz, PIC16F1516/7/8/9 ONLY 40 Max. Max: 85°C + 3ı Typical: 25°C 35 30 Typical IDD (μA) 25 20 15 10 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.
PIC16(L)F1516/7/8/9 FIGURE 26-3: IDD TYPICAL, XT AND EXTRC OSCILLATOR, PIC16LF1516/7/8/9 ONLY 350 Typical: 25°C 300 4 MHz XT IDD (μA) 250 200 150 1 MHz XT 100 50 1 MHz EXTRC 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 26-4: IDD MAXIMUM, XT AND EXTRC OSCILLATOR, PIC16LF1516/7/8/9 ONLY 400 Max: 85°C + 3ı 350 4 MHz XT 300 IDD (μA) 250 200 150 1 MHz XT 100 50 1 MHz EXTRC 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.
PIC16(L)F1516/7/8/9 FIGURE 26-5: IDD TYPICAL, XT AND EXTRC OSCILLATOR, PIC16F1516/7/8/9 ONLY 450 400 4 MHz XT Typical: 25°C 350 4 MHz EXTRC IDD (μA) 300 250 1 MHz XT 200 150 100 1 MHz EXTRC 50 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 26-6: IDD MAXIMUM, XT AND EXTRC OSCILLATOR, PIC16F1516/7/8/9 ONLY 500 4 MHz XT Max: 85°C + 3ı 450 400 4 MHz EXTRC 350 IDD (μA) 300 1 MHz XT 250 200 150 1 MHz EXTRC 100 50 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.
PIC16(L)F1516/7/8/9 FIGURE 26-7: IDD, EC OSCILLATOR, LOW-POWER MODE, FOSC = 32 kHz, PIC16LF1516/7/8/9 ONLY 25 Max. Max: 85°C + 3ı Typical: 25°C 20 IDD (μA) 15 Typical 10 5 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 26-8: IDD, EC OSCILLATOR, LOW-POWER MODE, FOSC = 32 kHz, PIC16F1516/7/8/9 ONLY 35 Max. Max: 85°C + 3ı Typical: 25°C 30 IDD (μA) 25 Typical 20 15 10 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 FIGURE 26-9: IDD, EC OSCILLATOR, LOW-POWER MODE, FOSC = 500 kHz, PIC16LF1516/7/8/9 ONLY 60 Max. Max: 85°C + 3ı Typical: 25°C 50 IDD (μA) 40 Typical 30 20 10 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 26-10: IDD, EC OSCILLATOR, LOW-POWER MODE, FOSC = 500 kHz, PIC16F1516/7/8/9 ONLY 70 Max. Max: 85°C + 3ı Typical: 25°C 60 Typical IDD (μA) 50 40 30 20 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.
PIC16(L)F1516/7/8/9 FIGURE 26-11: IDD TYPICAL, EC OSCILLATOR, MEDIUM-POWER MODE, PIC16LF1516/7/8/9 ONLY 300 4 MHz Typical: 25°C 250 IDD (μA) 200 150 100 1 MHz 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 3.4 3.6 3.8 VDD (V) FIGURE 26-12: IDD MAXIMUM, EC OSCILLATOR, MEDIUM-POWER MODE, PIC16LF1516/7/8/9 ONLY 350 4 MHz Max: 85°C + 3ı 300 IDD (μA) 250 200 150 1 MHz 100 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 VDD (V) 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 FIGURE 26-13: IDD TYPICAL, EC OSCILLATOR, MEDIUM-POWER MODE, PIC16F1516/7/8/9 ONLY 350 4 MHz Typical: 25°C 300 IDD (μA) 250 200 1 MHz 150 100 50 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) IDD MAXIMUM, EC OSCILLATOR, MEDIUM-POWER MODE, PIC16F1516/7/8/9 ONLY FIGURE 26-14: 400 350 Max: 85°C + 3ı 4 MHz 300 IDD (μA) 250 200 1 MHz 150 100 50 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) DS40001452D-page 316 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 FIGURE 26-15: IDD TYPICAL, EC OSCILLATOR, HIGH-POWER MODE, PIC16LF1516/7/8/9 ONLY 1.6 Typical: 25°C 1.4 20 MHz 1.2 16 MHz IDD (mA) 1.0 0.8 0.6 8 MHz 0.4 0.2 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 26-16: IDD MAXIMUM, EC OSCILLATOR, HIGH-POWER MODE, PIC16LF1516/7/8/9 ONLY 1.8 1.6 Max: 85°C + 3ı 20 MHz 1.4 IDD (mA) 1.2 16 MHz 1.0 0.8 0.6 8 MHz 0.4 0.2 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.
PIC16(L)F1516/7/8/9 FIGURE 26-17: IDD TYPICAL, EC OSCILLATOR, HIGH-POWER MODE, PIC16F1516/7/8/9 ONLY 1.6 20 MHz Typical: 25°C 1.4 1.2 16 MHz IDD (mA) 1.0 0.8 8 MHz 0.6 0.4 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 26-18: IDD MAXIMUM, EC OSCILLATOR, HIGH-POWER MODE, PIC16F1516/7/8/9 ONLY 1.8 Max: 85°C + 3ı 1.6 20 MHz 1.4 16 MHz IDD (mA) 1.2 1.0 0.8 8 MHz 0.6 0.4 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.
PIC16(L)F1516/7/8/9 FIGURE 26-19: IDD, LFINTOSC MODE, FOSC = 31 kHz, PIC16LF1516/7/8/9 ONLY 30 Max: 85°C + 3ı Typical: 25°C 25 Max. IDD (μA) 20 15 Typical 10 5 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 26-20: IDD, LFINTOSC MODE, FOSC = 31 kHz, PIC16F1516/7/8/9 ONLY 35 Max. 30 IDD (μA) 25 Typical 20 15 10 Max: 85°C + 3ı Typical: 25°C 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 FIGURE 26-21: IDD, MFINTOSC MODE, FOSC = 500 kHz, PIC16LF1516/7/8/9 ONLY 350 Max. Max: 85°C + 3ı Typical: 25°C 300 IDD (μA) Typical 250 200 150 100 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 26-22: IDD, MFINTOSC MODE, FOSC = 500 kHz, PIC16F1516/7/8/9 ONLY 450 Max. Max: 85°C + 3ı Typical: 25°C 400 Typical IDD (μA) 350 300 250 200 150 100 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.
PIC16(L)F1516/7/8/9 FIGURE 26-23: IDD TYPICAL, HFINTOSC MODE, PIC16LF1516/7/8/9 ONLY 1.4 16 MHz Typical: 25°C 1.2 IDD (mA) 1.0 8 MHz 0.8 4 MHz 0.6 0.4 0.2 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 3.6 3.8 VDD (V) FIGURE 26-24: IDD MAXIMUM, HFINTOSC MODE, PIC16LF1516/7/8/9 ONLY 1.6 16 MHz 1.4 Max: 85°C + 3ı IDD (mA) 1.2 1.0 8 MHz 0.8 4 MHz 0.6 0.4 0.2 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 VDD (V) 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 FIGURE 26-25: IDD TYPICAL, HFINTOSC MODE, PIC16F1516/7/8/9 ONLY 1.4 16 MHz Typical: 25°C 1.2 1.0 IDD (mA) 8 MHz 0.8 4 MHz 0.6 0.4 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 5.5 6.0 VDD (V) FIGURE 26-26: IDD MAXIMUM, HFINTOSC MODE, PIC16F1516/7/8/9 ONLY 1.6 1.4 16 MHz Max: 85°C + 3ı 1.2 IDD (mA) 1.0 8 MHz 0.8 4 MHz 0.6 0.4 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VDD (V) DS40001452D-page 322 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 FIGURE 26-27: IDD TYPICAL, HS OSCILLATOR, PIC16LF1516/7/8/9 ONLY 1.8 Typical: 25°C 1.6 20 MHz 1.4 IDD (mA) 1.2 1 0.8 8 MHz 0.6 4 MHz 0.4 0.2 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 3.4 3.6 3.8 VDD (V) FIGURE 26-28: IDD MAXIMUM, HS OSCILLATOR, PIC16LF1516/7/8/9 ONLY 2.0 1.8 Max: 85°C + 3ı 20 MHz 1.6 1.4 IDD (mA) 1.2 1.0 8 MHz 0.8 0.6 4 MHz 0.4 0.2 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 VDD (V) 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 FIGURE 26-29: IDD TYPICAL, HS OSCILLATOR, PIC16F1516/7/8/9 ONLY 2 1.8 Typical: 25°C 20 MHz 1.6 1.4 IDD (mA) 1.2 1 8 MHz 0.8 0.6 4 MHz 0.4 0.2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 26-30: IDD MAXIMUM, HS OSCILLATOR, PIC16F1516/7/8/9 ONLY 2.5 20 MHz Max: 85°C + 3ı 2.0 IDD (mA) 1.5 8 MHz 1.0 4 MHz 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) DS40001452D-page 324 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 FIGURE 26-31: IPD BASE, SLEEP MODE, PIC16LF1516/7/8/9 ONLY 450 Max: 85°C + 3 M 3ı Typical: 25°C 400 Max. 350 IPD D (nA) 300 250 200 150 100 Typical 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 26-32: IPD BASE, LOW-POWER SLEEP MODE (VREGPM = 1), PIC16F1516/7/8/9 ONLY 600 Max. Max: 85°C + 3ı Typical: 25°C 500 IPD (nA) 400 300 Typical 200 100 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 FIGURE 26-33: IPD, WATCHDOG TIMER (WDT), PIC16LF1516/7/8/9 ONLY 1.4 Max: 85°C + 3ı Typical: 25°C 1.2 Max. IPD (μA (μA) 1.0 0 8 0.8 Typical 0.6 0.4 0.2 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 26-34: IPD, WATCHDOG TIMER (WDT), PIC16F1516/7/8/9 ONLY 1.2 Max: 85°C + 3ı Typical: 25°C 1.0 Max. IPD (μA A) 0.8 Typical 0.6 0.4 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.
PIC16(L)F1516/7/8/9 FIGURE 26-35: IPD, FIXED VOLTAGE REFERENCE (FVR), PIC16LF1516/7/8/9 ONLY 25 Max. Typical 20 IPD (μA A) 15 10 Max: 85°C + 3ı Typical: 25°C 5 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 26-36: IPD, FIXED VOLTAGE REFERENCE (FVR), PIC16F1516/7/8/9 ONLY 30 Max. 25 IPD (μA) 20 Typical 15 10 Max: 85°C + 3ı Typical: 25°C 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 FIGURE 26-37: IPD, BROWN-OUT RESET (BOR), BORV = 1, PIC16LF1516/7/8/9 ONLY 12 Max. Max: 85°C + 3ı Typical: 25°C 10 8 IPD D (μA) Typical 6 4 2 0 16 1.6 1 8 1.8 2 0 2.0 2 2 2.2 2 4 2.4 2 6 2.6 2 8 2.8 3 0 3.0 3 2 3.2 3 4 3.4 3 6 3.6 3 8 3.8 VDD (V) IPD, BROWN-OUT RESET (BOR), BORV = 1, PIC16F1516/7/8/9 ONLY FIGURE 26-38: 14 Max Max. Max: 85°C + 3ı Ma Typical: 25°C 12 IPD (μA) 10 Typical 8 6 4 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.
PIC16(L)F1516/7/8/9 FIGURE 26-39: IPD, SECONDARY OSCILLATOR, FOSC = 32 kHz, PIC16LF1516/7/8/9 ONLY 6.0 Max: 85°C + 3ı Typical: 25°C 5.0 Max. IPD (μA A) 4.0 3.0 Typical 2.0 1.0 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 26-40: IPD, SECONDARY OSCILLATOR, FOSC = 32 kHz, PIC16F1516/7/8/9 ONLY 12 Max: 85°C + 3ı Typical: 25°C 10 Max. IPD (μA) 8 Typical 6 4 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 FIGURE 26-41: VOH VS. IOH OVER TEMPERATURE, VDD = 5.5V, PIC16F1516/7/8/9 ONLY 6 Max: 125°C + 3ı Typical: 25°C Min: -40°C - 3ı 5 VOH (V) 4 Min. (-40°C) 3 Typical (25°C) 2 Max. (125°C) 1 0 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 IOH (mA) VOL VS. IOL OVER TEMPERATURE, VDD = 5.5V, PIC16F1516/7/8/9 ONLY FIGURE 26-42: 5 Max: 125°C + 3ı Typical: 25°C Min: -40°C - 3ı 4 Max. (125°C) VOL (V) Typical (25°C) 3 Min.
PIC16(L)F1516/7/8/9 FIGURE 26-43: VOH VS. IOH OVER TEMPERATURE, VDD = 3.0V 3.5 Max: 125°C + 3ı Typical: 25°C Min: -40°C - 3ı 3.0 VOH (V) 2.5 2.0 1.5 1.0 Min. (-40°C) Typical (25°C) Max. (125°C) 0.5 0.0 -15 -13 -11 -9 -7 -5 -3 -1 IOH (mA) FIGURE 26-44: VOL VS. IOL OVER TEMPERATURE, VDD = 3.0V 3.0 Max: 125°C + 3ı Typical: 25°C Min: -40°C - 3ı 2.5 VOL (V) 2.0 Max. (125°C) Typical (25°C) Min. (-40°C) 1.5 1.0 0.5 0.
PIC16(L)F1516/7/8/9 FIGURE 26-45: VOH VS. IOH OVER TEMPERATURE, VDD = 1.8V, PIC16LF1516/7/8/9 ONLY 2.0 1.8 Max: 125°C + 3ı Typical: 25°C Min: -40°C - 3ı 1.6 VOH (V) 1.4 1.2 Min. (-40°C) Max. (125°C) Typical (25°C) 1.0 0.8 0.6 0.4 0.2 0.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 IOH (mA) VOL VS. IOL OVER TEMPERATURE, VDD = 1.8V, PIC16LF1516/7/8/9 ONLY FIGURE 26-46: 1.8 Max: 125°C + 3ı Typical: 25°C Min: -40°C - 3ı 1.6 1.4 VOL (V) 1.2 1.0 0.8 Max. (125°C) Min.
PIC16(L)F1516/7/8/9 FIGURE 26-47: POR RELEASE VOLTAGE 1.70 1.68 Max. 1.66 Voltage (V) 1.64 Typical 1.62 Min. 1.60 1.58 1.56 Max: Typical + 3ı Typical: 25°C Min: Typical - 3ı 1.54 1.52 1.50 -60 -40 -20 0 20 40 60 80 100 120 140 120 140 Temperature (°C) FIGURE 26-48: POR REARM VOLTAGE, PIC16F1516/7/8/9 ONLY 1.54 Max: Typical + 3ı Typical: 25°C Min: Typical - 3ı 1.52 1.50 Max. Voltage (V) 1.48 1.46 1.44 Typical 1.42 1.40 Min. 1.38 1.36 1.
PIC16(L)F1516/7/8/9 FIGURE 26-49: BROWN-OUT RESET VOLTAGE, BORV = 1, PIC16LF1516/7/8/9 ONLY 2.00 Max. Voltage (V) 1.95 Typical 1.90 1.85 Min. Max: Typical + 3ı Min: Typical - 3ı 1.80 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 26-50: BROWN-OUT RESET HYSTERESIS, BORV = 1, PIC16LF1516/7/8/9 ONLY 60 50 Max. Max: Typical + 3ı Typical: 25°C Min: Typical - 3ı Voltage (mV) 40 Typical 30 20 Min.
PIC16(L)F1516/7/8/9 FIGURE 26-51: BROWN-OUT RESET VOLTAGE, BORV = 1, PIC16F1516/7/8/9 ONLY 2.60 Max. 2.55 Voltage (V) 2.50 Typical 2.45 Min. 2.40 Max: Typical + 3ı Min: Typical - 3ı 2.35 2.30 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 26-52: BROWN-OUT RESET HYSTERESIS, BORV = 1, PIC16F1516/7/8/9 ONLY 70 Max. 60 Max: Typical + 3ı Typical: 25°C Min: Typical - 3ı Voltage (mV) 50 40 Typical 30 20 Min.
PIC16(L)F1516/7/8/9 FIGURE 26-53: BROWN-OUT RESET VOLTAGE, BORV = 0 2.80 2.75 Voltage (V) Max. 2.70 Typical 2.65 Min. Max: Typical + 3ı Min: Typical - 3ı 2.60 2.55 -60 -40 -20 0 20 40 60 80 100 120 140 120 140 Temperature (°C) FIGURE 26-54: BROWN-OUT RESET HYSTERESIS, BORV = 0 90 80 Min. 70 Voltage (mV) 60 Typical 50 40 Max: Typical + 3ı Typical: 25°C Min: Typical - 3ı 30 20 Max.
PIC16(L)F1516/7/8/9 FIGURE 26-55: LOW-POWER BROWN-OUT RESET VOLTAGE, LPBOR = 0 2.50 Max. Max: Typical + 3ı Min: Typical - 3ı 2.40 Voltage (V) 2.30 Typical 2.20 2.10 2.00 Min. 1.90 1.80 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 26-56: LOW-POWER BROWN-OUT RESET HYSTERESIS, LPBOR = 0 45 Max: Typical + 3ı Typical: 25°C Min: Typical - 3ı 40 35 Max. Typical Voltage (mV) 30 25 Min.
PIC16(L)F1516/7/8/9 FIGURE 26-57: WDT TIME-OUT PERIOD 24 22 Max. Time (ms) 20 18 Typical 16 Min. 14 Max: Typical + 3ı (-40°C to +125°C) Typical: statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C) 12 10 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 26-58: PWRT PERIOD 100 Max: Typical + 3ı (-40°C to +125°C) Typical: statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C) 90 Max. Time (ms) 80 70 Typical 60 Min. 50 40 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.
PIC16(L)F1516/7/8/9 FIGURE 26-59: FVR STABILIZATION PERIOD 40 35 Max: Typical + 3ı Typical: statistical mean @ 25°C Max. Time (us) 30 Typical 25 20 15 Note: The FVR Stabilization Period applies when: 1) coming out of Reset or exiting Sleep mode for PIC12/16LFxxxx devices. 2) when exiting Sleep mode with VREGPM = 1 for PIC12/16Fxxxx devices In all other cases, the FVR is stable when released from Reset. 10 5 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.
PIC16(L)F1516/7/8/9 FIGURE 26-60: LFINTOSC FREQUENCY OVER VDD AND TEMPERATURE, PIC16LF1516/7/8/9 ONLY 36 34 Max. Frequency (kHz) 32 30 Typical 28 Min. 26 24 Max: Typical + 3ı (-40°C to +125°C) Typical: statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C) 22 20 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 26-61: LFINTOSC FREQUENCY OVER VDD AND TEMPERATURE, PIC16F1516/7/8/9 ONLY 36 34 Max. Frequency (kHz) 32 30 Typical 28 26 Min.
PIC16(L)F1516/7/8/9 27.
PIC16(L)F1516/7/8/9 27.2 MPLAB XC Compilers The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16, and 32-bit MCU and DSC devices. These compilers provide powerful integration capabilities, superior code optimization and ease of use. MPLAB XC Compilers run on Windows, Linux or MAC OS X. For easy source level debugging, the compilers provide debug information that is optimized to the MPLAB X IDE.
PIC16(L)F1516/7/8/9 27.6 MPLAB X SIM Software Simulator The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC16(L)F1516/7/8/9 27.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification.
PIC16(L)F1516/7/8/9 28.0 PACKAGING INFORMATION 28.1 Package Marking Information 28-Lead SOIC (7.50 mm) XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX Example PIC16F1516-E/SO e3 1248017 YYWWNNN 28-Lead SPDIP (.300”) Example PIC16F1516-E/SP e3 1248017 28-Lead SSOP (5.30 mm) Example PIC16F1516 -E/SS e3 1248017 Legend: XX...
PIC16(L)F1516/7/8/9 Package Marking Information (Continued) 28-Lead UQFN (4x4x0.5 mm) PIN 1 Example PIN 1 40-Lead PDIP (600 mil) XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN Example PIC16F1517-E/P 1248107 40-Lead UQFN (5x5x0.5 mm) PIN 1 Example PIN 1 44-Lead TQFP (10x10x1 mm) XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN DS40001452D-page 346 PIC16 F1516 E/MV e3 248017 PIC16 LF1517 -E/MV e3 1248017 Example PIC16F1517 -E/PT e3 1248017 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 28.2 Package Details The following sections give the technical details of the packages. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001452D-page 348 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 ! " 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB 6 &! ' ! 9 ' &! 7"') % ! 7,8. 7 7 & ; < & & 7: 1 , = = - 1 ! & & = = .
PIC16(L)F1516/7/8/9 #$ ! " % &' % 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 D N E E1 1 2 b NOTE 1 e c A2 A φ A1 L L1 6 &! ' ! 9 ' &! 7"') % ! 99 . . 7 7 7: ; < & : 8 & = = ? < & # %% = = : > #& . < < # # 4 > #& .
PIC16(L)F1516/7/8/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001452D-page 352 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001452D-page 354 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 ( ) ! " 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB 6 &! ' ! 9 ' &! 7"') % ! 7,8. 7 7 & ; & & 7: 1 , = = = 1 ! & & = = .
PIC16(L)F1516/7/8/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001452D-page 358 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 (( *# ! " + , - * . /. /. 0 ' *+, 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 D D1 E e E1 N b NOTE 1 1 2 3 NOTE 2 α A φ c β A2 A1 L L1 6 &! ' ! 9 ' &! 7"') % 9 #! 99 . .
PIC16(L)F1516/7/8/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 NOTES: DS40001452D-page 362 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 APPENDIX A: DATA SHEET REVISION HISTORY Revision A (12/2010) Original release. Revision B (05/2011) Initial public release of device family. Revision C (09/2012) Update to Electrical Specifications and release of Characterization Data. Revision D (07/2013) Updated the Notes in Figures 2 and 4; Updated Table 5-1, Register 14-1, Register 20-1 and Table 21-4; Updated Section 22.
PIC16(L)F1516/7/8/9 NOTES: DS40001452D-page 364 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 INDEX A A/D Specifications............................................................ 299 Absolute Maximum Ratings .............................................. 277 AC Characteristics Industrial and Extended ............................................ 292 Load Conditions ........................................................ 291 ACKSTAT ......................................................................... 214 ACKSTAT Status Flag ..................................................
PIC16(L)F1516/7/8/9 Internal Oscillator Clock Switch Timing............... 53 LFINTOSC .......................................................... 52 Clock Switching................................................................... 55 Code Examples ADC Conversion ....................................................... 140 Changing Between Capture Prescalers .................... 170 Initializing PORTA..................................................... 109 Writing to Flash Program Memory ...................
PIC16(L)F1516/7/8/9 COMF ....................................................................... 269 DECF ........................................................................ 269 DECFSZ.................................................................... 270 GOTO ....................................................................... 270 INCF.......................................................................... 270 INCFSZ .....................................................................
PIC16(L)F1516/7/8/9 PMDRH Register............................................................... 104 PORTA.............................................................................. 109 Associated Registers ................................................ 112 Configuration Word w/ PORTA ................................. 112 PORTA Register ................................................... 30, 31 Specifications............................................................ 294 PORTA Register ..............
PIC16(L)F1516/7/8/9 SSPCON1 Register .......................................................... 227 SSPCON2 Register .......................................................... 228 SSPCON3 Register .......................................................... 229 SSPMSK Register............................................................. 230 SSPOV.............................................................................. 216 SSPOV Status Flag ..........................................................
PIC16(L)F1516/7/8/9 Requirements, Synchronous Receive............... 302 Requirements, Synchronous Transmission ...... 301 Timing Diagram, Synchronous Receive............ 302 Timing Diagram, Synchronous Transmission ... 301 V VREF. SEE ADC Reference Voltage VREGCON Register............................................................ 84 W Wake-up on Break ............................................................ 250 Wake-up Using Interrupts ...................................................
PIC16(L)F1516/7/8/9 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC16(L)F1516/7/8/9 NOTES: DS40001452D-page 372 2010-2013 Microchip Technology Inc.
PIC16(L)F1516/7/8/9 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. [X](1) PART NO.
PIC16(L)F1516/7/8/9 NOTES: DS40001452D-page 374 2010-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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