Datasheet

 2010-2013 Microchip Technology Inc. DS40001452D-page 369
PIC16(L)F1516/7/8/9
SSPCON1 Register .......................................................... 227
SSPCON2 Register .......................................................... 228
SSPCON3 Register .......................................................... 229
SSPMSK Register............................................................. 230
SSPOV.............................................................................. 216
SSPOV Status Flag .......................................................... 216
SSPSTAT Register ..................................................... 32, 226
R/W
Bit...................................................................... 195
Stack ................................................................................... 35
Accessing.................................................................... 35
Reset........................................................................... 37
Stack Overflow/Underflow................................................... 66
STATUS Register ............................................................... 21
SUBWFB........................................................................... 275
T
T1CON Register ......................................................... 30, 161
T1GCON Register............................................................. 162
T2CON (Timer2) Register................................................. 167
T2CON Register ................................................................. 30
Temperature Indicator
Associated Registers ................................................ 134
Temperature Indicator Module.......................................... 133
Thermal Considerations.................................................... 290
Timer0 ............................................................................... 149
Associated Registers ................................................ 151
Operation .................................................................. 149
Specifications............................................................ 297
Timer1 ............................................................................... 153
Associated registers.................................................. 163
Asynchronous Counter Mode ................................... 155
Reading and Writing ......................................... 155
Clock Source Selection............................................. 154
Interrupt..................................................................... 157
Operation .................................................................. 154
Operation During Sleep ............................................ 157
Prescaler................................................................... 155
Secondary Oscillator................................................. 155
Specifications............................................................ 297
Timer1 Gate
Selecting Source............................................... 155
TMR1H Register .......................................................153
TMR1L Register........................................................ 153
Timer2 ............................................................................... 165
Associated registers.................................................. 168
Timers
Timer1
T1CON.............................................................. 161
T1GCON........................................................... 162
Timer2
T2CON.............................................................. 167
Timing Diagrams
Acknowledge Sequence ........................................... 218
ADC Conversion ....................................................... 300
ADC Conversion (Sleep Mode)................................. 300
Asynchronous Reception .......................................... 238
Asynchronous Transmission..................................... 234
Asynchronous Transmission (Back to Back) ............ 234
Auto Wake-up Bit (WUE) During Normal Operation . 251
Auto Wake-up Bit (WUE) During Sleep .................... 251
Automatic Baud Rate Calibration.............................. 249
Baud Rate Generator with Clock Arbitration ............. 211
BRG Reset Due to SDA Arbitration During Start
Condition........................................................... 221
Brown-out Reset (BOR)............................................ 295
Brown-out Reset Situations ........................................ 65
Bus Collision During a Repeated Start
Condition (Case 1)............................................ 222
Bus Collision During a Repeated Start
Condition (Case 2)............................................ 222
Bus Collision During a Start Condition (SCL = 0) ..... 221
Bus Collision During a Stop Condition (Case 1)....... 223
Bus Collision During a Stop Condition (Case 2)....... 223
Bus Collision During Start Condition (SDA only) ...... 220
Bus Collision for Transmit and Acknowledge ........... 219
Capture/Compare/PWM (CCP) ................................ 298
CLKOUT and I/O ...................................................... 293
Clock Synchronization .............................................. 208
Clock Timing............................................................. 292
Fail-Safe Clock Monitor (FSCM)................................. 59
First Start Bit Timing ................................................. 212
I
2
C Bus Data............................................................. 307
I
2
C Bus Start/Stop Bits ............................................. 306
I
2
C Master Mode (7 or 10-Bit Transmission) ............ 215
I
2
C Master Mode (7-Bit Reception) .......................... 217
I
2
C Stop Condition Receive or Transmit Mode......... 218
INT Pin Interrupt ......................................................... 74
Internal Oscillator Switch Timing ................................ 54
Repeat Start Condition ............................................. 213
Reset Start-up Sequence ........................................... 67
Reset, WDT, OST and Power-up Timer ................... 294
Send Break Character Sequence............................. 252
SPI Master Mode (CKE = 1, SMP = 1) ..................... 303
SPI Mode (Master Mode) ......................................... 185
SPI Slave Mode (CKE = 0)....................................... 304
SPI Slave Mode (CKE = 1)....................................... 304
Synchronous Reception (Master Mode, SREN) ....... 256
Synchronous Transmission ...................................... 254
Synchronous Transmission (Through TXEN)........... 254
Timer0 and Timer1 External Clock ........................... 296
Timer1 Incrementing Edge ....................................... 157
Two Speed Start-up.................................................... 57
USART Synchronous Receive (Master/Slave) ......... 302
USART Synchronous Transmission (Master/Slave). 301
Wake-up from Interrupt............................................... 82
Timing Parameter Symbology .......................................... 291
Timing Requirements
I
2
C Bus Data............................................................. 307
I2C Bus Start/Stop Bits............................................. 306
TMR0 Register.................................................................... 30
TMR1H Register................................................................. 30
TMR1L Register.................................................................. 30
TMR2 Register.................................................................... 30
TRIS ................................................................................. 276
TRISA Register........................................................... 30, 110
TRISB ............................................................................... 113
TRISB Register........................................................... 30, 114
TRISC............................................................................... 116
TRISC Register........................................................... 30, 117
TRISD............................................................................... 119
TRISD Register........................................................... 30, 120
TRISE ............................................................................... 122
TRISE Register........................................................... 30, 123
Two-Speed Clock Start-up Mode........................................ 56
TXREG ............................................................................. 233
TXREG Register................................................................. 31
TXSTA Register.......................................................... 31, 241
BRGH Bit.................................................................. 244
U
USART
Synchronous Master Mode