Datasheet

PIC16(L)F1516/7/8/9
DS40001452D-page 366  2010-2013 Microchip Technology Inc.
Internal Oscillator Clock Switch Timing............... 53
LFINTOSC ..........................................................52
Clock Switching................................................................... 55
Code Examples
ADC Conversion ....................................................... 140
Changing Between Capture Prescalers.................... 170
Initializing PORTA..................................................... 109
Writing to Flash Program Memory ............................100
Compare Module.
See Capture/Compare/PWM (CCP)
CONFIG1 Register..............................................................42
CONFIG2 Register..............................................................44
Core Function Register ....................................................... 29
Customer Change Notification Service ............................. 371
Customer Notification Service...........................................371
Customer Support ............................................................. 371
D
Data Memory....................................................................... 20
DC and AC Characteristics ............................................... 309
DC Characteristics
Extended and Industrial ............................................ 287
Industrial and Extended ............................................ 280
Development Support ....................................................... 341
Device Configuration........................................................... 41
Code Protection .......................................................... 45
Configuration Word .....................................................41
User ID.................................................................. 45, 46
Device ID Register .............................................................. 46
Device Overview ............................................................. 9, 87
E
Effects of Reset
PWM mode ...............................................................177
Electrical Specifications ....................................................277
Enhanced Mid-range CPU .................................................. 15
Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART)............................... 231
Errata .................................................................................... 8
EUSART............................................................................ 231
Associated Registers
Baud Rate Generator........................................ 245
Asynchronous Mode ................................................. 233
12-bit Break Transmit and Receive................... 252
Associated Registers
Receive..................................................... 239
Transmit.................................................... 235
Auto-Wake-up on Break....................................250
Baud Rate Generator (BRG)............................. 244
Clock Accuracy .................................................240
Receiver............................................................236
Setting up 9-bit Mode with Address Detect....... 238
Transmitter........................................................ 233
Baud Rate Generator (BRG)
Auto Baud Rate Detect ..................................... 249
Baud Rate Error, Calculating ............................ 244
Baud Rates, Asynchronous Modes................... 246
Formulas........................................................... 245
High Baud Rate Select (BRGH Bit)................... 244
Synchronous Master Mode ............................... 253, 257
Associated Registers
Receive..................................................... 256
Transmit.................................................... 254
Reception..........................................................255
Transmission.....................................................253
Synchronous Slave Mode
Associated Registers
Receive .................................................... 258
Transmit.................................................... 257
Reception ......................................................... 258
Transmission .................................................... 257
Extended Instruction Set
ADDFSR................................................................... 267
F
Fail-Safe Clock Monitor ...................................................... 58
Fail-Safe Condition Clearing....................................... 58
Fail-Safe Detection ..................................................... 58
Fail-Safe Operation..................................................... 58
Reset or Wake-up from Sleep .................................... 58
Firmware Instructions ....................................................... 263
Fixed Voltage Reference (FVR)........................................ 131
Associated Registers................................................ 132
Flash Program Memory ...................................................... 91
Associated Registers................................................ 106
Configuration Word w/ Flash Program Memory........ 106
Erasing ....................................................................... 95
Modifying .................................................................. 101
Write Verify ............................................................... 103
Writing ........................................................................ 97
FSR Register ...................................................................... 29
FVRCON (Fixed Voltage Reference Control) Register..... 132
I
I
2
C Mode (MSSP)
Acknowledge Sequence Timing ............................... 218
Bus Collision
During a Repeated Start Condition................... 222
During a Stop Condition ................................... 223
Effects of a Reset ..................................................... 219
I
2
C Clock Rate w/BRG.............................................. 225
Master Mode
Operation.......................................................... 210
Reception ......................................................... 216
Start Condition Timing .............................. 212, 213
Transmission .................................................... 214
Multi-Master Communication, Bus Collision and
Arbitration ......................................................... 219
Multi-Master Mode.................................................... 219
Read/Write Bit Information (R/W
Bit)........................ 195
Slave Mode
Transmission .................................................... 200
Sleep Operation........................................................ 219
Stop Condition Timing .............................................. 218
INDF Register..................................................................... 29
Indirect Addressing ............................................................. 37
Instruction Format............................................................. 264
Instruction Set................................................................... 263
ADDLW..................................................................... 267
ADDWF..................................................................... 267
ADDWFC.................................................................. 267
ANDLW..................................................................... 267
ANDWF..................................................................... 267
BCF .......................................................................... 268
BRA .......................................................................... 268
BSF........................................................................... 268
BTFSC...................................................................... 268
BTFSS ...................................................................... 268
CALL......................................................................... 269
CALLW ..................................................................... 269
CLRF ........................................................................ 269
CLRW ....................................................................... 269
CLRWDT .................................................................. 269