Datasheet

 2012 Microchip Technology Inc. Preliminary DS41624B-page 81
PIC16(L)F1512/3
8.2 Low-Power Sleep Mode
The PIC16F1512/3 device contains an internal Low
Dropout (LDO) voltage regulator, which allows the
device I/O pins to operate at voltages up to 5.5V while
the internal device logic operates at a lower voltage.
The LDO and its associated reference circuitry must
remain active when the device is in Sleep mode. The
PIC16F1512/3 allows the user to optimize the
operating current in Sleep, depending on the
application requirements.
A Low-Power Sleep mode can be selected by setting
the VREGPM bit of the VREGCON register. With this
bit set, the LDO and reference circuitry are placed in a
low-power state when the device is in Sleep.
8.2.1 SLEEP CURRENT VS. WAKE-UP
TIME
In the default operating mode, the LDO and reference
circuitry remain in the normal configuration while in
Sleep. The device is able to exit Sleep mode quickly
since all circuits remain active. In Low-Power Sleep
mode, when waking up from Sleep, an extra delay time
is required for these circuits to return to the normal
configuration and stabilize.
The Low-Power Sleep mode is beneficial for
applications that stay in Sleep mode for long periods of
time. The normal mode is beneficial for applications
that need to wake from Sleep quickly and frequently.
8.2.2 PERIPHERAL USAGE IN SLEEP
Some peripherals that can operate in Sleep mode will
not operate properly with the Low-Power Sleep mode
selected. The LDO will remain in the Normal Power
mode when those peripherals are enabled. The Low-
Power Sleep mode is intended for use with these
peripherals:
• Brown-Out Reset (BOR)
• Watchdog Timer (WDT)
• External interrupt pin/interrupt-on-change pins
• Timer1 (with external clock source)
• CCP (Capture mode)
8.3 Power Control Registers
Note: The PIC16LF1512/3 does not have a
configurable Low-Power Sleep mode.
PIC16LF1512/3 is an unregulated device
and is always in the lowest power state
when in Sleep, with no wake-up time
penalty. This device has a lower maximum
V
DD and I/O voltage than the
PIC16F1512/3. See Section 25.0
“Electrical Specifications” for more
information.
REGISTER 8-1: VREGCON: VOLTAGE REGULATOR CONTROL REGISTER
(1)
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-1/1
— — — — — —VREGPMReserved
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-2 Unimplemented: Read as ‘0’
bit 1 VREGPM: Voltage Regulator Power Mode Selection bit
1 = Low-Power Sleep mode enabled in Sleep
(2)
Draws lowest current in Sleep, slower wake-up
0 = Normal-Power mode enabled in Sleep
(2)
Draws higher current in Sleep, faster wake-up
bit 0 Reserved: Read as ‘1’. Maintain this bit set.
Note 1: PIC16F1512/3 only.
2: See Section 25.0 “Electrical Specifications”.