Datasheet

 2012 Microchip Technology Inc. Preliminary DS41624B-page 343
PIC16(L)F1512/3
TRISB (Tri-State PORTB)......................................... 112
TRISC (Tri-State PORTC) ........................................ 115
TRISE (Tri-State PORTE)......................................... 118
TXSTA (Transmit Status and Control) ...................... 256
VREGCON (Voltage Regulator Control) ..................... 81
WDTCON (Watchdog Timer Control) ......................... 87
WPUB (Weak Pull-up PORTB)................................. 113
RESET .............................................................................. 289
Reset................................................................................... 59
Reset Instruction................................................................. 62
Resets................................................................................. 59
Associated Registers .................................................. 66
Revision History ................................................................ 337
S
Software Simulator (MPLAB SIM)..................................... 325
SPBRG Register ................................................................. 27
SPBRGH Register ............................................................ 259
SPBRGL Register............................................................. 259
Special Event Trigger........................................................ 134
Special Function Registers (SFRs)..................................... 26
SPI Mode (MSSP)
Associated Registers ................................................ 193
SPI Clock .................................................................. 189
SSPADD Register............................................................. 235
SSPCON1 Register .......................................................... 232
SSPCON2 Register .......................................................... 233
SSPCON3 Register .......................................................... 234
SSPMSK Register............................................................. 235
SSPOV.............................................................................. 220
SSPOV Status Flag .......................................................... 220
SSPSTAT Register ........................................................... 231
R/W
Bit...................................................................... 199
Stack ................................................................................... 31
Accessing.................................................................... 31
Reset........................................................................... 33
Stack Overflow/Underflow................................................... 62
STATUS Register ............................................................... 19
SUBWFB........................................................................... 291
T
T1CON Register ......................................................... 26, 175
T1GCON Register............................................................. 176
T2CON (Timer2) Register................................................. 181
T2CON Register ................................................................. 26
Temperature Indicator
Associated Registers ................................................ 128
Temperature Indicator Module.......................................... 127
Thermal Considerations.................................................... 304
Timer0............................................................................... 163
Associated Registers ................................................ 165
Operation .................................................................. 163
Specifications............................................................ 311
Timer1............................................................................... 167
Associated registers.................................................. 177
Asynchronous Counter Mode ................................... 169
Reading and Writing ......................................... 169
Clock Source Selection............................................. 168
Interrupt..................................................................... 171
Operation .................................................................. 168
Operation During Sleep ............................................ 171
Prescaler................................................................... 169
Secondary Oscillator................................................. 169
Specifications............................................................ 311
Timer1 Gate
Selecting Source............................................... 169
TMR1H Register....................................................... 167
TMR1L Register ....................................................... 167
Timer2 .............................................................................. 179
Associated registers ................................................. 182
Timer2/4/6
Associated registers ................................................. 182
Timers
Timer1
T1CON ............................................................. 175
T1GCON........................................................... 176
Timer2
T2CON ............................................................. 181
Timing Diagrams
A/D Conversion ........................................................ 313
A/D Conversion (Sleep Mode).................................. 314
Acknowledge Sequence ........................................... 222
Asynchronous Reception.......................................... 254
Asynchronous Transmission .................................... 250
Asynchronous Transmission (Back to Back) ............ 251
Auto Wake-up Bit (WUE) During Normal Operation. 266
Auto Wake-up Bit (WUE) During Sleep.................... 266
Automatic Baud Rate Calibration ............................. 264
Baud Rate Generator with Clock Arbitration............. 215
BRG Reset Due to SDA Arbitration During
Start Condition.................................................. 226
Brown-out Reset (BOR)............................................ 309
Brown-out Reset Situations ........................................ 61
Bus Collision During a Repeated Start Condition
(Case 1)............................................................ 227
Bus Collision During a Repeated Start Condition
(Case 2)............................................................ 227
Bus Collision During a Start Condition (SCL = 0)..... 226
Bus Collision During a Stop Condition (Case 1)....... 228
Bus Collision During a Stop Condition (Case 2)....... 228
Bus Collision During Start Condition (SDA only) ...... 225
Bus Collision for Transmit and Acknowledge ........... 224
Capture/Compare/PWM (CCP) ................................ 312
CLKOUT and I/O ...................................................... 307
Clock Synchronization .............................................. 212
Clock Timing............................................................. 306
Fail-Safe Clock Monitor (FSCM)................................. 55
First Start Bit Timing ................................................. 216
I
2
C Bus Data............................................................. 319
I
2
C Bus Start/Stop Bits ............................................. 318
I
2
C Master Mode (7 or 10-Bit Transmission) ............ 219
I
2
C Master Mode (7-Bit Reception) .......................... 221
I
2
C Stop Condition Receive or Transmit Mode......... 223
INT Pin Interrupt ......................................................... 70
Internal Oscillator Switch Timing ................................ 50
Repeat Start Condition ............................................. 217
Reset Start-up Sequence ........................................... 63
Reset, WDT, OST and Power-up Timer ................... 308
Send Break Character Sequence............................. 267
SPI Master Mode (CKE = 1, SMP = 1) ..................... 316
SPI Mode (Master Mode) ......................................... 189
SPI Slave Mode (CKE = 0)....................................... 317
SPI Slave Mode (CKE = 1)....................................... 317
Synchronous Reception (Master Mode, SREN) ....... 271
Synchronous Transmission ...................................... 269
Synchronous Transmission (Through TXEN)........... 269
Timer0 and Timer1 External Clock ........................... 311
Timer1 Incrementing Edge ....................................... 171
Two Speed Start-up.................................................... 53
USART Synchronous Receive (Master/Slave) ......... 315
USART Synchronous Transmission (Master/Slave). 314