Datasheet

 2012 Microchip Technology Inc. Preliminary DS41624B-page 251
PIC16(L)F1512/3
FIGURE 22-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
TABLE 22-1: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 258
INTCON GIE PEIE
TMR0IE INTE IOCIE TMR0IF INTF IOCIF 72
PIE1
TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 73
PIR1
TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
75
RCSTA SPEN
RX9 SREN CREN ADDEN FERR OERR RX9D 257
SPBRGL BRG<7:0> 259*
SPBRGH BRG<15:8> 259*
TRISC TRISC7 TRISC6
TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 115
TXREG
EUSART Transmit Data Register 249*
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 256
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for asynchronous transmission.
* Page provides register information.
Transmit Shift Reg.
Write to TXREG
BRG Output
(Shift Clock)
TX/CK
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1
Word 2
Word 1
Word 2
Start bit
Stop bit
Start bit
Transmit Shift Reg.
Word 1
Word 2
bit 0 bit 1
bit 7/8 bit 0
Note: This timing diagram shows two consecutive transmissions.
1 TCY
1 TCY
pin
TXIF bit
(Transmit Buffer
Reg. Empty Flag)