Datasheet

 2012 Microchip Technology Inc. Preliminary DS41624B-page 189
PIC16(L)F1512/3
20.2.3 SPI MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK line. The master
determines when the slave (Processor 2, Figure 20-5)
is to broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SDO output could be
disabled (programmed as an input). The SSPSR
register will continue to shift in the signal present on the
SDI pin at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and Status bits
appropriately set).
The clock polarity is selected by appropriately
programming the CKP bit of the SSPCON1 register
and the CKE bit of the SSPSTAT register. This then,
would give waveforms for SPI communication as
shown in Figure 20-6, Figure 20-9 and Figure 20-10,
where the MSb is transmitted first. In Master mode, the
SPI clock rate (bit rate) is user programmable to be one
of the following:
•F
OSC/4 (or TCY)
•F
OSC/16 (or 4 * TCY)
•F
OSC/64 (or 16 * TCY)
• Timer2 output/2
• Fosc/(4 * (SSPADD + 1))
Figure 20-6 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
data is shown.
FIGURE 20-6: SPI MODE WAVEFORM (MASTER MODE)
SCK
(CKP =
0
SCK
(CKP =
1
SCK
(CKP =
0
SCK
(CKP =
1
4 Clock
Modes
Input
Sample
Input
Sample
SDI
bit 7
bit 0
SDO bit 7
bit 6
bit 5 bit 4
bit 3
bit 2
bit 1 bit 0
bit 7
SDI
SSPIF
(SMP =
1)
(SMP =
0)
(SMP =
1)
CKE =
1)
CKE =
0)
CKE =
1)
CKE =
0)
(SMP =
0)
Write to
SSPBUF
SSPSR to
SSPBUF
SDO
bit 7
bit 6
bit 5 bit 4
bit 3
bit 2
bit 1 bit 0
(CKE =
0)
(CKE =
1)
bit 0