Datasheet

PIC16(L)F1512/3
DS41624B-page 158 Preliminary  2012 Microchip Technology Inc.
REGISTER 16-13: AADACQ: A/D ACQUISITION TIME CONTROL REGISTER
REGISTER 16-14: AADGRD: A/D GUARD RING CONTROL REGISTER
U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— ADACQ<6:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-0
ADACQ<6:0>: Acquisition/Charge Share Time Select bits
(1)
111 1111 = Acquisition/charge share for 127 instruction cycles
111 1110 = Acquisition/charge share for 126 instruction cycles
•
•
•
000 0001 = Acquisition/charge share for one instruction cycle (Fosc/4)
000 0000 = ADC Acquisition/charge share time is disabled
Note 1: When the FRC clock is selected as the conversion clock source, it is also the clock used for the pre-
charge and acquisition times.
R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 U-0
GRDBOE
(2)
GRDAOE
(2)
GRDPOL
(1,2)
— — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other
Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7
GRDBOE: Guard Ring B Output Enable bit
(2)
1 = ADC guard ring output is enabled to ADGRDB pin. Its corresponding TRISx bit must be clear.
0 = No ADC guard ring function to this pin is enabled
bit 6
GRDAOE: Guard Ring A Output Enable bit
(2)
1 = ADC Guard Ring Output is enabled to ADGRDA pin. Its corresponding TRISx, x bit must be clear.
0 = No ADC Guard Ring function is enabled
bit 5
GRDPOL: Guard Ring Polarity Selection bit
(1,2)
1 = ADC guard ring outputs start as digital high during pre-charge stage
0 = ADC guard ring outputs start as digital low during pre-charge stage
bit 4-0
Unimplemented: Read as ‘0’
Note 1: When the ADDSEN = 1 and ADIPEN = 1; the polarity of this output is inverted for the second conversion
time. The stored bit value does not change.
2: Guard ring outputs are maintained while ADON = 1. The ADGRDA output switches polarity at the start of
the acquisition time.