Datasheet

PIC16(L)F1512/3
DS41624B-page 152 Preliminary  2012 Microchip Technology Inc.
16.6.10 ANALOG BUS VISIBILITY
The ADOEN and ADOLEN bits of the AADCON3
register can be used to connect the ADC conversion
bus to the ADOUT pin. This connection can be used to
monitor the state and behavior of the internal analog
bus. The ADOEN bit provides the connection via a
standard channel passgate. The ADLOEN bit provides
a lower impedance connection. Both bits can be
enabled to provide the lowest impedance connection
between the internal ADC analog bus and the ADOUT
pin.
The ADOUT pin connection can be overridden during
the pre-charge stage of conversion. This function is
controlled by the ADOOEN bit, which corresponds to
the override enable signal. The polarity of the override
is set by the ADIPPOL bit.
16.6.11 A/D DOUBLE CONVERSION
PROCEDURE
This is an example procedure for using the ADC to
perform a Double Analog-to-Digital conversion:
1. Configure Port:
• Disable pin output driver (refer to the TRIS
register)
• Configure pin as analog (refer to the ANSEL
register)
2. Configure the ADC module:
• Select ADC conversion clock
• Configure voltage reference
• Select ADC input channel
• Turn on ADC module
• Set ADDSEN bit
3. Configure ADC interrupt (optional):
• Clear ADC interrupt flag
• Enable ADC interrupt
• Enable peripheral interrupt
• Enable global interrupt
(1)
4. Wait the required acquisition time
(2)
.
5. Start conversion by setting the GO/DONE
bit.
6. Wait for ADC conversions to complete by one of
the following:
• Polling the GO/DONE
bit
• Waiting for the ADC interrupt (interrupts
enabled)
7. Read ADC Result.
• Conversion 1 result in AADRES0H and
AADRES0L
• Conversion 2 result in AADRES1H and
AADRES1L
8. Clear the ADC interrupt flag (required if interrupt
is enabled).
9. Configure Port: (required if pin is needed as an
output)
• Enable pin output driver (refer to the TRIS
register)
• Unconfigure pin as analog (refer to the ANSEL
register)
EXAMPLE 16-2: A/D DOUBLE
CONVERSION
Note 1: The global interrupt can be disabled if the
user is attempting to wake-up from Sleep
and resume in-line code execution.
2: Refer to Section 16.4 “A/D Acquisition
Requirements”
.
;This code block configures the ADC
;for polling, Vdd and Vss references, Frc
;clock and AN0 input.
;
;Conversion start & polling for completion
; are included.
;
BANKSEL AADCON1;
MOVLW B’11110000’ ;Right justify, Frc
;clock
MOVWF AADCON1 ;Vdd and Vss Vref
BANKSEL TRISA ;
BSF TRISA,0 ;Set RA0 to input
BANKSEL ANSEL ;
BSF ANSEL,0 ;Set RA0 to analog
BANKSEL AADCON0 ;
MOVLW B’00000001’ ;Select channel AN0
MOVWF AADCON0 ;Turn ADC On
CALL SampleTime ;Acquisiton delay
BSF AADCON0,GO/DONE
;Start conversion
BTFSC AADCON0,GO/DONE
;Is conversion
;done?
;RESULTS OF CONVERIONS 1.
GOTO $-1 ;No, test again
BANKSEL AADRES0H ;
MOVF AADRES0H,W ;Read upper 2 bits
MOVWF RESULTHI ;store in GPR space
BANKSEL AADRES0L ;
MOVF AADRES0L,W ;Read lower 8 bits
MOVWF RESULTLO ;Store in GPR space
;RESULTS OF CONVERIONS 2.
GOTO $-1 ;No, test again
BANKSEL AADRES1H ;
MOVF AADRES1H,W ;Read upper 2 bits
MOVWF RESULTHI ;store in GPR space
BANKSEL AADRES1L ;
MOVF AADRES1L,W ;Read lower 8 bits
MOVWF RESULTLO ;Store in GPR space