Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller SPDIP 28 8-Bit 20 MHz I/O number 25

 2012 Microchip Technology Inc. Preliminary DS41624B

PIC16(L)F1512/1513

Data Sheet

28-Pin Flash Microcontrollers

with XLP Technology

Summary of content (348 pages)

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PIC16(L)F1512/1513 Data Sheet 28-Pin Flash Microcontrollers with XLP Technology  2012 Microchip Technology Inc.
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Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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PIC16(L)F1512/3 28-Pin Flash Microcontrollers with XLP Technology High-Performance RISC CPU: • C Compiler Optimized Architecture • Only 49 Instructions • Up to 7 Kbytes Linear Program Memory Addressing • Up to 256 Bytes Linear Data Memory Addressing • Operating Speed: - DC – 20 MHz clock input @ 2.5V - DC – 16 MHz clock input @ 1.
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PIC16(L)F1512/3 FIGURE 1: Debug(1) XLP PIC16(L)F1512 (1) 2048 128 25 17 Y 2/1 1 1 PIC16(L)F1513 (1) 4096 256 25 17 Y 2/1 1 1 PIC16(L)F1516 (2) 8192 512 25 17 N 2/1 1 1 PIC16(L)F1517 (2) 8192 512 36 28 N 2/1 1 1 PIC16(L)F1518 (2) 16384 1024 25 17 N 2/1 1 1 PIC16(L)F1519 (2) 16384 1024 36 28 N 2/1 1 1 PIC16(L)F1526 (3) 8192 768 54 30 N 6/3 2 2 PIC16(L)F1527 (3) 16384 1536 54 30 N 6/3 2 2 Note 1: I - Debugging, Integrated on Chip; H - Debugging, Requires Debug Header. 2: One pin is input-only.
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PIC16(L)F1512/3 FIGURE 2: 28-PIN UQFN (4X4) PACKAGE DIAGRAM FOR PIC16(L)F1512/3 28 27 26 25 24 23 22 RA1 RA0 RE3/MCLR/VPP RB7/ICSPDAT/ICDDAT RB6/ICSPCLK/ICDCLK RB5 RB4 28-Pin UQFN PIC16F1512/3 PIC16LF1512/3 8 9 10 11 12 13 14 1 2 3 4 5 6 7 21 20 19 18 17 16 15 RB3 RB2 RB1 RB0 VDD VSS RC7 RC0 RC1 RC2 RC3 RC4 RC5 RC6 RA2 RA3 RA4 RA5 VSS RA7 RA6  2012 Microchip Technology Inc.
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PIC16(L)F1512/3 — — SS(2) — — — — — — — — — Basic — — Pull-up MSSP AN0 AN1 CCP 27 28 Timers 2 3 A/D RA0 RA1 I/O EUSART Interrupt 28-PIN ALLOCATION TABLE (PIC16(L)F1512/3) 28-Pin UQFN 28-Pin SPDIP, SOIC, SSOP TABLE 1: RA2 4 1 AN2 — — — — — — — RA3 5 2 AN3/VREF+ — — — — — — — RA4 6 3 — T0CKI — — — — — — RA5 7 4 AN4 — — — SS(1) — — VCAP RA6 10 7 — — — — — — — OSC2/CLKOUT RA7 9 6 — — — — — — — OSC1/CLKIN RB0 21 18
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PIC16(L)F1512/3 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 Enhanced Mid-range CPU ......................................................................................................................................................... 13 3.0 Memory Organization .............................................................................
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PIC16(L)F1512/3 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.
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PIC16(L)F1512/3 1.0 DEVICE OVERVIEW The PIC16(L)F1512/3 are described within this data sheet. They are available in 28-pin packages. Figure 1-1 shows a block diagram of the PIC16(L)F1512/3 devices. Table 1-2 shows the pinout descriptions. Reference Table 1-1 for peripherals available per device.
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PIC16(L)F1512/3 FIGURE 1-1: PIC16(L)F1512/3 BLOCK DIAGRAM Program Flash Memory RAM OSC2/CLKOUT PORTB Timing Generation OSC1/CLKIN PORTA CPU INTRC Oscillator PORTC (Figure 2-1) MCLR Note 1: 2: DS41624B-page 10 PORTE CCP1 Timer0 Temp. Indicator ADC 10-Bit FVR CCP2 MSSP Timer1 Timer2 EUSART See applicable chapters for more information on peripherals. See Table 1-1 for peripherals available on specific devices. Preliminary  2012 Microchip Technology Inc.
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PIC16(L)F1512/3 TABLE 1-2: PIC16(L)F1512/3 PINOUT DESCRIPTION Name RA0/AN0/SS(2) Function Input Type RA0 TTL AN0 AN SS ST RA1/AN1 RA1 TTL AN1 AN RA2/AN2 RA2 TTL AN2 AN RA3/AN3/VREF+ RA3 TTL RA4/T0CKI (1) RA5/AN4/SS /VCAP RA6/OSC2/CLKOUT RA7/OSC1/CLKIN RB0/AN12/INT RB1/AN10 RB2/AN8 RB3/AN9/CCP2(2) RB4/AN11/ADOUT RB5/AN13/T1G RB6/ICSPCLK/ADGRDA Output Type Description CMOS General purpose I/O. — A/D Channel 0 input. — Slave Select input. CMOS General purpose I/O.
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PIC16(L)F1512/3 TABLE 1-2: PIC16(L)F1512/3 PINOUT DESCRIPTION (CONTINUED) Name RB7/ICSPDAT/ADGRDB RC0/SOSCO/T1CKI RC1/SOSCI/CCP2(1) RC2/AN14/CCP1 RC3/AN15/SCK/SCL RC4/AN16/SDI/SDA RC5/AN17/SDO RC6/AN18/TX/CK RC7/AN19/RX/DT RE3/MCLR/VPP Function Input Type RB7 TTL Output Type Description CMOS General purpose I/O with IOC and WPU. ICSPDAT ST CMOS ICSP™ Data I/O. ADGRDB — CMOS Guard Ring output B. RC0 ST CMOS General purpose I/O.
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PIC16(L)F1512/3 2.0 ENHANCED MID-RANGE CPU This family of devices contain an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, Indirect, and Relative Addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory.
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PIC16(L)F1512/3 FIGURE 2-1: CORE BLOCK DIAGRAM 15 Configuration 15 MUX Flash Program Memory Program Bus 16-Level 8 Level Stack Stack (13-bit) (15-bit) 14 Instruction Instruction Reg reg 8 Data Bus Program Counter RAM Program Memory Read (PMR) 12 RAM Addr Addr MUX Indirect Addr 12 12 Direct Addr 7 5 BSR FSR Reg reg 15 FSR0reg Reg FSR FSR1 Reg FSR reg 15 STATUS Reg reg STATUS 8 3 Power-up Timer OSC1/CLKIN OSC2/CLKOUT Instruction Decodeand & Decode Control Timing Generation Oscillator
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PIC16(L)F1512/3 3.0 MEMORY ORGANIZATION 3.1 These devices contain the following types of memory: • Program Memory - Configuration Words - Device ID - User ID - Flash Program Memory • Data Memory - Core Registers - Special Function Registers - General Purpose RAM - Common RAM Program Memory Organization The enhanced mid-range core has a 15-bit program counter capable of addressing a 32K x 14 program memory space. Table 3-1 shows the memory sizes implemented for these devices.
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PIC16(L)F1512/3 FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR PIC16(L)F1512 PARTS FIGURE 3-2: PC<14:0> CALL, CALLW RETURN, RETLW Interrupt, RETFIE On-chip Program Memory PROGRAM MEMORY MAP AND STACK FOR PIC16(L)F1513 PARTS PC<14:0> CALL, CALLW RETURN, RETLW Interrupt, RETFIE 15 15 Stack Level 0 Stack Level 1 Stack Level 0 Stack Level 1 Stack Level 15 Stack Level 15 Reset Vector 0000h Reset Vector 0000h Interrupt Vector 0004h 0005h Interrupt Vector 0004h 0005h Page 0 Rollover to Page 0 Wr
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PIC16(L)F1512/3 3.1.1 READING PROGRAM MEMORY AS DATA There are two methods of accessing constants in program memory. The first method is to use tables of RETLW instructions. The second method is to set an FSR to point to the program memory. 3.1.1.1 RETLW Instruction The RETLW instruction can be used to provide access to tables of constants. The recommended way to create such a table is shown in Example 3-1.
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PIC16(L)F1512/3 3.2 Data Memory Organization 3.2.1 The data memory is partitioned in 32 memory banks with 128 bytes in a bank. Each bank consists of (Figure 3-3): • • • • 12 core registers 20 Special Function Registers (SFR) Up to 80 bytes of General Purpose RAM (GPR) 16 bytes of common RAM The core registers contain the registers that directly affect the basic operation. The core registers occupy the first 12 addresses of every data memory bank (addresses x00h/x08h through x0Bh/x8Bh).
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PIC16(L)F1512/3 3.2.1.1 STATUS Register The STATUS register, shown in Register 3-1, contains: • the arithmetic status of the ALU • the Reset status The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable.
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PIC16(L)F1512/3 3.2.2 SPECIAL FUNCTION REGISTER FIGURE 3-3: The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). The registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet. 3.2.
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 2012 Microchip Technology Inc.
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PIC16(L)F1513 MEMORY MAP (BANKS 0-7) BANK 0 000h BANK 1 080h Core Registers (Table 3-2) Preliminary 00Bh 00Ch 00Dh 00Eh 00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh PORTA PORTB PORTC — PORTE PIR1 PIR2 — — TMR0 TMR1L TMR1H T1CON T1GCON TMR2 PR2 T2CON — — 01Fh 020h — Core Registers (Table 3-2) 08Bh 08Ch 08Dh 08Eh 08Fh 090h 091h 092h 093h 094h 095h 096h 097h 098h 099h 09Ah 09Bh 09Ch 09Dh 09Eh 09Fh 0A0h General Purpose Register 80 Bytes 06Fh 070h  2012 Microchip Te
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 2012 Microchip Technology Inc.
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PIC16(L)F1512/3 TABLE 3-6: PIC16(L)F1512/3 MEMORY MAP (BANK 14) TABLE 3-7: PIC16(L)F1512/3 MEMORY MAP (BANK 31) Bank 14 Bank 31 700h F80h Core Registers (Table 3-2) 70Bh 70Ch 710h 711h 712h 713h 714h 715h 716h 717h 718h 719h 71Ah 71Bh 71Ch 71Dh 71Eh 71Fh 720h 76Fh 770h 77Fh Legend: Core Registers (Table 3-2) F8Bh F8Ch Unimplemented Read as ‘0’ Unimplemented Read as ‘0’ AADCON0 AADCON1 AADCON2 AADCON3 AADSTAT AADPRE AADACQ AADGRD AADCAP FE3h FE4h FE5h FE6h FE7h FE8h FE9h FEAh FEBh FECh FEDh FE
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PIC16(L)F1512/3 3.2.6 CORE FUNCTION REGISTERS SUMMARY The Core Function Registers listed in Table 3-8 can be addressed from any Bank.
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PIC16(L)F1512/3 3.2.7 SPECIAL FUNCTION REGISTERS SUMMARY The Special Function Registers are listed in Table 3-9.
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PIC16(L)F1512/3 TABLE 3-9: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 2 10Ch LATA PORTA Data Latch xxxx xxxx uuuu uuuu 10Dh LATB PORTB Data Latch xxxx xxxx uuuu uuuu 10Eh LATC PORTC Data Latch xxxx xxxx uuuu uuuu 10Fh to — 115h Unimplemented 116h BORCON SBOREN BORFS — — — — — 117h FVRCON FVREN FVRRDY TSEN TSRNG — — ADFVR<1:0> 118h to — 11Ch — BORRDY 10-- --
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PIC16(L)F1512/3 TABLE 3-9: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 Value on POR, BOR Value on all other Resets — — Bank 4 20Ch — Unimplemented 20Dh WPUB WPUB7 WPUB6 1111 1111 1111 1111 20Eh — Unimplemented — — 20Fh — Unimplemented — — 210h WPUE 211h SSP1BUF — — — — WPUE3 — — — ---- 1--- ---- 1--- Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx u
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PIC16(L)F1512/3 TABLE 3-9: Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets — — Bank 14 70ch to — 710h 711h Unimplemented AADCON0(3) 712h AADCON1(3) 713h AADCON2 714h AADCON3 — CHS<4:0> GO/DONE ADON -000 0000 -000 0000 ADFM ADCS<2:0> — — ADPREF<1:0> 0000 --00 0000 --00 — TRIGSEL<2:0> — — — -000 ---- -000 ---- ADOOEN — ADIPEN — ADCONV ADEPPOL ADIPPOL ADOLEN ADOEN — —
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PIC16(L)F1512/3 3.3 PCL and PCLATH 3.3.3 COMPUTED FUNCTION CALLS The Program Counter (PC) is 15 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<14:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 3-4 shows the five situations for the loading of the PC.
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PIC16(L)F1512/3 3.4 Stack 3.4.1 The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack. Both registers are read/writable. TOS is split into TOSH and TOSL due to the 15-bit size of the PC. To access the stack, adjust the value of STKPTR, which will position TOSH:TOSL, then read/write to TOSH:TOSL. STKPTR is five bits to allow detection of overflow and underflow.
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PIC16(L)F1512/3 FIGURE 3-6: ACCESSING THE STACK EXAMPLE 2 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 This figure shows the stack configuration after the first CALL or a single interrupt. If a RETURN instruction is executed, the return address will be placed in the Program Counter and the Stack Pointer decremented to the empty state (0x1F).
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PIC16(L)F1512/3 FIGURE 3-8: ACCESSING THE STACK EXAMPLE 4 TOSH:TOSL 3.4.
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PIC16(L)F1512/3 FIGURE 3-9: INDIRECT ADDRESSING 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory 0x29AF 0x29B0 FSR Address Range Reserved 0x7FFF 0x8000 0x0000 Program Flash Memory 0xFFFF Note: 0x7FFF Not all memory regions are completely implemented. Consult device memory tables for memory limits. DS41624B-page 34 Preliminary  2012 Microchip Technology Inc.
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PIC16(L)F1512/3 3.5.1 TRADITIONAL DATA MEMORY The traditional data memory is a region from FSR address 0x000 to FSR address 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers.
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PIC16(L)F1512/3 3.5.2 3.5.3 LINEAR DATA MEMORY The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the banks. Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the FSR beyond one bank will go directly to the GPR memory of the next bank.
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PIC16(L)F1512/3 4.0 DEVICE CONFIGURATION Device Configuration consists of Configuration Words, Code Protection and Device ID. 4.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h. Note: The DEBUG bit in Configuration Word 2 is managed automatically by device development tools including debuggers and programmers.
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PIC16(L)F1512/3 REGISTER 4-1: CONFIGURATION WORD 1 R/P-1 R/P-1 R/P-1 FCMEN IESO CLKOUTEN R/P-1 R/P-1 U-1 BOREN<1:0> — bit 13 R/P-1 R/P-1 R/P-1 CP MCLRE PWRTE bit 8 R/P-1 R/P-1 R/P-1 WDTE<1:0> R/P-1 R/P-1 FOSC<2:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor is enabled 0 =
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PIC16(L)F1512/3 REGISTER 4-1: bit 2-0 CONFIGURATION WORD 1 (CONTINUED) FOSC<2:0>: Oscillator Selection bits 111 = ECH: External Clock, High-Power mode (4-20 MHz): device clock supplied to CLKIN pin 110 = ECM: External Clock, Medium-Power mode (0.5-4 MHz): device clock supplied to CLKIN pin 101 = ECL: External Clock, Low-Power mode (0-0.
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PIC16(L)F1512/3 REGISTER 4-2: CONFIGURATION WORD 2 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 U-1 LVP DEBUG LPBOR BORV STVREN — bit 13 U-1 U-1 — bit 8 U-1 — — R/P-1 (1) VCAPEN U-1 U-1 — — R/P-1 R/P-1 WRT<1:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase bit 13 LVP: Low-Voltage Programming Enable bit 1 = Low-voltage programming enabled 0 = High-voltage on MC
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PIC16(L)F1512/3 4.2 Code Protection Code protection allows the device to be protected from unauthorized access. Program memory protection is controlled independently. Internal access to the program memory is unaffected by any code protection setting. 4.2.1 PROGRAM MEMORY PROTECTION The entire program memory space is protected from external reads and writes by the CP bit in Configuration Words. When CP = 0, external reads and writes of program memory are inhibited and a read will return all ‘0’s.
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PIC16(L)F1512/3 4.5 Device ID and Revision ID Development tools, such as device programmers and debuggers, may be used to read the Device ID and Revision ID. The memory location 8006h is where the Device ID and Revision ID are stored. The upper nine bits hold the Device ID. The lower five bits hold the Revision ID. See Section 11.4 “User ID, Device ID and Configuration Word Access” for more information on accessing these memory locations.
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PIC16(L)F1512/3 5.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR) 5.1 Overview The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 5-1 illustrates a block diagram of the oscillator module. Clock sources can be supplied from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits.
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PIC16(L)F1512/3 SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM FIGURE 5-1: Low-Power Mode Event Switch (SCS<1:0>) Primary Oscillator OSC2 Primary Oscillator (OSC) 2 OSC1 Primary Clock 00 SOSCO/ T1CKI SOSCI Secondary Oscillator (SOSC) Secondary Clock INTOSC 01 1x Clock Switch MUX Secondary Oscillator Internal Oscillator IRCF<3:0> 4 Start-Up Osc LF-INTOSC (31.
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PIC16(L)F1512/3 5.2 Clock Source Types Clock sources can be classified as external or internal. External clock sources rely on external circuitry for the clock source to function. Examples are: oscillator modules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC) mode circuits. Internal clock sources are contained within the oscillator module.
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PIC16(L)F1512/3 FIGURE 5-3: QUARTZ CRYSTAL OPERATION (LP, XT OR HS MODE) FIGURE 5-4: CERAMIC RESONATOR OPERATION (XT OR HS MODE) PIC® MCU PIC® MCU OSC1/CLKIN C1 C1 To Internal Logic Quartz Crystal C2 OSC1/CLKIN RS(1) RF(2) Sleep RP(3) OSC2/CLKOUT A series resistor (RS) may be required for quartz crystals with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M.
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PIC16(L)F1512/3 5.2.1.4 5.2.1.5 Secondary Oscillator External RC Mode The secondary oscillator is a separate crystal oscillator that is associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the SOSCO and SOSCI device pins. The external Resistor-Capacitor (RC) modes support the use of an external RC circuit.
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PIC16(L)F1512/3 5.2.2 INTERNAL CLOCK SOURCES 5.2.2.2 The device may be configured to use the internal oscillator block as the system clock by performing one of the following actions: • Program the FOSC<2:0> bits in Configuration Words to select the INTOSC clock source, which will be used as the default system clock upon a device Reset. • Write the SCS<1:0> bits in the OSCCON register to switch the system clock source to the internal oscillator during run-time. See Section 5.
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PIC16(L)F1512/3 5.2.2.3 Internal Oscillator Frequency Selection 5.2.2.4 The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register. The output of the 16 MHz HFINTOSC and 31 kHz LFINTOSC connects to a postscaler and multiplexer (see Figure 5-1). The Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register select the frequency output of the internal oscillators.
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PIC16(L)F1512/3 FIGURE 5-7: HFINTOSC INTERNAL OSCILLATOR SWITCH TIMING LFINTOSC (FSCM and WDT disabled) HFINTOSC Start-up Time 2-cycle Sync Running LFINTOSC IRCF <3:0> 0 0 System Clock HFINTOSC LFINTOSC (Either FSCM or WDT enabled) HFINTOSC 2-cycle Sync Running LFINTOSC 0 IRCF <3:0> 0 System Clock LFINTOSC HFINTOSC LFINTOSC turns off unless WDT or FSCM is enabled LFINTOSC Start-up Time 2-cycle Sync Running HFINTOSC IRCF <3:0> =0 0 System Clock DS41624B-page 50 Prelimi
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PIC16(L)F1512/3 5.3 Clock Switching 5.3.3 SECONDARY OSCILLATOR The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bits of the OSCCON register. The following clock sources can be selected using the SCS bits: The secondary oscillator is a separate crystal oscillator associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the SOSCO and SOSCI device pins.
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PIC16(L)F1512/3 5.4 Two-Speed Clock Start-up Mode 5.4.1 Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device.
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PIC16(L)F1512/3 5.4.2 1. 2. 3. 4. 5. 6. 7. TWO-SPEED START-UP SEQUENCE 5.4.3 Wake-up from Power-on Reset or Sleep. Instructions begin execution by the internal oscillator at the frequency set in the IRCF<3:0> bits of the OSCCON register. OST enabled to count 1024 clock cycles. OST timed out, wait for falling edge of the internal oscillator. OSTS is set. System clock held low until the next falling edge of new clock (LP, XT or HS mode). System clock is switched to external clock source.
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PIC16(L)F1512/3 5.5 Fail-Safe Clock Monitor 5.5.3 The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the Configuration Words. The FSCM is applicable to all external Oscillator modes (LP, XT, HS, EC, RC and secondary oscillator).
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PIC16(L)F1512/3 FIGURE 5-10: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure System Clock Output Clock Monitor Output (Q) Failure Detected OSCFIF Test Note: Test Test The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity.  2012 Microchip Technology Inc.
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PIC16(L)F1512/3 5.
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PIC16(L)F1512/3 REGISTER 5-2: OSCSTAT: OSCILLATOR STATUS REGISTER R-1/q U-0 R-q/q R-0/q U-0 U-0 R-0/0 R-0/q SOSCR — OSTS HFIOFR — — LFIOFR HFIOFS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Conditional bit 7 SOSCR: Secondary Oscillator Ready bit If T1OSCEN = 1: 1 = Secondary oscillator is ready 0 = S
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PIC16(L)F1512/3 NOTES: DS41624B-page 58 Preliminary  2012 Microchip Technology Inc.
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PIC16(L)F1512/3 6.0 RESETS A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 6-1. There are multiple ways to reset this device: • • • • • • • • • Power-on Reset (POR) Brown-out Reset (BOR) Low-Power Brown-out Reset (LPBOR) MCLR Reset WDT Reset RESET instruction Stack Overflow Stack Underflow Programming mode exit To allow VDD to stabilize, an optional power-up timer can be enabled to extend the Reset time after a BOR or POR event.
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PIC16(L)F1512/3 6.1 Power-on Reset (POR) 6.2 Brown-Out Reset (BOR) The POR circuit holds the device in Reset until VDD has reached an acceptable level for minimum operation. Slow rising VDD, fast operating speeds or analog performance may require greater than minimum VDD. The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met. The BOR circuit holds the device in Reset when VDD reaches a selectable minimum level.
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PIC16(L)F1512/3 FIGURE 6-2: BROWN-OUT SITUATIONS VDD VBOR Internal Reset TPWRT(1) VDD VBOR Internal Reset < TPWRT TPWRT(1) VDD VBOR Internal Reset Note 1: TPWRT(1) TPWRT delay only if PWRTE bit is programmed to ‘0’.
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PIC16(L)F1512/3 6.3 Low-Power Brown-out Reset (LPBOR) 6.5 The Low-Power Brown-Out Reset (LPBOR) is an essential part of the Reset subsystem. Refer to Figure 6-1 to see how the BOR interacts with other modules. The LPBOR is used to monitor the external VDD pin. When too low of a voltage is detected, the device is held in Reset. When this occurs, a register bit (BOR) is changed to indicate that a BOR Reset has occurred. The same bit is set for both the BOR and the LPBOR. Refer to Register 6-2. 6.3.
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PIC16(L)F1512/3 FIGURE 6-3: RESET START-UP SEQUENCE VDD Internal POR TPWRT Power-Up Timer MCLR TMCLR Internal RESET Oscillator Modes External Crystal TOST Oscillator Start-Up Timer Oscillator FOSC Internal Oscillator Oscillator FOSC External Clock (EC) CLKIN FOSC  2012 Microchip Technology Inc.
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PIC16(L)F1512/3 6.11 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON register are updated to indicate the cause of the Reset. Table 6-3 and Table 6-4 show the Reset conditions of these registers.
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PIC16(L)F1512/3 6.12 Power Control (PCON) Register The Power Control (PCON) register contains flag bits to differentiate between a: • • • • • • • Power-on Reset (POR) Brown-out Reset (BOR) Reset Instruction Reset (RI) MCLR Reset (RMCLR) Watchdog Timer Reset (RWDT) Stack Underflow Reset (STKUNF) Stack Overflow Reset (STKOVF) The PCON register bits are shown in Register 6-2.
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PIC16(L)F1512/3 TABLE 6-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BORCON SBOREN BORFS — — — — — BORRDY 61 PCON STKOVF STKUNF — RWDT RMCLR RI POR BOR 65 STATUS — — — TO PD Z DC C 19 WDTCON — — SWDTEN 87 WDTPS<4:0> Legend: — = unimplemented, reads as ‘0’. Shaded cells are not used by Resets.
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PIC16(L)F1512/3 7.0 INTERRUPTS The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode. This chapter contains the following information for Interrupts: • • • • • Operation Interrupt Latency Interrupts During Sleep INT Pin Automatic Context Saving Many peripherals produce interrupts. Refer to the corresponding chapters for details.
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PIC16(L)F1512/3 7.1 Operation 7.2 Interrupts are disabled upon any device Reset. They are enabled by setting the following bits: • GIE bit of the INTCON register • Interrupt Enable bit(s) for the specific interrupt event(s) • PEIE bit of the INTCON register (if the Interrupt Enable bit of the interrupt event is contained in the PIEx register) Interrupt Latency Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins.
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PIC16(L)F1512/3 FIGURE 7-2: INTERRUPT LATENCY OSC1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKOUT Interrupt Sampled during Q1 Interrupt GIE PC Execute PC-1 PC 1 Cycle Instruction at PC PC+1 0004h 0005h Inst(PC) NOP NOP Inst(0004h) PC+1/FSR ADDR New PC/ PC+1 0004h 0005h Inst(PC) NOP NOP Inst(0004h) FSR ADDR PC+1 PC+2 0004h 0005h INST(PC) NOP NOP NOP Inst(0004h) Inst(0005h) FSR ADDR PC+1 0004h 0005h INST(PC) NOP
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PIC16(L)F1512/3 FIGURE 7-3: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT (3) (4) INT pin (1) (1) INTF Interrupt Latency (2) (5) GIE INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: PC Inst (PC) Inst (PC – 1) PC + 1 Inst (PC + 1) PC + 1 — Dummy Cycle Inst (PC) 0004h 0005h Inst (0004h) Inst (0005h) Dummy Cycle Inst (0004h) INTF flag is sampled here (every Q1).
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PIC16(L)F1512/3 7.3 Interrupts During Sleep Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction.
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PIC16(L)F1512/3 7.6 Interrupt Control Registers 7.6.1 Note: INTCON REGISTER The INTCON register is a readable and writable register that contains the various enable and flag bits for TMR0 register overflow, interrupt-on-change and external INT pin interrupts. REGISTER 7-1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register.
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PIC16(L)F1512/3 7.6.2 PIE1 REGISTER The PIE1 register contains the interrupt enable bits, as shown in Register 7-2. REGISTER 7-2: Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
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PIC16(L)F1512/3 7.6.3 PIE2 REGISTER The PIE2 register contains the interrupt enable bits, as shown in Register 7-3. REGISTER 7-3: Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
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PIC16(L)F1512/3 7.6.4 PIR1 REGISTER The PIR1 register contains the interrupt flag bits, as shown in Register 7-4. REGISTER 7-4: Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
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PIC16(L)F1512/3 7.6.5 PIR2 REGISTER The PIR2 register contains the interrupt flag bits, as shown in Register 7-5. REGISTER 7-5: Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
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PIC16(L)F1512/3 TABLE 7-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Bit 7 INTCON Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 TMR0IF Bit 1 Bit 0 INTF IOCIF Register on Page GIE PEIE TMR0IE INTE IOCIE WPUEN INTEDG TMR0CS TMR0SE PSA PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 73 PIE2 OSFIE — — — BCLIE — — CCP2IE 74 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 75 PIR2 OSFIF — — — BCLIF — — CCP2IF 76 OPTION_REG Legend: PS<2:0> 7
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PIC16(L)F1512/3 NOTES: DS41624B-page 78 Preliminary  2012 Microchip Technology Inc.
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PIC16(L)F1512/3 8.0 POWER-DOWN MODE (SLEEP) 8.1 Wake-up from Sleep The Power-Down mode is entered by executing a SLEEP instruction. The device can wake-up from Sleep through one of the following events: Upon entering Sleep mode, the following conditions exist: 1. 2. 3. 4. 5. 6. 1. 2. 3. 4. 5. 6. 7. 8. 9. WDT will be cleared but keeps running, if enabled for operation during Sleep. PD bit of the STATUS register is cleared. TO bit of the STATUS register is set. CPU clock is disabled.
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PIC16(L)F1512/3 8.1.
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PIC16(L)F1512/3 8.2 Low-Power Sleep Mode 8.2.2 Some peripherals that can operate in Sleep mode will not operate properly with the Low-Power Sleep mode selected. The LDO will remain in the Normal Power mode when those peripherals are enabled. The LowPower Sleep mode is intended for use with these peripherals: The PIC16F1512/3 device contains an internal Low Dropout (LDO) voltage regulator, which allows the device I/O pins to operate at voltages up to 5.
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PIC16(L)F1512/3 TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 72 IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 123 IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 123 IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 123 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 73 IO
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PIC16(L)F1512/3 9.0 LOW DROPOUT (LDO) VOLTAGE REGULATOR The PIC16F1512/3 has an internal Low Dropout Regulator (LDO) which provides operation above 3.6V. The LDO regulates a voltage for the internal device logic while permitting the VDD and I/O pins to operate at a higher voltage. There is no user enable/disable control available for the LDO, it is always active. The PIC16LF1512/3 operates at a maximum VDD of 3.6V and does not incorporate an LDO.
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PIC16(L)F1512/3 NOTES: DS41624B-page 84 Preliminary  2012 Microchip Technology Inc.
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PIC16(L)F1512/3 10.0 WATCHDOG TIMER (WDT) The Watchdog Timer is a system timer that generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The Watchdog Timer is typically used to recover the system from unexpected events.
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PIC16(L)F1512/3 10.1 Independent Clock Source 10.3 The WDT derives its time base from the 31 kHz LFINTOSC internal oscillator. Time intervals in this chapter are based on a nominal interval of 1 ms. See Section 25.0 “Electrical Specifications” for the LFINTOSC tolerances. 10.2 The Watchdog Timer module has four operating modes controlled by the WDTE<1:0> bits in Configuration Words. See Table 10-1. 10.2.
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PIC16(L)F1512/3 10.
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PIC16(L)F1512/3 TABLE 10-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER Bit 7 Bit 6 OSCCON — STATUS — — WDTCON — — Legend: CONFIG1 Legend: Bit 4 Bit 3 IRCF<3:0> — Bit 2 — TO PD Bit 1 Bit 0 SCS<1:0> Z DC WDTPS<4:0> Register on Page 56 C 19 SWDTEN 87 x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Watchdog Timer.
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PIC16(L)F1512/3 11.0 FLASH PROGRAM MEMORY CONTROL 11.1.1 The Flash program memory is readable and writable during normal operation over the full VDD range. Program memory is indirectly addressed using Special Function Registers (SFRs).
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PIC16(L)F1512/3 TABLE 11-1: Device FLASH MEMORY ORGANIZATION BY DEVICE Row Erase (words) Write Latches (words) 32 32 FIGURE 11-1: PIC16(L)F1516 PIC16(L)F1517 PIC16(L)F1518 READING THE FLASH PROGRAM MEMORY To read a program memory location, the user must: 1. 2. 3. Write the desired address to the PMADRH:PMADRL register pair. Clear the CFGS bit of the PMCON1 register. Then, set control bit RD of the PMCON1 register.
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PIC16(L)F1512/3 FIGURE 11-2: FLASH PROGRAM MEMORY READ CYCLE EXECUTION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC Flash ADDR Flash Data PC + 1 INSTR (PC) INSTR(PC - 1) executed here PC +3 PC+3 PMADRH,PMADRL INSTR (PC + 1) BSF PMCON1,RD executed here PMDATH,PMDATL INSTR(PC + 1) instruction ignored Forced NOP executed here PC + 4 INSTR (PC + 3) INSTR(PC + 2) instruction ignored Forced NOP executed here PC + 5 INSTR (PC + 4) INSTR(PC + 3) executed here INSTR
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PIC16(L)F1512/3 11.2.2 FLASH MEMORY UNLOCK SEQUENCE FIGURE 11-3: The unlock sequence is a mechanism that protects the Flash program memory from unintended self-write programming or erasing.
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PIC16(L)F1512/3 11.2.3 ERASING FLASH PROGRAM MEMORY FIGURE 11-4: While executing code, program memory can only be erased by rows. To erase a row: 1. 2. 3. 4. 5. Load the PMADRH:PMADRL register pair with any address within the row to be erased. Clear the CFGS bit of the PMCON1 register. Set the FREE and WREN bits of the PMCON1 register. Write 55h, then AAh, to PMCON2 (Flash programming unlock sequence). Set control bit WR of the PMCON1 register to begin the erase operation. See Example 11-2.
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PIC16(L)F1512/3 EXAMPLE 11-2: ERASING ONE ROW OF PROGRAM MEMORY Required Sequence ; This row erase routine assumes the following: ; 1. A valid address within the erase row is loaded in ADDRH:ADDRL ; 2.
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PIC16(L)F1512/3 11.2.4 WRITING TO FLASH PROGRAM MEMORY Program memory is programmed using the following steps: 1. 2. 3. 4. Load the address in PMADRH:PMADRL of the row to be programmed. Load each write latch with data. Initiate a programming operation. Repeat steps 1 through 3 until all data is written. The following steps should be completed to load the write latches and program a row of program memory. These steps are divided into two parts.
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7 BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES 6 0 7 5 4 PMADRH - r9 r8 r7 r6 r5 7 0 PMADRL r4 r3 r2 r1 r0 c4 c3 c2 c1 c0 5 - 0 7 PMDATH 6 0 PMDATL 8 14 10 Program Memory Write Latches 5 14 Write Latch #0 00h PMADRL<4:0> Preliminary 14 CFGS = 0  2012 Microchip Technology Inc.
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PIC16(L)F1512/3 FIGURE 11-6: FLASH PROGRAM MEMORY WRITE FLOWCHART Start Write Operation Determine the number of words to be written into the Program or Configuration Memory. The number of words cannot exceed the number of words per row. (word_cnt) Disable Interrupts (GIE = 0) Select Program or Config.
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PIC16(L)F1512/3 EXAMPLE 11-3: ; ; ; ; ; ; ; WRITING TO FLASH PROGRAM MEMORY This write routine assumes the following: 1. 64 bytes of data are loaded, starting at the address in DATA_ADDR 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR, stored in little endian format 3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL 4.
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PIC16(L)F1512/3 11.3 Modifying Flash Program Memory FIGURE 11-7: When modifying existing data in a program memory row, and data within that row must be preserved, it must first be read and saved in a RAM image. Program memory is modified using the following steps: 1. 2. 3. 4. 5. 6. 7. Load the starting address of the row to be modified. Read the existing data from the row into a RAM image. Modify the RAM image to contain the new data to be written into program memory.
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PIC16(L)F1512/3 11.4 User ID, Device ID and Configuration Word Access Instead of accessing program memory, the User ID’s, Device ID/Revision ID and Configuration Words can be accessed when CFGS = 1 in the PMCON1 register. This is the region that would be pointed to by PC<15> = 1, but not all addresses are accessible. Different access may exist for reads and writes. Refer to Table 11-2.
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PIC16(L)F1512/3 11.5 Write Verify It is considered good programming practice to verify that program memory writes agree with the intended value. Since program memory is stored as a full page then the stored program memory contents are compared with the intended data stored in RAM after the last write is complete. FIGURE 11-8: FLASH PROGRAM MEMORY VERIFY FLOWCHART Start Verify Operation This routine assumes that the last row of data written was from an image saved in RAM.
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PIC16(L)F1512/3 11.
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PIC16(L)F1512/3 REGISTER 11-5: PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER U-1(1) R/W-0/0 R/W-0/0 R/W/HC-0/0 R/W/HC-x/q(2) R/W-0/0 R/S/HC-0/0 R/S/HC-0/0 — CFGS LWLO FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 Unimplemented: Read as ‘1’ bit 6
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PIC16(L)F1512/3 REGISTER 11-6: W-0/0 PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 Program Memory Control Register 2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Flash Memory Unlock Pattern bits To unlock writes, a 55h must be written first, followed by an AAh, before
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PIC16(L)F1512/3 12.0 I/O PORTS FIGURE 12-1: GENERIC I/O PORT OPERATION Each port has three standard registers for its operation. These registers are: • TRISx registers (data direction) • PORTx registers (reads the levels on the pins of the device) • LATx registers (output latch) Read LATx D Some ports may have one or more of the following additional registers.
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PIC16(L)F1512/3 12.1 Alternate Pin Function The Alternate Pin Function Control (APFCON) register is used to steer specific peripheral input and output functions between different pins. The APFCON register is shown in Register 12-1. For this device family, the following functions can be moved between different pins. • SS (Slave Select) • CCP2 These bits have no effect on the values of any TRIS register. PORT and TRIS overrides will be routed to the correct pin. The unselected pin will be unaffected.
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PIC16(L)F1512/3 12.2 PORTA Registers 12.2.2 PORTA is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 12-3). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). Example 12-1 shows how to initialize PORTA.
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PIC16(L)F1512/3 REGISTER 12-2: PORTA: PORTA REGISTER R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared RA<7:0>: PORTA I/O Value bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL bit 7-0 Note 1: Writes to PORTA are
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PIC16(L)F1512/3 REGISTER 12-4: LATA: PORTA DATA LATCH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared LATA<7:0>: PORTA Output Latch Value bits(1) bit 7-0 Note 1: Writes to PORTA are actuall
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PIC16(L)F1512/3 TABLE 12-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Register on Page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ANSELA — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 109 APFCON — — — — — — SSSEL CCP2SEL 106 LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 109 WPUEN INTEDG TMR0CS TMR0SE PSA PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 108 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 108 LATA OPTION_REG Legend: CONFIG
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PIC16(L)F1512/3 12.3 PORTB Registers 12.3.2 PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB (Register 12-7). Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin).
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PIC16(L)F1512/3 REGISTER 12-6: PORTB: PORTB REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared RB<7:0>: PORTB General Purpose I/O Pin bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL bit 7-0 Note 1: Write
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PIC16(L)F1512/3 REGISTER 12-9: ANSELB: PORTB ANALOG SELECT REGISTER U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 ANSB<5:0>: Analog Select between Analog or Digital F
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PIC16(L)F1512/3 12.4 PORTC Registers 12.4.2 PORTC is an 8-bit wide bidirectional port. The corresponding data direction register is TRISC (Register 12-12). Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin).
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PIC16(L)F1512/3 REGISTER 12-11: PORTC: PORTC REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared RC<7:0>: PORTC General Purpose I/O Pin bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL bit 7-0 Note 1: Writes
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PIC16(L)F1512/3 REGISTER 12-14: ANSELC: PORTC ANALOG SELECT REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 U-0 U-0 ANSC7 ANSC6 ANSC3 ANSC3 ANSC3 ANSC2 — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 ANSC<7:0>: Analog Select between Analog or Digital Function on pins RC<7:0>, respectively 0
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PIC16(L)F1512/3 12.5 PORTE Registers 12.5.1 PORTE is a 4-bit wide, bidirectional port. The corresponding data direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin).
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PIC16(L)F1512/3 REGISTER 12-15: PORTE: PORTE REGISTER U-0 U-0 — — U-0 — U-0 R-x/x U-0 U-0 U-0 — RE3 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 RE<3>: PORTE I/O Value bit (RE3 is read-only) bit 2-0 Unimplemented: Read as ‘0’ REGISTER 12-16: TRISE: PORTE TRI
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PIC16(L)F1512/3 REGISTER 12-17: WPUE: WEAK PULL-UP PORTE REGISTER U-0 U-0 U-0 U-0 R/W-1/1 U-0 U-0 U-0 — — — — WPUE3 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 WPUE: Weak Pull-up Register bit 1 = Pull-up enabled 0 = Pull-up disabled bit 2-0 Unimplemented: R
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PIC16(L)F1512/3 NOTES: DS41624B-page 120 Preliminary  2012 Microchip Technology Inc.
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PIC16(L)F1512/3 13.0 INTERRUPT-ON-CHANGE 13.3 The PORTB pins can be configured to operate as Interrupt-On-Change (IOC) pins. An interrupt can be generated by detecting a signal that has either a rising edge or a falling edge. Any individual PORTB pin, or combination of PORTB pins, can be configured to generate an interrupt.
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PIC16(L)F1512/3 FIGURE 13-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM IOCBNx D Q4Q1 Q CK edge detect R RBx IOCBPx D data bus = 0 or 1 Q write IOCBFx CK D S Q to data bus IOCBFx CK IOCIE R Q2 from all other IOCBFx individual pin detectors Q1 Q3 Q4 Q4Q1 DS41624B-page 122 Q1 Q1 Q2 Q2 Q2 Q3 Q4 Q4Q1 IOC interrupt to CPU core Q3 Q4 Q4 Q4Q1 Preliminary Q4Q1  2012 Microchip Technology Inc.
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PIC16(L)F1512/3 13.
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PIC16(L)F1512/3 TABLE 13-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 109 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 72 Name IOCBF IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 123 IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 123 IOCBP IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF
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PIC16(L)F1512/3 14.0 FIXED VOLTAGE REFERENCE (FVR) 14.1 Independent Gain Amplifiers The output of the FVR supplied to the ADC module is routed through a programmable gain amplifier. The amplifier can be configured to amplify the reference voltage by 1x, 2x or 4x, to produce the three possible voltage levels. The Fixed Voltage Reference, or FVR, is a stable voltage reference, independent of VDD, with 1.024V, 2.048V or 4.096V selectable output levels.
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PIC16(L)F1512/3 14.
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PIC16(L)F1512/3 15.0 TEMPERATURE INDICATOR MODULE FIGURE 15-1: This family of devices is equipped with a temperature circuit designed to measure the operating temperature of the silicon die. The circuit’s range of operating temperature falls between -40°C and +85°C. The output is a voltage that is proportional to the device temperature. The output of the temperature indicator is internally connected to the device ADC.
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PIC16(L)F1512/3 15.4 ADC Acquisition Time To ensure accurate temperature measurements, the user must wait at least 200 s after the ADC input multiplexer is connected to the temperature indicator output before the conversion is performed. In addition, the user must wait 200 s between sequential conversions of the temperature indicator output.
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PIC16(L)F1512/3 16.0 Note: ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE This section of the ADC chapter discusses legacy operation. If new Capacitive Voltage Divider (CVD) features are needed, refer to Section 16.5 “Capacitive Voltage Divider (CVD)” for more information. The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit.
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PIC16(L)F1512/3 FIGURE 16-1: ADC BLOCK DIAGRAM VDD ADPREF = 0x ADPREF = 11 FVR VREF+ AN0 00000 AN1 00001 AN2 00010 VREF+/AN3 00011 AN4 00100 Reserved 00101 Reserved 00110 Reserved 00111 AN8 01000 AN9 01001 AN10 01010 AN11 01011 AN12 01100 AN13 01101 AN14 01110 AN15 01111 AN16 10000 AN17 10001 AN18 10010 AN19 10011 Reserved 10100 Reserved 11001 VREFH (ADC positive reference) 11010 VREFL (ADC negative reference) 11011 Reserved Temp Indicator 11101 Reserved
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PIC16(L)F1512/3 16.1 ADC Configuration 16.1.4 When configuring and using the ADC the following functions must be considered: • • • • • • Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Result formatting 16.1.1 The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits. Refer to Section 12.
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PIC16(L)F1512/3 TABLE 16-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES ADC Clock Period (TAD) Device Frequency (FOSC) ADC Clock Source ADCS<2:0> 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz Fosc/2 000 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s 100 200 ns (2) (2) (2) 1.0 s 4.0 s 400 ns (2) 1.0 s 2.0 s 8.0 s(3) Fosc/4 250 ns (2) 0.5 s 500 ns Fosc/8 001 Fosc/16 101 800 ns 1.0 s 2.0 s 4.0 s 16.0 s(3) Fosc/32 010 1.6 s 2.0 s 4.0 s 8.0 s(3) 32.
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PIC16(L)F1512/3 16.1.5 INTERRUPTS 16.1.6 The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. RESULT FORMATTING The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON1 register controls the output format.
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PIC16(L)F1512/3 16.2 16.2.1 ADC Operation 16.2.4 STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a ‘1’. Setting the GO/ DONE bit of the ADCON0 register to a ‘1’ will start the Analog-to-Digital conversion. Note: 16.2.2 The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 16.2.6 “A/D Conversion Procedure”.
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PIC16(L)F1512/3 16.2.6 A/D CONVERSION PROCEDURE EXAMPLE 16-1: This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. 2. 3. 4. 5. 6. 7. 8.
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PIC16(L)F1512/3 16.3 ADC Register Definitions The following registers are used to control the operation of the ADC.
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PIC16(L)F1512/3 REGISTER 16-2: R/W-0/0 ADCON1: A/D CONTROL REGISTER 1 R/W-0/0 ADFM R/W-0/0 R/W-0/0 ADCS<2:0> U-0 U-0 — — R/W-0/0 R/W-0/0 ADPREF<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: A/D Result Format Select bit 1 = Right justified.
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PIC16(L)F1512/3 REGISTER 16-3: R/W-x/u ADRES0H: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ADRES<9:2>: ADC Result Register bits Upper 8 bits of 10-bit conversion result REGISTER 16-4: R/W-x/u A
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PIC16(L)F1512/3 REGISTER 16-5: ADRES0H: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — — — — — R/W-x/u R/W-x/u ADRES<9:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Reserved: Do not use.
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PIC16(L)F1512/3 16.4 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 16-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), refer to Figure 16-4.
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PIC16(L)F1512/3 FIGURE 16-4: ANALOG INPUT MODEL VDD Analog Input pin Rs VT  0.6V CPIN 5 pF VA RIC  1k Sampling Switch SS Rss I LEAKAGE(1) VT  0.
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PIC16(L)F1512/3 TABLE 16-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH ADC Bit 7 ADCON0 — ADCON1 ADFM Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 — — CHS<4:0> ADCS<2:0> ADRES0H A/D Result Register High ADRES0L A/D Result Register Low Bit 1 Bit 0 GO/DONE ADON ADPREF<1:0> 160, 139 ANSELA — — ANSA5 — ANSA3 ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — — — ANSELC CCP2CON FVRCON 153 154 160, 139 ANSA2 CCP1CON Register on Page DC1B<1:
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PIC16(L)F1512/3 16.5 Capacitive Voltage Divider (CVD) 16.5.1 ADC REGISTER MAPPING The ADC module with Capacitive Voltage Divider (CVD) is an enhanced version of the standard ADC module as stated in Section 16.0 “Analog-to-Digital Converter (ADC) Module” through Section 16.3 “ADC Register Definitions” and is backward compatible with the other devices in this family. Control of the standard ADC module uses Bank 1 registers, see Table 16-4.
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PIC16(L)F1512/3 TABLE 16-5: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES ADC Clock Period (TAD) Device Frequency (FOSC) ADC Clock Source ADCS<2:0> 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz Fosc/2 000 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s 100 200 ns (2) (2) (2) 1.0 s 4.0 s 400 ns (2) 1.0 s 2.0 s 8.0 s(3) Fosc/4 250 ns (2) 0.5 s 500 ns Fosc/8 001 Fosc/16 101 800 ns 1.0 s 2.0 s 4.0 s 16.0 s(3) Fosc/32 010 1.6 s 2.0 s 4.0 s 8.0 s(3) 32.
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PIC16(L)F1512/3 16.5.3 RESULT FORMATTING The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the AADCON1 register controls the output format. Figure 16-7 shows the two output formats. FIGURE 16-7: 10-BIT A/D CONVERSION RESULT FORMAT AADRES0H (ADFM = 0) AADRES0L MSB LSB bit 7 bit 0 bit 7 10-bit A/D Result (ADFM = 1) bit 0 Unimplemented: Read as ‘0’ MSB bit 7 LSB bit 0 Unimplemented: Read as ‘0’  2012 Microchip Technology Inc.
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PIC16(L)F1512/3 16.6 16.6.1 Automated Capacitive Voltage Divider 16.6.4 CONVERSION SEQUENCE The conversion sequence can be expanded into three stages; pre-charge time, acquisition time, and conversion. See Figure 16-6 for basic information on the timing of these stages. 16.6.2 PRE-CHARGE TIMER The pre-charge stage is an optional 1-127 instruction cycle time used to put the external ADC channel and the internal sample and hold capacitor (CHOLD) into preconditioned states.
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DOUBLE SAMPLE CONVERSION SEQUENCE (ADDSEN = 1, ADIPEN = 1, GUARD-RING, GRDPOL = 1) Pre-Charge Acquisition AADPRE[6:0] AADACQ[6:0] PIC16(L)F1512/3 DS41624B-page 147 FIGURE 16-8: Pre-Charge Acquisition AADPRE[6:0] AADACQ[6:0] Conversion Clock 1-127 TINST 1-127 TINST (1) TAD (1) 10’h000 AADRESxL/H<9:0> TPRE TACQ 2INST 9th 8th 7th 6th 5th 4th 3rd 2nd 1st TCONV First result written to AADRES0L/H 1-127 TINST (1) 1-127 TINST (1) 10’h000 First result ready TPRE TACQ 9th 8th 7th 6th 5th 4th 3rd
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 2012 Microchip Technology Inc.
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DOUBLE SAMPLE CONVERSION SEQUENCE (ADDSEN = 1, ADIPEN = 0, GUARD-RING AND GRDPOL = 1) Pre-Charge Acquisition AADPRE[6:0] AADACQ[6:0] PIC16(L)F1512/3 DS41624B-page 149 FIGURE 16-10: Pre-Charge Acquisition AADPRE[6:0] AADACQ[6:0] Conversion Clock 1-127 TINST 1-127 TINST (1) 10’h000 AADRESxL/H<9:0> TPRE TACQ 1-127 T 2INST (1) INST 1-127 TINST TAD (1) (1) 9th 8th 7th 6th 5th 4th 3rd 2nd 1st TCONV First result written to AADRES0L/H 10’h000 First result ready TPRE TACQ ‘1’ Out Digital Analog
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PIC16(L)F1512/3 16.6.8 GUARD RING OUTPUTS Guard ring drive is a pair of digital outputs from the ADC module. This function is enabled by the GRDAOE and GRDBOE bits of the AADGRD register. Polarity of the output is controlled by the GRDPOL bit. The guard ring outputs of the ADC are active at all times. The outputs are initialized at the start of the precharge stage to match the polarity of the GRDPOL bit. The guard output signal changes polarity at the start of the acquisition stage.
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PIC16(L)F1512/3 FIGURE 16-12: A/D CONNECTION BLOCK DIAGRAM ADOUT Pad (Uses ADC MUX) ADOUT ADOEN(1) VDD ADIPPOL = 1 ADC Conversion Bus ANx ANx Pads ADIPPOL = 0 VGND ADDCAP<2:0> Additional Sample and Hold Cap VGND VGND VGND Note 1: ADOEN or ADOLEN for PIC16(L)F1512/3 devices.  2012 Microchip Technology Inc.
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PIC16(L)F1512/3 16.6.10 ANALOG BUS VISIBILITY 9. The ADOEN and ADOLEN bits of the AADCON3 register can be used to connect the ADC conversion bus to the ADOUT pin. This connection can be used to monitor the state and behavior of the internal analog bus. The ADOEN bit provides the connection via a standard channel passgate. The ADLOEN bit provides a lower impedance connection. Both bits can be enabled to provide the lowest impedance connection between the internal ADC analog bus and the ADOUT pin.
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PIC16(L)F1512/3 16.
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PIC16(L)F1512/3 REGISTER 16-8: R/W-0/0 AADCON1: A/D CONTROL REGISTER 1(1) R/W-0/0 ADFM R/W-0/0 R/W-0/0 ADCS<2:0> U-0 U-0 — — R/W-0/0 R/W-0/0 ADPREF<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: A/D Result Format Select bit 1 = Right justified.
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PIC16(L)F1512/3 REGISTER 16-9: U-0 AADCON2: A/D CONTROL REGISTER 2 R/W-0/0 — R/W-0/0 R/W-0/0 TRIGSEL<2:0> U-0 U-0 U-0 U-0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-4 TRIGSEL<2:0>: ADC Special Event Trigger Source Selection bits 111 = Reserved.
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PIC16(L)F1512/3 REGISTER 16-10: AADCON3: A/D CONTROL REGISTER 3 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 ADEPPOL ADIPPOL ADOLEN ADOEN ADOOEN — ADIPEN ADDSEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADEPPOL: External Pre-charge Polarity bit(1) 1 = Selected channel is shorted to V
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PIC16(L)F1512/3 REGISTER 16-11: AADSTAT: A/D STATUS REGISTER U-0 U-0 U-0 U-0 U-0 R/W-0/0 — — — — — ADCONV R/W-0/0 R/W-0/0 ADSTG<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2 ADCONV: A/D Conversion Status bit 1 = Indicates A/D in Conversion Sequence for AADRES1H:
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PIC16(L)F1512/3 REGISTER 16-13: AADACQ: A/D ACQUISITION TIME CONTROL REGISTER U-0 R/W-0/0 R/W-0/0 R/W-0/0 — R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ADACQ<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-0 ADACQ<6:0>: Acquisition/Charge Share Time Select bits(1) 111 1111 = Acquisi
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PIC16(L)F1512/3 REGISTER 16-15: AADCAP: A/D ADDITIONAL SAMPLE CAPACITOR SELECTION REGISTER U-0 U-0 U-0 U-0 U-0 — R/W-0/0 R/W-0/0 R/W-0/0 ADDCAP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 ADDCAP: ADC Additional Sample Capacitor Selection bits 111 = Nominal additi
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PIC16(L)F1512/3 REGISTER 16-16: AADRESxH: ADC RESULT REGISTER MSB ADFM = 0(1) R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRESx<9:2> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 AD<9:2>: Most Significant A/D results Note 1: See Section 16.5.
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PIC16(L)F1512/3 REGISTER 16-18: AADRESxH: ADC RESULT REGISTER MSB ADFM = 1(1) U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — R/W-x/u R/W-x/u ADRESx<9:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Reserved: Do not use. bit 1-0 AD<9:8>: Most Significant A/D results Note 1: See Section 16.5.
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PIC16(L)F1512/3 TABLE 16-6: Name SUMMARY OF REGISTERS ASSOCIATED WITH ADC Bit 7 Bit 6 Bit 5 — — AADCAP — AADCON0 — Bit 4 Bit 3 — — Bit 2 Bit 1 Bit 0 Register on Page ADON 153 ADDCAP<2:0> CHS<4:0> GO/DONE 159 AADCON1 ADFM ADCS<2:0> — — AADCON2 — TRIGSEL<2:0> — — — — 155 AADCON3 ADEPPOL ADIPPOL ADOLEN ADOEN ADOOEN — ADIPEN ADDSEN 156 AADGRD GRDBOE GRDAOE GRDPOL — — — — — 158 — AADPRE ADPREF<1:0> ADPRE<6:0> 154 157 AADRES0H A/D Result 0 Register H
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PIC16(L)F1512/3 17.0 TIMER0 MODULE 17.1.2 8-BIT COUNTER MODE The Timer0 module is an 8-bit timer/counter with the following features: In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin. • • • • • • 8-Bit Counter mode using the T0CKI pin is selected by setting the TMR0CS bit in the OPTION_REG register to ‘1’.
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PIC16(L)F1512/3 17.1.3 SOFTWARE PROGRAMMABLE PRESCALER A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION_REG register. Note: The Watchdog Timer (WDT) uses its own independent prescaler. There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION_REG register.
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PIC16(L)F1512/3 17.
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PIC16(L)F1512/3 NOTES: DS41624B-page 166 Preliminary  2012 Microchip Technology Inc.
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PIC16(L)F1512/3 18.0 TIMER1 MODULE WITH GATE CONTROL • • • • The Timer1 module is a 16-bit timer/counter with the following features: Figure 18-1 is a block diagram of the Timer1 module.
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PIC16(L)F1512/3 18.1 Timer1 Operation 18.2 The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. The TMR1CS<1:0> and T1OSCEN bits of the T1CON register are used to select the clock source for Timer1. Table 18-2 displays the clock source selections. 18.2.1 When used with an internal clock source, the module is a timer and increments on every instruction cycle.
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PIC16(L)F1512/3 18.3 Timer1 Prescaler Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L. 18.4 Secondary Oscillator The secondary oscillator circuit is enabled by setting the T1OSCEN bit of the T1CON register. The oscillator will continue to run during Sleep. 18.
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PIC16(L)F1512/3 18.6.2.1 T1G Pin Gate Operation 18.6.4 The T1G pin is one source for Timer1 gate control. It can be used to supply an external source to the Timer1 gate circuitry. 18.6.2.2 Timer0 Overflow Gate Operation When Timer0 increments from FFh to 00h, a low-to-high pulse will automatically be generated and internally supplied to the Timer1 gate circuitry. 18.6.2.
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PIC16(L)F1512/3 18.7 Timer1 Interrupt 18.9 The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: • • • • TMR1ON bit of the T1CON register TMR1IE bit of the PIE1 register PEIE bit of the INTCON register GIE bit of the INTCON register The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine.
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PIC16(L)F1512/3 FIGURE 18-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL t1g_in T1CKI T1GVAL Timer1 N FIGURE 18-4: N+1 N+2 N+3 N+4 TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM t1g_in T1CKI T1GVAL Timer1 DS41624B-page 172 N N+1 N+2 N+3 N+4 Preliminary N+5 N+6 N+7 N+8  2012 Microchip Technology Inc.
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PIC16(L)F1512/3 FIGURE 18-5: TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G t1g_in T1CKI T1GVAL Timer1 TMR1GIF N N+1 Set by hardware on falling edge of T1GVAL Cleared by software  2012 Microchip Technology Inc.
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PIC16(L)F1512/3 FIGURE 18-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G t1g_in T1CKI T1GVAL Timer1 TMR1GIF DS41624B-page 174 N Cleared by software N+1 N+2 N+3 N+4 Set by hardware on falling edge of T1GVAL Preliminary Cleared by software  2012 Microchip Technology Inc.
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PIC16(L)F1512/3 18.11 Timer1 Control Register The Timer1 Control register (T1CON), shown in Register 18-1, is used to control Timer1 and select the various features of the Timer1 module.
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PIC16(L)F1512/3 18.12 Timer1 Gate Control Register The Timer1 Gate Control register (T1GCON), shown in Register 18-2, is used to control Timer1 gate.
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PIC16(L)F1512/3 TABLE 18-5: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 113 CCP1CON — — Name DC1B<1:0> CCP1M<3:0> — — GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 72 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 73 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 75 CCP2CON INTCON DC2B<1:0> 246 CCP2M<3:0> TMR1H Holding Re
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PIC16(L)F1512/3 NOTES: DS41624B-page 178 Preliminary  2012 Microchip Technology Inc.
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PIC16(L)F1512/3 19.0 TIMER2 MODULE The Timer2 module incorporates the following features: • 8-bit Timer and Period registers (TMR2 and PR2, respectively) • Readable and writable (both registers) • Software programmable prescaler (1:1, 1:4, 1:16, and 1:64) • Software programmable postscaler (1:1 to 1:16) • Interrupt on TMR2 match with PR2, respectively • Optional use as the shift clock for the MSSP modules See Figure 19-1 for a block diagram of Timer2.
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PIC16(L)F1512/3 19.1 Timer2 Operation 19.3 The clock input to the Timer2 modules is the system instruction clock (FOSC/4). TMR2 increments from 00h on each clock edge. A 4-bit counter/prescaler on the clock input allows direct input, divide-by-4 and divide-by-16 prescale options. These options are selected by the prescaler control bits, T2CKPS<1:0> of the T2CON register. The value of TMR2 is compared to that of the Period register, PR2, on each clock cycle.
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PIC16(L)F1512/3 19.
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PIC16(L)F1512/3 TABLE 19-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page Name Bit 7 Bit 6 CCP1CON — — DC1B<1:0> CCP1M<3:0> 246 CCP2CON — — DC2B<1:0> CCP2M<3:0> 246 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 72 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 73 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 75 PR2 Timer2 Module Period Register INTCON T2CON TMR2 — 179* T2OUTPS<3:0> T
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PIC16(L)F1512/3 20.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE 20.1 Master SSP (MSSP) Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc.
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PIC16(L)F1512/3 The I2C interface supports the following modes and features: • • • • • • • • • • • • • Master mode Slave mode Byte NACKing (Slave mode) Limited Multi-master support 7-bit and 10-bit addressing Start and Stop interrupts Interrupt masking Clock stretching Bus collision detection General call address matching Address masking Address Hold and Data Hold modes Selectable SDA hold times Figure 20-2 is a block diagram of the I2C interface module in Master mode.
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PIC16(L)F1512/3 FIGURE 20-3: MSSP BLOCK DIAGRAM (I2C™ SLAVE MODE) Internal Data Bus Read Write SSPBUF Reg SCL Shift Clock SSPSR Reg SDA MSb LSb SSPMSK Reg Match Detect Addr Match SSPADD Reg Start and Stop bit Detect  2012 Microchip Technology Inc.
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PIC16(L)F1512/3 20.2 SPI Mode Overview The Serial Peripheral Interface (SPI) bus is a synchronous serial data communication bus that operates in Full Duplex mode. Devices communicate in a master/slave environment where the master device initiates the communication. A slave device is controlled through a Chip Select known as Slave Select.
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PIC16(L)F1512/3 FIGURE 20-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION SPI Master SCK SCK SDO SDI SDI SDO General I/O General I/O SS General I/O SCK SDI SDO SPI Slave #1 SPI Slave #2 SS SCK SDI SDO SPI Slave #3 SS 20.2.1 SPI MODE REGISTERS 20.2.2 The MSSP module has five registers for SPI mode operation.
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PIC16(L)F1512/3 The MSSP consists of a transmit/receive shift register (SSPSR) and a buffer register (SSPBUF). The SSPSR shifts the data in and out of the device, MSb first. The SSPBUF holds the data that was written to the SSPSR until the received data is ready. Once the eight bits of data have been received, that byte is moved to the SSPBUF register. Then, the Buffer Full Detect bit, BF of the SSPSTAT register, and the interrupt flag bit, SSPIF, are set.
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PIC16(L)F1512/3 20.2.3 SPI MASTER MODE The master can initiate the data transfer at any time because it controls the SCK line. The master determines when the slave (Processor 2, Figure 20-5) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input).
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PIC16(L)F1512/3 20.2.4 SPI SLAVE MODE 20.2.5 In Slave mode, the data is transmitted and received as external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCK pin. The Idle state is determined by the CKP bit of the SSPCON1 register.
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PIC16(L)F1512/3 FIGURE 20-7: SPI DAISY-CHAIN CONNECTION SPI Master SCK SCK SDO SDI SDI SPI Slave #1 SDO General I/O SS SCK SDI SPI Slave #2 SDO SS SCK SDI SPI Slave #3 SDO SS FIGURE 20-8: SLAVE SELECT SYNCHRONOUS WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF Shift register SSPSR and bit count are reset SSPBUF to SSPSR SDO bit 7 bit 6 bit 7 SDI bit 6 bit 0 bit 0 bit 7 bit 7 Input Sample SSPIF Interrupt Flag SSPSR to SSPBUF  2012 Microchip Technology In
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PIC16(L)F1512/3 FIGURE 20-9: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 0 bit 7 Input Sample SSPIF Interrupt Flag SSPSR to SSPBUF Write Collision detection active FIGURE 20-10: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b
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PIC16(L)F1512/3 20.2.6 SPI OPERATION IN SLEEP MODE In SPI Master mode, module clocks may be operating at a different speed than when in Full-Power mode; in the case of the Sleep mode, all clocks are halted. Special care must be taken by the user when the MSSP clock is much faster than the system clock. In Slave mode, when MSSP interrupts are enabled, after the master completes sending data, an MSSP interrupt will wake the controller from Sleep.
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PIC16(L)F1512/3 20.3 I2C MODE OVERVIEW FIGURE 20-11: The Inter-Integrated Circuit Bus (I2C) is a multi-master serial data communication bus. Devices communicate in a master/slave environment where the master devices initiate the communication. A slave device is controlled through addressing. VDD SCL The I2C bus specifies two signal connections: • Serial Clock (SCL) • Serial Data (SDA) Figure 20-11 shows a typical connection between two processors configured as master and slave devices.
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PIC16(L)F1512/3 When one device is transmitting a logical one, or letting the line float, and a second device is transmitting a logical zero, or holding the line low, the first device can detect that the line is not a logical one. This detection, when used on the SCL line, is called clock stretching. Clock stretching gives slave devices a mechanism to control the flow of data. When this detection is used on the SDA line, it is called arbitration.
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PIC16(L)F1512/3 20.4 I2C MODE OPERATION TABLE 20-2: All MSSP I2C communication is byte oriented and shifted out MSb first. Six SFR registers and 2 interrupt flags interface the module with the PIC® microcontroller and user software. Two pins, SDA and SCL, are exercised by the module to communicate with other external I2C devices. 20.4.1 BYTE FORMAT All communication in I2C is done in 9-bit segments. A byte is sent from a master to a slave or vice-versa, followed by an Acknowledge bit sent back.
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PIC16(L)F1512/3 20.4.5 START CONDITION 20.4.7 2 The I C specification defines a Start condition as a transition of SDA from a high to a low state while SCL line is high. A Start condition is always generated by the master and signifies the transition of the bus from an Idle to an Active state. Figure 20-12 shows wave forms for Start and Stop conditions. A Restart is valid any time that a Stop would be valid.
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PIC16(L)F1512/3 20.4.9 20.5 ACKNOWLEDGE SEQUENCE The 9th SCL pulse for any transferred byte in I2C is dedicated as an Acknowledge. It allows receiving devices to respond back to the transmitter by pulling the SDA line low. The transmitter must release control of the line during this time to shift in the response. The Acknowledge (ACK) is an active-low signal, pulling the SDA line low indicated to the transmitter that the device has received the transmitted data and is ready to receive more.
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PIC16(L)F1512/3 20.5.2 SLAVE RECEPTION 20.5.2.2 When the R/W bit of a matching received address byte is clear, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register and Acknowledged. When the overflow condition exists for a received address, then not Acknowledge is given. An overflow condition is defined as either bit BF bit of the SSPSTAT register is set, or bit SSPOV bit of the SSPCON1 register is set.
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DS41624B-page 200 Preliminary SSPOV BF SSPIF S 1 A7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 9 ACK 1 D7 2 D6 4 D4 5 D3 6 D2 7 D1 SSPBUF is read Cleared by software 3 D5 Receiving Data 8 9 2 D6 First byte of data is available in SSPBUF 1 D0 ACK D7 4 D4 5 D3 6 D2 7 D1 SSPOV set because SSPBUF is still full. ACK is not sent.
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 2012 Microchip Technology Inc. Preliminary CKP SSPOV BF SSPIF 1 SCL S A7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 9 R/W=0 ACK SEN 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 CKP is written to ‘1’ in software, releasing SCL SSPBUF is read Cleared by software Clock is held low until CKP is set to ‘1’ 1 D7 Receive Data 9 ACK SEN 3 D5 4 D4 5 D3 First byte of data is available in SSPBUF 6 D2 7 D1 SSPOV set because SSPBUF is still full. ACK is not sent.
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DS41624B-page 202 Preliminary P S ACKTIM CKP ACKDT BF SSPIF S Receiving Address 1 3 5 6 7 8 ACK the received byte Slave software clears ACKDT to Address is read from SSBUF If AHEN = 1: SSPIF is set 4 ACKTIM set by hardware on 8th falling edge of SCL When AHEN=1: CKP is cleared by hardware and SCL is stretched 2 A7 A6 A5 A4 A3 A2 A1 Receiving Data 9 2 3 4 5 6 7 ACKTIM cleared by hardware in 9th rising edge of SCL When DHEN=1: CKP is cleared by hardware on 8th falling edge of
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PIC16(L)F1512/3 20.5.3 SLAVE TRANSMISSION 20.5.3.2 7-bit Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register, and an ACK pulse is sent by the slave on the ninth bit. A master device can transmit a read request to a slave, and then clock data out of the slave. The list below outlines what software for a slave will need to do to accomplish a standard transmission.
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PIC16(L)F1512/3 20.5.3.3 7-bit Transmission with Address Hold Enabled Setting the AHEN bit of the SSPCON3 register enables additional clock stretching and interrupt generation after the 8th falling edge of a received matching address. Once a matching address has been clocked in, CKP is cleared and the SSPIF interrupt is set. Figure 20-18 displays a standard waveform of a 7-bit Address Slave Transmission with AHEN enabled. 1. 2. Bus starts Idle.
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 2012 Microchip Technology Inc. Preliminary D/A R/W ACKTIM CKP ACKSTAT ACKDT BF SSPIF S Receiving Address 2 4 5 6 7 8 Slave clears ACKDT to ACK address ACKTIM is set on 8th falling edge of SCL 9 ACK When R/W = 1; CKP is always cleared after ACK R/W = 1 Received address is read from SSPBUF 3 When AHEN = 1; CKP is cleared by hardware after receiving matching address.
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PIC16(L)F1512/3 20.5.4 SLAVE MODE 10-BIT ADDRESS RECEPTION 20.5.5 This section describes a standard sequence of events for the MSSP module configured as an I2C slave in 10-bit Addressing mode. Figure 20-19 is used as a visual reference for this description. This is a step by step process of what must be done by slave software to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. Bus starts Idle.
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DS41624B-page 210 Preliminary ACKTIM CKP UA ACKDT BF 2 1 5 0 6 A9 7 A8 Set by hardware on 9th falling edge 4 1 ACKTIM is set by hardware on 8th falling edge of SCL If when AHEN = 1; on the 8th falling edge of SCL of an address byte, CKP is cleared Slave software clears ACKDT to ACK the received byte 3 1 8 R/W = 0 9 ACK UA 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 Update to SSPADD is not allowed until 9th falling edge of SCL SSPBUF can be read anytime before the next received byt
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PIC16(L)F1512/3 20.5.6 CLOCK STRETCHING 20.5.6.2 Clock stretching occurs when a device on the bus holds the SCL line low effectively pausing communication. The slave may stretch the clock to allow more time to handle data or prepare a response for the master device. A master device is not concerned with stretching as anytime it is active on the bus and not transferring data it is stretching. Any stretching done by a slave is invisible to the master software and handled by the hardware that generates SCL.
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PIC16(L)F1512/3 20.5.8 GENERAL CALL ADDRESS SUPPORT software can read SSPBUF Figure 20-23 shows a general sequence. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master device. The exception is the general call address which can address all devices. When this address is used, all devices should, in theory, respond with an Acknowledge. respond.
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PIC16(L)F1512/3 20.6 I2C MASTER MODE 20.6.1 Master mode is enabled by setting and clearing the appropriate SSPM bits in the SSPCON1 register and by setting the SSPEN bit. In Master mode, the SDA and SCK pins must be configured as inputs. The MSSP peripheral hardware will override the output driver TRIS controls when necessary to drive the pins low. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions.
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PIC16(L)F1512/3 20.6.2 CLOCK ARBITRATION Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, releases the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<7:0> and begins counting.
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PIC16(L)F1512/3 20.6.4 I2C MASTER MODE START CONDITION TIMING To initiate a Start condition, the user sets the Start Enable bit, SEN bit of the SSPCON2 register. If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<7:0> and starts its count. If SCL and SDA are both sampled high when the Baud Rate Generator times out (TBRG), the SDA pin is driven low.
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PIC16(L)F1512/3 20.6.5 I2C MASTER MODE REPEATED START CONDITION TIMING SSPCON2 register will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDA pin held low. As soon as a Start condition is detected on the SDA and SCL pins, the S bit of the SSPSTAT register will be set. The SSPIF bit will not be set until the Baud Rate Generator has timed out.
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PIC16(L)F1512/3 20.6.6.1 BF Status Flag In Transmit mode, the BF bit of the SSPSTAT register is set when the CPU writes to SSPBUF and is cleared when all 8 bits are shifted out. 20.6.6.2 WCOL Status Flag If the user writes the SSPBUF when a transmit is already in progress (i.e., SSPSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write does not occur). WCOL must be cleared by software before the next transmission. 20.6.6.
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PIC16(L)F1512/3 20.6.7 I2C MASTER MODE RECEPTION 20.6.7.4 Master mode reception is enabled by programming the Receive Enable bit, RCEN bit of the SSPCON2 register. Note: The MSSP module must be in an Idle state before the RCEN bit is set or the RCEN bit will be disregarded. The Baud Rate Generator begins counting and on each rollover, the state of the SCL pin changes (high-to-low/low-to-high) and data is shifted into the SSPSR.
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PIC16(L)F1512/3 20.6.8 ACKNOWLEDGE SEQUENCE TIMING 20.6.9 A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN bit of the SSPCON2 register. At the end of a receive/transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and counts down to ‘0’.
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PIC16(L)F1512/3 FIGURE 20-31: STOP CONDITION RECEIVE OR TRANSMIT MODE SCL = 1 for TBRG, followed by SDA = 1 for TBRG after SDA sampled high. P bit (SSPSTAT<4>) is set. Write to SSPCON2, set PEN PEN bit (SSPCON2<2>) is cleared by hardware and the SSPIF bit is set Falling edge of 9th clock TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period. 20.6.10 SLEEP OPERATION 20.6.
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PIC16(L)F1512/3 FIGURE 20-32: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCL = 0 SDA line pulled low by another source SDA released by master Sample SDA. While SCL is high, data does not match what is driven by the master. Bus collision has occurred. SDA SCL Set bus collision interrupt (BCLIF) BCLIF DS41624B-page 224 Preliminary  2012 Microchip Technology Inc.
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PIC16(L)F1512/3 20.6.13.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDA or SCL are sampled low at the beginning of the Start condition (Figure 20-32). SCL is sampled low before SDA is asserted low (Figure 20-33). During a Start condition, both the SDA and the SCL pins are monitored. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 20-34).
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PIC16(L)F1512/3 FIGURE 20-34: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF.
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PIC16(L)F1512/3 20.6.13.2 Bus Collision During a Repeated Start Condition If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, Figure 20-35). If SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time.
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PIC16(L)F1512/3 20.6.13.3 Bus Collision During a Stop Condition The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPADD and counts down to zero. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 20-37).
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PIC16(L)F1512/3 TABLE 20-3: SUMMARY OF REGISTERS ASSOCIATED WITH I2C™ OPERATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 72 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 73 PIE2 OSFIE — — — BCLIE — — CCP2IE 74 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 75 PIR2 OSFIF — — — BCLIF — — CCP2IF Name INTCON SSPADD ADD<7:0> SSPBUF Synchronous Serial Port Receiv
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PIC16(L)F1512/3 20.7 BAUD RATE GENERATOR The MSSP module has a Baud Rate Generator available for clock generation in both I2C and SPI Master modes. The Baud Rate Generator (BRG) reload value is placed in the SSPADD register (Register 20-6). When a write occurs to SSPBUF, the Baud Rate Generator will automatically begin counting down. Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state.
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PIC16(L)F1512/3 20.
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PIC16(L)F1512/3 REGISTER 20-2: SSPCON1: SSP CONTROL REGISTER 1 R/C/HS-0/0 R/C/HS-0/0 R/W-0/0 R/W-0/0 WCOL SSPOV SSPEN CKP R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SSPM<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared bit 7 WCOL: Write Collision Detect bit Master mode: 1
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PIC16(L)F1512/3 REGISTER 20-3: SSPCON2: SSP CONTROL REGISTER 2 R/W-0/0 R-0/0 R/W-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/W/HS-0/0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware S = User set bit 7 GCEN: General Call Enable bit (i
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PIC16(L)F1512/3 REGISTER 20-4: SSPCON3: SSP CONTROL REGISTER 3 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only)(3) 1 = Indicates the I2C bus is in
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PIC16(L)F1512/3 REGISTER 20-5: R/W-1/1 SSPMSK: SSP MASK REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 MSK<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 MSK<7:1>: Mask bits 1 = The received address bit n is compared to SSPADD to detect I2C address match 0 = The received address bit
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PIC16(L)F1512/3 NOTES: DS41624B-page 236 Preliminary  2012 Microchip Technology Inc.
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PIC16(L)F1512/3 21.0 CAPTURE/COMPARE/PWM MODULES The Capture/Compare/PWM module is a peripheral which allows the user to time and control different events, and to generate Pulse-Width Modulation (PWM) signals. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate Pulse-Width Modulated signals of varying frequency and duty cycle.
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PIC16(L)F1512/3 21.1 Capture Mode 21.1.2 The Capture mode function described in this section is available and identical for all CCP modules. Capture mode makes use of the 16-bit Timer1 resource. When an event occurs on the CCPx pin, the 16-bit CCPRxH:CCPRxL register pair captures and stores the 16-bit value of the TMR1H:TMR1L register pair, respectively.
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PIC16(L)F1512/3 21.1.5 CAPTURE DURING SLEEP Capture mode depends upon the Timer1 module for proper operation. There are two options for driving the Timer1 module in Capture mode. It can be driven by the instruction clock (FOSC/4), or by an external clock source. When Timer1 is clocked by FOSC/4, Timer1 will not increment during Sleep. When the device wakes from Sleep, Timer1 will continue from its previous state. Capture mode will operate during Sleep when Timer1 is clocked by an external clock source.
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PIC16(L)F1512/3 21.2 Compare Mode 21.2.2 The Compare mode function described in this section is available and identical for al CCP modules. Compare mode makes use of the 16-bit Timer1 resource. The 16-bit value of the CCPRxH:CCPRxL register pair is constantly compared against the 16-bit value of the TMR1H:TMR1L register pair. When a match occurs, one of the following events can occur: • • • • • In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode.
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PIC16(L)F1512/3 21.2.5 COMPARE DURING SLEEP The Compare mode is dependent upon the system clock (FOSC) for proper operation. Since FOSC is shut down during Sleep mode, the Compare mode will not function properly during Sleep. 21.2.6 ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register APFCON. To determine which pins can be moved and what their default locations are upon a Reset, see Section 12.
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PIC16(L)F1512/3 21.3 PWM Overview FIGURE 21-3: Pulse-Width Modulation (PWM) is a scheme that provides power to a load by switching quickly between fully on and fully off states. The PWM signal resembles a square wave where the high portion of the signal is considered the on state and the low portion of the signal is considered the off state. The high portion, also known as the pulse width, can vary in time and is defined in steps.
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PIC16(L)F1512/3 21.3.2 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for standard PWM operation: 1. 2. 3. 4. 5. 6. Disable the CCPx pin output driver by setting the associated TRIS bit. Load the PR2 register with the PWM period value. Configure the CCP module for the PWM mode by loading the CCPxCON register with the appropriate values. Load the CCPRxL register and the DCxBx bits of the CCPxCON register, with the PWM duty cycle value.
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PIC16(L)F1512/3 21.3.6 PWM RESOLUTION EQUATION 21-4: The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is 10 bits when PR2 is 255. The resolution is a function of the PR2 register value as shown by Equation 21-4.
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PIC16(L)F1512/3 21.3.7 OPERATION IN SLEEP MODE 21.3.10 In Sleep mode, the TMR2 register will not increment and the state of the module will not change. If the CCPx pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state. 21.3.8 CHANGES IN SYSTEM CLOCK FREQUENCY ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register APFCON.
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PIC16(L)F1512/3 21.
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PIC16(L)F1512/3 22.
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PIC16(L)F1512/3 FIGURE 22-2: EUSART RECEIVE BLOCK DIAGRAM SPEN CREN RX/DT pin Baud Rate Generator Data Recovery FOSC SPBRGH SPBRGL x4 x16 x64 SYNC 1 X 0 0 0 BRGH X 1 1 0 0 BRG16 X 1 0 1 0 (8) ••• 7 1 LSb 0 Start RX9 ÷n BRG16 Multiplier Stop RCIDL RSR Register MSb Pin Buffer and Control +1 OERR n FERR RX9D RCREG Register 8 FIFO Data Bus RCIF RCIE Interrupt The operation of the EUSART module is controlled through three registers: • Transmit Status and Control (TXSTA) •
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PIC16(L)F1512/3 22.1 EUSART Asynchronous Mode 22.1.1.2 The EUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a VOH mark state which represents a ‘1’ data bit, and a VOL space state which represents a ‘0’ data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission.
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PIC16(L)F1512/3 22.1.1.5 TSR Status 22.1.1.7 The TRMT bit of the TXSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied to this bit, so the user has to poll this bit to determine the TSR status. Note: 22.1.1.6 1. 2. 3.
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PIC16(L)F1512/3 FIGURE 22-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREG TX/CK pin Start bit bit 0 bit 1 Word 1 1 TCY TXIF bit (Transmit Buffer Reg. Empty Flag) bit 7/8 Stop bit Start bit Word 2 bit 0 1 TCY Word 1 Transmit Shift Reg. TRMT bit (Transmit Shift Reg. Empty Flag) Note: Word 2 Word 1 BRG Output (Shift Clock) Word 2 Transmit Shift Reg. This timing diagram shows two consecutive transmissions.
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PIC16(L)F1512/3 22.1.2 EUSART ASYNCHRONOUS RECEIVER 22.1.2.2 The Asynchronous mode is typically used in RS-232 systems. The receiver block diagram is shown in Figure 22-2. The data is received on the RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate.
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PIC16(L)F1512/3 22.1.2.4 Receive Framing Error 22.1.2.7 Each character in the receive FIFO buffer has a corresponding framing error Status bit. A framing error indicates that a Stop bit was not seen at the expected time. The framing error status is accessed via the FERR bit of the RCSTA register. The FERR bit represents the status of the top unread character in the receive FIFO. Therefore, the FERR bit must be read before reading the RCREG.
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PIC16(L)F1512/3 22.1.2.8 Asynchronous Reception Set-up: 22.1.2.9 1. Initialize the SPBRGH, SPBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 22.4 “EUSART Baud Rate Generator (BRG)”). 2. Clear the ANSEL bit for the RX pin (if applicable). 3. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. 4. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register.
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PIC16(L)F1512/3 TABLE 22-2: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 258 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 72 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 73 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 75 SPEN RX9 SREN OERR RX9D Name BAUDCON INTCON RCREG RCSTA EUSART Receive Data Register SPBRGL CRE
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PIC16(L)F1512/3 22.2 Clock Accuracy with Asynchronous Operation The factory calibrates the internal oscillator block output (INTOSC). However, the INTOSC frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. 22.3 The first (preferred) method uses the OSCTUNE register to adjust the INTOSC output.
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PIC16(L)F1512/3 RCSTA: RECEIVE STATUS AND CONTROL REGISTER(1) REGISTER 22-2: R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-x/x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK
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PIC16(L)F1512/3 REGISTER 22-3: BAUDCON: BAUD RATE CONTROL REGISTER R-0/0 R-1/1 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-b
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PIC16(L)F1512/3 22.4 EUSART Baud Rate Generator (BRG) EXAMPLE 22-1: The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit of the BAUDCON register selects 16-bit mode.
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PIC16(L)F1512/3 TABLE 22-3: BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula 0 8-bit/Asynchronous FOSC/[64 (n+1)] 0 1 8-bit/Asynchronous 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous 1 x 16-bit/Synchronous SYNC BRG16 BRGH 0 0 0 1 Legend: FOSC/[4 (n+1)] x = Don’t care, n = value of SPBRGH, SPBRGL register pair.
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PIC16(L)F1512/3 TABLE 22-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 20.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 18.432 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 16.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 — — — — — — — — — — — — 1200 1221 1.73 255 1200 0.00 239 1202 0.16 207 1200 0.00 143 2400 2404 0.16 129 2400 0.
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PIC16(L)F1512/3 TABLE 22-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 8.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 4.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 3.6864 MHz Actual Rate FOSC = 1.000 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 300 1200 — — — — — — — 1202 — 0.16 — 207 — 1200 — 0.00 — 191 300 1202 0.16 0.16 207 51 2400 2404 0.16 207 2404 0.
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PIC16(L)F1512/3 TABLE 22-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 1200 300.0 1200 0.00 -0.01 16665 4166 300.0 1200 0.00 0.00 15359 3839 300.0 1200.1 0.00 0.01 13332 3332 300.0 1200 0.00 0.00 9215 2303 2400 2400 0.02 2082 2400 0.00 1919 2399.5 -0.02 1666 2400 0.00 1151 9600 9597 -0.
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PIC16(L)F1512/3 22.4.1 AUTO-BAUD DETECT The EUSART module supports automatic detection and calibration of the baud rate. In the Auto-Baud Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RX signal, the RX signal is timing the BRG. The Baud Rate Generator is used to time the period of a received 55h (ASCII “U”) which is the Sync character for the LIN bus. The unique feature of this character is that it has five rising edges including the Stop bit edge.
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PIC16(L)F1512/3 22.4.2 AUTO-BAUD OVERFLOW 22.4.3.1 During the course of automatic baud detection, the ABDOVF bit of the BAUDCON register will be set if the baud rate counter overflows before the fifth rising edge is detected on the RX pin. The ABDOVF bit indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the SPBRGH:SPBRGL register pair. After the ABDOVF bit has been set, the counter continues to count until the fifth rising edge is detected on the RX pin.
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PIC16(L)F1512/3 FIGURE 22-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Auto Cleared Bit set by user WUE bit RX/DT Line RCIF Note 1: Cleared due to User Read of RCREG The EUSART remains in Idle while the WUE bit is set.
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PIC16(L)F1512/3 22.4.4 BREAK CHARACTER SEQUENCE The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. A Break character consists of a Start bit, followed by 12 ‘0’ bits and a Stop bit. To send a Break character, set the SENDB and TXEN bits of the TXSTA register. The Break character transmission is then initiated by a write to the TXREG. The value of data written to TXREG will be ignored and all ‘0’s will be transmitted.
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PIC16(L)F1512/3 22.5 EUSART Synchronous Mode 22.5.1.2 Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line.
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PIC16(L)F1512/3 FIGURE 22-10: SYNCHRONOUS TRANSMISSION RX/DT pin bit 0 bit 1 Word 1 bit 2 bit 7 bit 0 bit 1 Word 2 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit TXEN bit ‘1’ Note: ‘1’ Sync Master mode, SPBRGL = 0, continuous transmission of two 8-bit words.
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PIC16(L)F1512/3 22.5.1.5 Synchronous Master Reception 22.5.1.7 Data is received at the RX/DT pin. The RX/DT pin output driver is automatically disabled when the EUSART is configured for synchronous master receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCSTA register) or the Continuous Receive Enable bit (CREN of the RCSTA register).
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PIC16(L)F1512/3 FIGURE 22-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RCREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
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PIC16(L)F1512/3 22.5.2 SYNCHRONOUS SLAVE MODE The following bits are used to configure the EUSART for synchronous slave operation: • • • • • SYNC = 1 CSRC = 0 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 1. 2. 3. 4. Setting the SYNC bit of the TXSTA register configures the device for synchronous operation. Clearing the CSRC bit of the TXSTA register configures the device as a slave.
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PIC16(L)F1512/3 22.5.2.3 EUSART Synchronous Slave Reception 22.5.2.4 The operation of the Synchronous Master and Slave modes is identical (Section 22.5.1.5 “Synchronous Master Reception”), with the following exceptions: • Sleep • CREN bit is always set, therefore the receiver is never Idle • SREN bit, which is a “don’t care” in Slave mode 1. 2. 3. A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep.
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PIC16(L)F1512/3 22.6 EUSART Operation During Sleep The EUSART will remain active during Sleep only in the Synchronous Slave mode. All other modes require the system clock and therefore cannot generate the necessary signals to run the Transmit or Receive Shift registers during Sleep. Synchronous Slave mode uses an externally generated clock to run the Transmit and Receive Shift registers. 22.6.
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PIC16(L)F1512/3 23.0 IN-CIRCUIT SERIAL PROGRAMMING™ (ICSP™) 23.2 ICSP™ programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can be done after the assembly process allowing the device to be programmed with the most recent firmware or a custom firmware. Five pins are needed for ICSP™ programming: • ICSPCLK • ICSPDAT • MCLR/VPP • VDD • VSS In Program/Verify mode the program memory, user IDs and the Configuration Words are programmed through serial communications.
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PIC16(L)F1512/3 Another connector often found in use with the PICkit™ programmers is a standard 6-pin header with 0.1 inch spacing. Refer to Figure 23-2. FIGURE 23-2: PICkit™ PROGRAMMER STYLE CONNECTOR INTERFACE Pin 1 Indicator Pin Description* 1 2 3 4 5 6 1 = VPP/MCLR 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT 5 = ICSPCLK 6 = No Connect * DS41624B-page 276 The 6-pin header (0.100" spacing) accepts 0.025" square pins. Preliminary  2012 Microchip Technology Inc.
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PIC16(L)F1512/3 For additional interface recommendations, refer to your specific device programmer manual prior to PCB design. It is recommended that isolation devices be used to separate the programming pins from other circuitry. The type of isolation is highly dependent on the specific application and may include devices such as resistors, diodes, or even jumpers. See Figure 23-3 for more information.
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PIC16(L)F1512/3 NOTES: DS41624B-page 278 Preliminary  2012 Microchip Technology Inc.
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PIC16(L)F1512/3 24.0 INSTRUCTION SET SUMMARY 24.1 Read-Modify-Write Operations • Byte Oriented • Bit Oriented • Literal and Control Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction, or the destination designator ‘d’. A read operation is performed on a register even if the instruction writes to that register.
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PIC16(L)F1512/3 FIGURE 24-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 OPCODE d f (FILE #) 0 d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 OPCODE b (BIT #) f (FILE #) 0 b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE 8 7 0 k (literal) k = 8-bit immediate value CALL and GOTO instructions only 13 11 10 OPCODE 0 k (literal
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PIC16(L)F1512/3 TABLE 24-3: INSTRUCTION SET Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ADDWFC ANDWF ASRF LSLF LSRF CLRF CLRW COMF DECF INCF IORWF MOVF MOVWF RLF RRF SUBWF SUBWFB SWAPF XORWF f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d f, d Add W and f Add with Carry W and f AND W with f Arithmetic Right Shift Logical Left Shift Logical Right Shift Clear f Clear W Complemen
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PIC16(L)F1512/3 TABLE 24-3: INSTRUCTION SET (CONTINUED) Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes CONTROL OPERATIONS 2 2 2 2 2 2 2 2 BRA BRW CALL CALLW GOTO RETFIE RETLW RETURN k – k – k k k – Relative Branch Relative Branch with W Call Subroutine Call Subroutine with W Go to address Return from interrupt Return with literal in W Return from Subroutine CLRWDT NOP OPTION RESET SLEEP TRIS – – – – – f Clear Watchdog Timer No Operation Load OPTION_REG regi
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PIC16(L)F1512/3 24.2 Instruction Descriptions ADDFSR Add Literal to FSRn ANDLW AND literal with W Syntax: [ label ] ADDFSR FSRn, k Syntax: [ label ] ANDLW Operands: -32  k  31 n  [ 0, 1] Operands: 0  k  255 Operation: FSR(n) + k  FSR(n) Status Affected: None Description: The signed 6-bit literal ‘k’ is added to the contents of the FSRnH:FSRnL register pair. k Operation: (W) .AND.
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PIC16(L)F1512/3 BCF Bit Clear f Syntax: [ label ] BCF f,b BTFSC Bit Test f, Skip if Clear Syntax: [ label ] BTFSC f,b 0  f  127 0b7 Operands: 0  f  127 0b7 Operands: Operation: 0  (f) Operation: skip if (f) = 0 Status Affected: None Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared. Description: If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed.
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PIC16(L)F1512/3 CALL Call Subroutine CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0  k  2047 Operands: None Operation: (PC)+ 1 TOS, k  PC<10:0>, (PCLATH<6:3>)  PC<14:11> Operation: Status Affected: None 00h  WDT 0  WDT prescaler, 1  TO 1  PD Description: Call Subroutine. First, return address (PC + 1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH.
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PIC16(L)F1512/3 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0  f  127 d  [0,1] Operands: 0  f  127 d  [0,1] Operation: (f) - 1  (destination); skip if result = 0 Operation: (f) + 1  (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in the W register.
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PIC16(L)F1512/3 LSLF Logical Left Shift f {,d} MOVF Move f Syntax: [ label ] LSLF Syntax: [ label ] Operands: 0  f  127 d [0,1] Operands: 0  f  127 d  [0,1] Operation: (f<7>)  C (f<6:0>)  dest<7:1> 0  dest<0> Operation: (f)  (dest) Status Affected: C, Z Description: The contents of register ‘f’ are shifted one bit to the left through the Carry flag. A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’.
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PIC16(L)F1512/3 MOVIW Move INDFn to W Syntax: [ label ] MOVIW ++FSRn [ label ] MOVIW --FSRn [ label ] MOVIW FSRn++ [ label ] MOVIW FSRn-[ label ] MOVIW k[FSRn] Operands: n  [0,1] mm  [00,01, 10, 11] -32  k  31 Operation: INDFn  W Effective address is determined by • FSR + 1 (preincrement) • FSR - 1 (predecrement) • FSR + k (relative offset) After the Move, the FSR value will be either: • FSR + 1 (all increments) • FSR - 1 (all decrements) • Unchanged Status Affected: MOVLP Move literal to PCL
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PIC16(L)F1512/3 MOVWI Move W to INDFn Syntax: [ label ] MOVWI ++FSRn [ label ] MOVWI --FSRn [ label ] MOVWI FSRn++ [ label ] MOVWI FSRn-[ label ] MOVWI k[FSRn] Operands: Operation: Status Affected: n  [0,1] mm  [00,01, 10, 11] -32  k  31 W  INDFn Effective address is determined by • FSR + 1 (preincrement) • FSR - 1 (predecrement) • FSR + k (relative offset) After the Move, the FSR value will be either: • FSR + 1 (all increments) • FSR - 1 (all decrements) Unchanged None No Operation Syntax: [
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PIC16(L)F1512/3 RETFIE Return from Interrupt Syntax: [ label ] RETURN RETFIE k Return from Subroutine Syntax: [ label ] None RETURN Operands: None Operands: Operation: TOS  PC, 1  GIE Operation: TOS  PC Status Affected: None Status Affected: None Description: Description: Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction.
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PIC16(L)F1512/3 SUBLW Subtract W from literal Syntax: [ label ] RRF Rotate Right f through Carry Syntax: [ label ] Operands: 0  f  127 d  [0,1] Operation: See description below Status Affected: C, DC, Z Status Affected: C Description: Description: The contents of register ‘f’ are rotated one bit to the right through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’.
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PIC16(L)F1512/3 SWAPF Swap Nibbles in f XORLW Exclusive OR literal with W Syntax: [ label ] Syntax: [ label ] Operands: 0  f  127 d  [0,1] Operation: SWAPF f,d (f<3:0>)  (destination<7:4>), (f<7:4>)  (destination<3:0>) XORLW k Operands: 0 k 255 Operation: (W) .XOR. k W) Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register.
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PIC16(L)F1512/3 25.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings(†) Ambient temperature under bias....................................................................................................... -40°C to +125°C Storage temperature ........................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS, PIC16F1512/3 .......................................................................... -0.
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PIC16(L)F1512/3 PIC16F1512/3 VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C FIGURE 25-1: VDD (V) 5.5 2.5 2.3 0 4 10 16 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 25-1 for each Oscillator mode’s supported frequencies. PIC16LF1512/3 VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C VDD (V) FIGURE 25-2: 3.6 2.5 1.
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PIC16(L)F1512/3 25.1 DC Characteristics: PIC16(L)F1512/3-I/E (Industrial, Extended) PIC16LF1512/3 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended PIC16F1512/3 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param. No. D001 Sym. VDD Characteristic VDR Typ† Max. Units Conditions PIC16LF1512/3 1.8 2.
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PIC16(L)F1512/3 FIGURE 25-3: POR AND POR REARM WITH SLOW RISING VDD VDD VPOR VPORR VSS NPOR POR REARM VSS TVLOW(2) Note 1: 2: 3: DS41624B-page 296 TPOR(3) When NPOR is low, the device is held in Reset. TPOR 1 s typical. TVLOW 2.7 s typical. Preliminary  2012 Microchip Technology Inc.
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PIC16(L)F1512/3 25.2 DC Characteristics: PIC16(L)F1512/3-I/E (Industrial, Extended) PIC16LF1512/3 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended PIC16F1512/3 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param No. Device Characteristics Min. Conditions Typ† Max. Units — 8.0 14 A 1.8 — 12.
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PIC16(L)F1512/3 25.2 DC Characteristics: PIC16(L)F1512/3-I/E (Industrial, Extended) (Continued) PIC16LF1512/3 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended PIC16F1512/3 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param No. Device Characteristics Min. Typ† — — Conditions Max. Units 120 210 A 1.
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PIC16(L)F1512/3 25.2 DC Characteristics: PIC16(L)F1512/3-I/E (Industrial, Extended) (Continued) PIC16LF1512/3 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended PIC16F1512/3 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param No. Device Characteristics Units Conditions Min. Typ† Max. — 1.0 1.8 mA 3.
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PIC16(L)F1512/3 25.3 DC Characteristics: PIC16(L)F1512/3-I/E (Power-Down) PIC16LF1512/3 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended PIC16F1512/3 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param No. Max. +85°C Max. +125°C Units — 0.02 1.0 8.0 A — 0.03 2.0 9.0 A 3.0 — 0.30 2.
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PIC16(L)F1512/3 25.3 DC Characteristics: PIC16(L)F1512/3-I/E (Power-Down) (Continued) PIC16LF1512/3 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended PIC16F1512/3 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param No. Device Characteristics D026 Min. Typ† Max. +85°C Max. +125°C Units — 0.
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PIC16(L)F1512/3 25.4 DC Characteristics: PIC16(L)F1512/3-I/E DC CHARACTERISTICS Param No. Sym. VIL Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Min. Typ† Max. Units Conditions Input Low Voltage I/O PORT: D030 — — 0.8 V 4.5V  VDD  5.5V — — 0.15 VDD V 1.8V  VDD  4.5V with Schmitt Trigger buffer — — 0.2 VDD V 2.0V  VDD  5.5V with I2C™ levels — — 0.
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PIC16(L)F1512/3 25.5 Memory Programming Requirements Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C DC CHARACTERISTICS Param No. Sym. Characteristic Min. Typ† Max. Units Conditions Program Memory Programming Specifications D110 VIHH Voltage on MCLR/VPP/RA5 pin 8.0 — 9.0 V D111 IDDP Supply Current during Programming — — 10 mA VDD for Bulk Erase 2.7 — VDD max. V D112 D113 VPEW VDD for Write or Row Erase VDD min. — VDD max.
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PIC16(L)F1512/3 25.6 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param No. TH01 TH02 Sym. Characteristic JA Thermal Resistance Junction to Ambient JC TH03 TJMAX TH04 PD TH05 Thermal Resistance Junction to Case Maximum Junction Temperature Power Dissipation PINTERNAL Internal Power Dissipation Typ.
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PIC16(L)F1512/3 25.7 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2.
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PIC16(L)F1512/3 25.8 AC Characteristics: PIC16(L)F1512/3-I/E FIGURE 25-5: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1/CLKIN OS02 OS04 OS04 OS03 OSC2/CLKOUT (LP,XT,HS modes) OSC2/CLKOUT (CLKOUT mode) TABLE 25-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param No. OS01 Sym.
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PIC16(L)F1512/3 TABLE 25-2: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. OS08 Sym. HFOSC Freq. Tolerance Min. Typ† Max. Units Conditions 2% 4% — — 16.0 16.0 — — MHz MHz 4% to 8% — 16.0 — MHz 4% to 12% — 16.0 — MHz 25°C; 3.2V 0°C  TA  +85°C 2.3V  VDD  5.5V -40°C  TA  +125°C 2.0V  VDD  5.5V -40°C  TA  +125°C 1.8V  VDD  5.
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PIC16(L)F1512/3 TABLE 25-3: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. OS11 OS12 Sym. TosH2ckL Characteristic Min. Typ† Max. Units Conditions — — 70 ns VDD = 3.3-5.0V — — 72 ns VDD = 3.3-5.
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PIC16(L)F1512/3 FIGURE 25-8: BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD VBOR and VHYST VBOR (Device in Brown-out Reset) (Device not in Brown-out Reset) 37 Reset 33(1) (due to BOR) Note 1: 64 ms delay only if PWRTE bit in the Configuration Words is programmed to ‘0’. 2 ms delay if PWRTE = 0 and VREGEN = 1.  2012 Microchip Technology Inc.
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PIC16(L)F1512/3 TABLE 25-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. Sym. Characteristic MCLR Pulse Width (low) Min. Typ† Max. Units 2 — — s 10 16 27 ms 30 TMCL 31 TWDTLP Low-Power Watchdog Timer Time-out Period 32 TOST Oscillator Start-up Timer Period(1), (2) — 1024 — Conditions VDD = 3.
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PIC16(L)F1512/3 FIGURE 25-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 49 47 TMR0 or TMR1 TABLE 25-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. 40* Sym. TT0H Characteristic T0CKI High Pulse Width Min.
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PIC16(L)F1512/3 FIGURE 25-10: CAPTURE/COMPARE/PWM TIMINGS (CCP) CCP (Capture mode) CC01 CC02 CC03 Note: Refer to Figure 25-4 for load conditions. TABLE 25-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP) Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C  TA  +125°C Param Sym. No. Characteristic CC01* TccL CCP Input Low Time CC02* TccH CCP Input High Time CC03* TccP * † Min. Typ† Max. Units 0.5TCY + 20 — — ns With Prescaler 20 — — ns No Prescaler 0.
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PIC16(L)F1512/3 TABLE 25-8: PIC16(L)F1512/3 A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param No. Sym. Characteristic AD130* TAD AD131 TCNV AD132* TACQ Min. Typ† Max. Units Conditions A/D Clock Period 1.0 — 9.0 s TOSC-based A/D Internal RC Oscillator Period 1.0 1.6 6.
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PIC16(L)F1512/3 FIGURE 25-12: PIC16(L)F1512/3 A/D CONVERSION TIMING (SLEEP MODE) BSF ADCON0, GO (TOSC/2 + TCY(1)) AD134 1 TCY AD131 Q4 AD130 A/D CLK 7 A/D Data 5 6 3 4 1 0 NEW_DATA OLD_DATA ADRESx 2 ADIF 1 TCY GO DONE Sampling Stopped AD132 Sample Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
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PIC16(L)F1512/3 TABLE 25-10: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param. No. Symbol Characteristic Min. Max. Units — 80 ns US120 TCKH2DTV SYNC XMIT (Master and Slave) Clock high to data-out valid 3.0-5.5V 1.8-5.5V — 100 ns US121 TCKRF Clock out rise time and fall time (Master mode) 3.0-5.5V — 45 ns 1.8-5.5V — 50 ns US122 TDTRF Data-out rise time and fall time 3.0-5.
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PIC16(L)F1512/3 FIGURE 25-15: SPI MASTER MODE TIMING (CKE = 0, SMP = 0) SSx SP70 SCKx (CKP = 0) SP71 SP72 SP78 SP79 SP79 SP78 SCKx (CKP = 1) SP80 bit 6 - - - - - -1 MSb SDOx LSb SP75, SP76 SDIx MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 25-4 for load conditions.
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PIC16(L)F1512/3 FIGURE 25-17: SPI SLAVE MODE TIMING (CKE = 0) SSx SP70 SCKx (CKP = 0) SP83 SP71 SP72 SP78 SP79 SP79 SP78 SCKx (CKP = 1) SP80 MSb SDOx LSb bit 6 - - - - - -1 SP77 SP75, SP76 SDIx MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 25-4 for load conditions.
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PIC16(L)F1512/3 TABLE 25-12: SPI MODE REQUIREMENTS Param No. Symbol Characteristic Min. Typ† Max. Units Conditions SP70* TSSL2SCH, SSx to SCKx or SCKx input TSSL2SCL TCY — — ns SP71* TSCH SCKx input high time (Slave mode) TCY + 20 — — ns SP72* TSCL SCKx input low time (Slave mode) TCY + 20 — — ns 100 — — ns 100 — — ns 3.0-5.5V — 10 25 ns 1.8-5.
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PIC16(L)F1512/3 FIGURE 25-20: I2C™ BUS DATA TIMING SP103 SCLx SP100 SP90 SP102 SP101 SP106 SP107 SP91 SDAx In SP92 SP110 SP109 SP109 SDAx Out Note: Refer to Figure 25-4 for load conditions.  2012 Microchip Technology Inc.
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PIC16(L)F1512/3 TABLE 25-13: I2C™ BUS DATA REQUIREMENTS Param. No. Symbol SP100* THIGH Characteristic Clock high time Min. Max. Units 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz SSP module SP101* TLOW Clock low time 1.5TCY — — 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a minimum of 10 MHz 1.
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PIC16(L)F1512/3 26.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS Graphs and charts are not available at this time.  2012 Microchip Technology Inc.
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PIC16(L)F1512/3 NOTES: DS41624B-page 322 Preliminary  2012 Microchip Technology Inc.
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PIC16(L)F1512/3 27.0 DEVELOPMENT SUPPORT 27.
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PIC16(L)F1512/3 27.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 27.
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PIC16(L)F1512/3 27.7 MPLAB SIM Software Simulator 27.9 The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
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PIC16(L)F1512/3 27.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 27.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
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PIC16(L)F1512/3 28.0 PACKAGING INFORMATION 28.1 Package Marking Information 28-Lead SOIC (7.50 mm) Example XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX PIC16F1512-E/SO YYWWNNN 1110017 28-Lead SPDIP (.300”) Example PIC16F1512-E/SP 1110017 28-Lead SSOP (5.30 mm) Example PIC16F1512-E/SS e3 1110017 Legend: XX...
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PIC16(L)F1512/3 Package Marking Information (Continued) 28-Lead UQFN (4x4x0.5 mm) Example PIN 1 DS41624B-page 328 PIN 1 Preliminary PIC16 F1513 I/ML e3 110017  2012 Microchip Technology Inc.
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PIC16(L)F1512/3 28.2 Package Details The following sections give the technical details of the packages. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2012 Microchip Technology Inc.
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PIC16(L)F1512/3 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41624B-page 330 Preliminary  2012 Microchip Technology Inc.
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PIC16(L)F1512/3 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2012 Microchip Technology Inc.
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PIC16(L)F1512/3 /HDG 6NLQQ\ 3ODVWLF 'XDO ,Q /LQH 63 ± PLO %RG\ >63',3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV ,1&+(6 0,1 1 120 0$; 3LWFK H 7RS WR 6HDWLQJ 3ODQH $ ± ± 0ROGHG 3DFNDJH 7KLFNQHVV $ %DVH WR 6HDWLQJ 3ODQH $ ± ± 6KRXOGHU WR 6KRXOGHU :LGWK (
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PIC16(L)F1512/3 /HDG 3ODVWLF 6KULQN 6PDOO 2XWOLQH 66 ± PP %RG\ >6623@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D N E E1 1 2 NOTE 1 b e c A2 A φ A1 L L1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 0,//,0(7(56 0,1 1 120 0$; 3LWFK H 2YHUDOO +HLJKW $ ± %6& ± 0ROGHG 3DFNDJH 7KLFNQHVV $ 6WDQGRII $ ± ± 2YHUDOO :LGWK ( 0ROGHG
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PIC16(L)F1512/3 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41624B-page 334 Preliminary  2012 Microchip Technology Inc.
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PIC16(L)F1512/3 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2012 Microchip Technology Inc.
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PIC16(L)F1512/3 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41624B-page 336 Preliminary  2012 Microchip Technology Inc.
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PIC16(L)F1512/3 APPENDIX A: DATA SHEET REVISION HISTORY Revision A (02/2012) Original release (02/2012) Revision B (06/2012) Updated Figure 16-1; Removed Figure 16-8; Added new Figure 16-8; Replaced Figures 16-9 and 16-10; Added Note 1 to Figure 16-12; Added Note 3 to Register 16-1; Added Note 4 to Register 16-7; Updated the Electrical Specifications section; Other minor corrections.  2012 Microchip Technology Inc.
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PIC16(L)F1512/3 NOTES: DS41624B-page 338 Preliminary  2012 Microchip Technology Inc.
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PIC16(L)F1512/3 INDEX A A/D Specifications.................................................... 312, 313 AADACQ Register ............................................................ 158 AADCAP Register ............................................................. 159 AADCON0 Register .......................................................... 153 AADCON1 Register .......................................................... 154 AADCON2 Register ..........................................................
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PIC16(L)F1512/3 Specifications ............................................................ 312 CCP. See Capture/Compare/PWM CCPxCON (CCPx) Register.............................................. 246 Clock Accuracy with Asynchronous Operation ................. 256 Clock Sources External Modes ........................................................... 45 EC ....................................................................... 45 HS .......................................................................
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PIC16(L)F1512/3 Instruction Set ................................................................... 279 ADDLW ..................................................................... 283 ADDWF..................................................................... 283 ADDWFC .................................................................. 283 ANDLW ..................................................................... 283 ANDWF..................................................................... 283 BRA.........
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PIC16(L)F1512/3 PCON Register ............................................................. 26, 65 PIE1 Register ................................................................ 26, 73 PIE2 Register ................................................................ 26, 74 Pinout Descriptions .................................................................................... 11 PIR1 Register................................................................ 26, 75 PIR2 Register...................................
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PIC16(L)F1512/3 TRISB (Tri-State PORTB)......................................... 112 TRISC (Tri-State PORTC) ........................................ 115 TRISE (Tri-State PORTE)......................................... 118 TXSTA (Transmit Status and Control) ...................... 256 VREGCON (Voltage Regulator Control) ..................... 81 WDTCON (Watchdog Timer Control) ......................... 87 WPUB (Weak Pull-up PORTB) ................................. 113 RESET ..................................
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PIC16(L)F1512/3 Wake-up from Interrupt ............................................... 80 Timing Parameter Symbology........................................... 305 Timing Requirements I2C Bus Data ............................................................. 320 SPI Mode .................................................................. 318 TMR0 Register .................................................................... 26 TMR1H Register .................................................................
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PIC16(L)F1512/3 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
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PIC16(L)F1512/3 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
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PIC16(L)F1512/3 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. [X](1) PART NO.
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Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.