Datasheet

PIC16(L)F1512/3
DS41624B-page 74 Preliminary  2012 Microchip Technology Inc.
7.6.3 PIE2 REGISTER
The PIE2 register contains the interrupt enable bits, as
shown in Register 7-3.
Note: Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
REGISTER 7-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0/0 U-0 U-0 U-0 R/W-0/0 U-0 U-0 R/W-0/0
OSFIE — — —BCLIE — — CCP2IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 OSFIE: Oscillator Fail Interrupt Enable bit
1 = Enables the oscillator fail interrupt
0 = Disables the oscillator fail interrupt
bit 6-4 Unimplemented: Read as ‘0’
bit 3 BCLIE: MSSP Bus Collision Interrupt Enable bit
1 = Enables the MSSP bus collision interrupt
0 = Disables the MSSP bus collision interrupt
bit 2-1 Unimplemented: Read as ‘0’
bit 0 CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt