Datasheet

 2012 Microchip Technology Inc. Preliminary DS41624B-page 157
PIC16(L)F1512/3
REGISTER 16-11: AADSTAT: A/D STATUS REGISTER
REGISTER 16-12: AADPRE: A/D PRE-CHARGE CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — —ADCONV ADSTG<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-3
Unimplemented: Read as ‘0’
bit 2
ADCONV: A/D Conversion Status bit
1 = Indicates A/D in Conversion Sequence for AADRES1H:AADRES1L
0 = Indicates A/D in Conversion Sequence for AADRES0H:AADRES0L (Also reads ‘0’ when
GO/DONE
= 0)
bit 1-0 ADSTG<1:0>: A/D Stage Status bits
11 = A/D module is in conversion stage
10 = A/D module is in acquisition stage
01 = A/D module is in pre-charge stage
00 = A/D module is not converting (same as GO/DONE
= 0)
U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— ADPRE<6:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-0
ADPRE<6:0>: Pre-charge Time Select bits
(1)
111 1111 = Pre-charge for 127 instruction cycles
111 1110 = Pre-charge for 126 instruction cycles
•
•
•
000 0001 = Pre-charge for 1 instruction cycle (Fosc/4)
000 0000 = ADC pre-charge time is disabled
Note 1: When the FRC clock is selected as the conversion clock source, it is also the clock used for the
pre-charge and acquisition times.