Datasheet

PIC16(L)F1512/3
DS41624B-page 130 Preliminary  2012 Microchip Technology Inc.
FIGURE 16-1: ADC BLOCK DIAGRAM
Note 1: When ADON = 0, all multiplexer inputs are disconnected.
2: See AADCON0 register (Register 16-7) for detailed analog channel selection per device.
3: ADRES0H and AADRES0H are the same register in two locations, Bank 1 and Bank 14. See Table 3-9.
4: ADRES0L and AADRES0L are the same register in two locations, Bank 1 and Bank 14. See Ta ble 3 -9.
VDD
VREF+
ADPREF =
10
ADPREF = 0x
FVR
FVR Buffer1
ADON
(1)
GO/DONE
VSS
ADC
00000
00001
00010
00011
CHS<4:0>
(2)
AN0
AN1
AN2
V
REF+/AN3
11111
ADRESxL
(4)
10
16
ADFM
0 = Left Justify
1 = Right Justify
Temp Indicator
11101
10011
AN19
11001
Reserved
ADPREF =
11
AN4
Reserved
Reserved
Reserved
AN8
00100
00101
00110
00111
01000
10100
Reserved
11010
VREFH (ADC positive reference)
11011
VREFL (ADC negative reference)
ADRESxH
(3)
AN9
01001
AN10
01010
AN11
01011
AN12
01100
AN13
01101
AN14
01110
AN15
01111
AN16
10000
AN17
10001
AN18
10010
11100
Reserved
11110Reserved