Datasheet

 2011-2013 Microchip Technology Inc. DS40001609B-page 341
PIC16(L)F1508/9
FIGURE 29-11: CLC PROPAGATION TIMING
TABLE 29-12: CONFIGURATION LOGIC CELL (CLC) CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Sym. Characteristic Min. Typ† Max. Units Conditions
CLC01* TCLCIN CLC input time — 7 — ns
CLC02* T
CLC CLC module input to output progagation time —
—
24
12
—
—
ns
ns
VDD = 1.8V
V
DD > 3.6V
CLC03* TCLCOUT CLC output time Rise Time — OS18 — — (Note 1)
Fall Time — OS19 — — (Note 1)
CLC04* F
CLCMAX CLC maximum switching frequency — 45 — MHz
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: See Table 29-9 for OS18 and OS19 rise and fall times.
LCx_in[n]
(1)
CLC
Output time
CLC
Input time
LCx_out
(1)
CLCx
CLCxINn
CLC
Module
CLC01 CLC02 CLC03
LCx_in[n]
(1)
CLC
Output time
CLC
Input time
LCx_out
(1)
CLCx
CLCxINn
CLC
Module
Rev. 10-000031A_A3
Note 1: See Figure 24-1, CLC Simplified Block Diagram.