Datasheet

 2011-2013 Microchip Technology Inc. DS40001609B-page 269
PIC16(L)F1508/9
24.0 CONFIGURABLE LOGIC CELL
(CLC)
The Configurable Logic Cell (CLCx) provides program-
mable logic that operates outside the speed limitations
of software execution. The logic cell takes up to 16
input signals, and through the use of configurable
gates, reduces the 16 inputs to four logic lines that drive
one of eight selectable single-output logic functions.
Input sources are a combination of the following:
• I/O pins
• Internal clocks
• Peripherals
• Register bits
The output can be directed internally to peripherals and
to an output pin.
Refer to Figure 24-1 for a simplified diagram showing
signal flow through the CLCx.
Possible configurations include:
• Combinatorial Logic
-AND
-NAND
- AND-OR
- AND-OR-INVERT
-OR-XOR
-OR-XNOR
• Latches
-S-R
- Clocked D with Set and Reset
- Transparent D with Set and Reset
- Clocked J-K with Reset
FIGURE 24-1: CLCx SIMPLIFIED BLOCK DIAGRAM
Input Data Selection Gates
(1)
Logic
Function
(2)
lcxg2
lcxg1
lcxg3
lcxg4
LCxMODE<2:0>
lcxq
LCxEN
LCx_in[0]
LCx_in[1]
LCx_in[2]
LCx_in[3]
LCx_in[4]
LCx_in[5]
LCx_in[6]
LCx_in[7]
LCx_in[8]
LCx_in[9]
LCx_in[10]
LCx_in[11]
LCx_in[12]
LCx_in[13]
LCx_in[14]
LCx_in[15]
LCxPOL
det
Interrupt
det
Interrupt
set bit
CLCxIF
LCXINTN
LCXINTP
LCxOE
TRIS Control
CLCx
to Peripherals
Q1
LCx_out
LCxOUT
MLCxOUT
DQ
Rev. 10-000025A_A1
Note 1: See Figure 24-2, Input Data Selection and Gating.
2: See Figure 24-3, Programmable Logic Functions.