Datasheet

PIC16(L)F1508/9
DS40001609B-page 260  2011-2013 Microchip Technology Inc.
FIGURE 22-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
TABLE 22-8: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER
RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
BAUDCON
ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 247
INTCON GIE PEIE
TMR0IE INTE IOCIE TMR0IF INTF IOCIF 76
PIE1
TMR1GIE ADIE RCIE TXIE SSP1IE — TMR2IE TMR1IE 77
PIR1
TMR1GIF ADIF RCIF TXIF SSP1IF — TMR2IF TMR1IF 80
RCREG EUSART Receive Data Register 240*
RCSTA SPEN RX9 SREN CREN
ADDEN FERR OERR RX9D 246
SPBRGL BRG<7:0> 248*
SPBRGH BRG<15:8> 248*
TRISB TRISB7
TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 116
TXSTA
CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 245
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous master reception.
* Page provides register information.
CREN bit
RX/DT
Write to
bit SREN
SREN bit
RCIF bit
(Interrupt)
Read
RCREG
‘0’
bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
‘0’
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TX/CK pin
TX/CK pin
pin
(SCKP = 0)
(SCKP = 1)