Datasheet

PIC16(L)F1508/9
DS40001609B-page 346  2011-2013 Microchip Technology Inc.
FIGURE 29-14: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 29-17: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 29-15: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 29-18: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Symbol Characteristic Min. Max. Units Conditions
US120 TCKH2DTV SYNC XMIT (Master and Slave)
Clock high to data-out valid
—80ns3.0V
 VDD  5.5V
— 100 ns 1.8V
 VDD  5.5V
US121 T
CKRF Clock out rise time and fall time
(Master mode)
—45ns3.0V  VDD  5.5V
—50ns1.8V
 VDD  5.5V
US122 T
DTRF Data-out rise time and fall time — 45 ns 3.0V  VDD  5.5V
—50ns1.8V
 VDD  5.5V
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Symbol Characteristic Min. Max. Units Conditions
US125 TDTV2CKL SYNC RCV (Master and Slave)
Data-hold before CK  (DT hold time) 10 — ns
US126 T
CKL2DTL Data-hold after CK  (DT hold time) 15 — ns
Note: Refer to Figure 29-4 for load conditions.
US121
US121
US120
US122
CK
DT
Note: Refer to Figure 29-4 for load conditions.
US125
US126
CK
DT