Datasheet

 2011-2013 Microchip Technology Inc. DS40001609C-page 333
PIC16(L)F1508/9
TABLE 29-4: I/O PORTS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Sym. Characteristic Min. Typ† Max. Units Conditions
V
IL Input Low Voltage
I/O PORT:
D030 with TTL buffer — — 0.8 V 4.5V  V
DD  5.5V
D030A — — 0.15 V
DD V1.8V  VDD  4.5V
D031 with Schmitt Trigger buffer — — 0.2 V
DD V2.0V  VDD  5.5V
with I
2
C™ levels — — 0.3 VDD V
with SMbus levels — — 0.8 V 2.7V  V
DD  5.5V
D032 MCLR
, OSC1 (EXTRC mode) — — 0.2 VDD V (Note 1)
D033 OSC1 (HS mode) — — 0.3 V
DD V
V
IH Input High Voltage
I/O PORT:
D040 with TTL buffer 2.0 — — V 4.5V  V
DD 5.5V
D040A 0.25 V
DD +
0.8
——V1.8V  VDD  4.5V
D041 with Schmitt Trigger buffer 0.8 V
DD ——V2.0V  VDD  5.5V
with I
2
C™ levels 0.7 VDD ——V
with SMbus levels 2.1 — — V 2.7V  V
DD  5.5V
D042 MCLR
0.8 VDD ——V
D043A OSC1 (HS mode) 0.7 V
DD ——V
D043B OSC1 (EXTRC mode) 0.9 V
DD ——VVDD  2.0V (Note 1)
I
IL Input Leakage Current
(2)
D060 I/O Ports — ± 5 ± 125 nA VSS  VPIN  VDD,
Pin at high-impedance, 85°C
— ± 5 ± 1000 nA V
SS  VPIN  VDD,
Pin at high-impedance, 125°C
D061 MCLR
(3)
—± 50± 200nAVSS  VPIN  VDD,
Pin at high-impedance, 85°C
I
PUR Weak Pull-up Current
D070* 25 100 200 AV
DD = 3.3V, VPIN = VSS
25 140 300 AVDD = 5.0V, VPIN = VSS
VOL Output Low Voltage
(4)
D080 I/O Ports
——0.6V
IOL = 8 mA, VDD = 5V
I
OL = 6 mA, VDD = 3.3V
I
OL = 1.8 mA, VDD = 1.8V
V
OH Output High Voltage
(4)
D090 I/O Ports
V
DD - 0.7 — — V
I
OH = 3.5 mA, VDD = 5V
I
OH = 3 mA, VDD = 3.3V
I
OH = 1 mA, VDD = 1.8V
D101* COSC2 Capacitive Loading Specifications on Output Pins
OSC2 pin
— — 15 pF
In XT, HS, LP modes when
external clock is used to drive
OSC1
D101A* CIO All I/O pins — — 50 pF
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an
external clock in EXTRC mode.
2: Negative current is defined as current sourced by the pin.
3: The leakage current on the MCLR
pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
4: Excluding OSC2 in CLKOUT mode.