Datasheet

PIC16(L)F1508/9
DS40001609C-page 272  2011-2013 Microchip Technology Inc.
24.1 CLCx Setup
Programming the CLCx module is performed by config-
uring the four stages in the logic signal flow. The four
stages are:
•Data selection
• Data gating
• Logic function selection
• Output polarity
Each stage is setup at run time by writing to the corre-
sponding CLCx Special Function Registers. This has
the added advantage of permitting logic reconfiguration
on-the-fly during program execution.
24.1.1 DATA SELECTION
There are 16 signals available as inputs to the configu-
rable logic. Four 8-input multiplexers are used to select
the inputs to pass on to the next stage. The 16 inputs
to the multiplexers are arranged in groups of four. Each
group is available to two of the four multiplexers, in
each case, paired with a different group. This arrange-
ment makes possible selection of up to two from a
group without precluding a selection from another
group.
Data selection is through four multiplexers as indicated
on the left side of Figure 24-2. Data inputs in the figure
are identified by a generic numbered input name.
Table 24-1 correlates the generic input name to the
actual signal for each CLC module. The columns labeled
lcxd1 through lcxd4 indicate the MUX output for the
selected data input. D1S through D4S are abbreviations
for the MUX select input codes: LCxD1S<2:0> through
LCxD4S<2:0>, respectively. Selecting a data input in a
column excludes all other inputs in that column.
Data inputs are selected with CLCxSEL0 and
CLCxSEL1 registers (Register 24-3 and Register 24-5,
respectively).
Note: Data selections are undefined at power-up.
TABLE 24-1: CLCx DATA INPUT SELECTION
Data Input
lcxd1
D1S
lcxd2
D2S
lcxd3
D3S
lcxd4
D4S
CLC 1CLC 2CLC 3CLC 4
LCx_in[0] 000
— — 100 CLC1IN0 CLC2IN0 CLC3IN0 CLC4IN0
LCx_in[1] 001
— — 101 CLC1IN1 CLC2IN1 CLC3IN1 CLC4IN1
LCx_in[2] 010
— — 110 C1OUT_sync C1OUT_sync C1OUT_sync C1OUT_sync
LCx_in[3] 011
— — 111 C2OUT_sync C2OUT_sync C2OUT_sync C2OUT_sync
LCx_in[4] 100 000
— —FOSC FOSC FOSC FOSC
LCx_in[5] 101 001 — — T0_overflow T0_overflow T0_overflow T0_overflow
LCx_in[6] 110 010
— — T1_overflow T1_overflow T1_overflow T1_overflow
LCx_in[7] 111 011
— — T2_match T2_match T2_match T2_match
LCx_in[8]
— 100 000 — LC1_out LC1_out LC1_out LC1_out
LCx_in[9]
— 101 001 — LC2_out LC2_out LC2_out LC2_out
LCx_in[10]
— 110 010 — LC3_out LC3_out LC3_out LC3_out
LCx_in[11]
— 111 011 — LC4_out LC4_out LC4_out LC4_out
LCx_in[12]
— — 100 000 NCO1_out LFINTOSC TX_out
(EUSART)
SCK_output
(MSSP)
LCx_in[13]
— — 101 001 HFINTOSC FRC LFINTOSC SDO_output
(MSSP)
LCx_in[14]
— — 110 010 PWM3_out PWM1_out PWM2_out PWM1_out
LCx_in[15]
— — 111 011 PWM4_out PWM2_out PWM3_out PWM4_out