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ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller SSOP 20 8-Bit 20 MHz I/O number 17

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20-Pin Flash, 8-Bit Microcontrollers with XLP Technology
PIC12(L)F1501/PIC16(L)F150X Family Types
Pin Diagrams
Pin Allocation Table
TABLE 1: 20-Pin Allocation Table (PIC16(L)F1508/9)
Table of Contents
1.0 Device Overview
- TABLE 1-1: Device Peripheral Summary
- FIGURE 1-1: PIC16(L)F1508/9 Block Diagram
- TABLE 1-2: PIC16(L)F1508/9 Pinout Description
2.0 Enhanced Mid-Range CPU
- FIGURE 2-1: Core Block Diagram
3.0 Memory Organization
- TABLE 3-1: Device Sizes and Addresses
- FIGURE 3-1: Program Memory Map And Stack For PIC16(L)F1508
- FIGURE 3-2: Program Memory Map And Stack For PIC16(L)F1509
  - EXAMPLE 3-1: RETLW Instruction
  - EXAMPLE 3-2: Accessing Program Memory Via FSR
  - 3.2 Data Memory Organization
- TABLE 3-2: Core Registers
  - Register 3-1: STATUS: STATUS Register
- FIGURE 3-3: Banked Memory Partitioning
- TABLE 3-3: PIC16(L)F1509 Memory Map, Bank 1-7
- TABLE 3-4: PIC16(L)F1508 Memory Map, Bank 1-7
- TABLE 3-5: PIC16(L)F1508/9 Memory Map, Bank 8-23
- 3.1 Program Memory Organization
- FIGURE 3-11: Linear Data Memory Map
- TABLE 3-6: PIC16(L)F1508/9 Memory Map, Bank 24-31
- TABLE 3-7: PIC16(L)F1508/9 Memory Map, Bank 30-31
- TABLE 3-8: Core Function Registers Summary
- TABLE 3-9: Special Function Register Summary
  - 3.3 PCL and PCLATH
- FIGURE 3-4: Loading of PC in Different Situations
  - 3.4 Stack
- FIGURE 3-5: Accessing the Stack Example 1
- FIGURE 3-6: Accessing the Stack Example 2
- FIGURE 3-7: Accessing the Stack Example 3
- FIGURE 3-8: Accessing the Stack Example 4
  - 3.5 Indirect Addressing
- FIGURE 3-9: Indirect Addressing
- FIGURE 3-10: Traditional Data Memory Map
- FIGURE 3-12: Program Flash Memory Map
4.0 Device Configuration
- 4.1 Configuration Words
- 4.2 Register Definitions: Configuration Words
- Register 4-1: CONFIG1: Configuration Word 1
- Register 4-2: CONFIG2: Configuration Word 2
- 4.3 Code Protection
- 4.4 Write Protection
- 4.5 User ID
- 4.6 Device ID and Revision ID
- 4.7 Register Definitions: Device ID
- Register 4-3: DEVID: Device ID Register
5.0 Oscillator Module (With Fail-Safe Clock Monitor)
- FIGURE 5-1: Simplified PIC® MCU Clock Source Block Diagram
  - 5.2 Clock Source Types
- FIGURE 5-2: External Clock (EC) Mode Operation
- FIGURE 5-3: Quartz Crystal Operation (LP, XT or HS Mode)
- FIGURE 5-4: Ceramic Resonator Operation (XT or HS Mode)
- FIGURE 5-5: Quartz Crystal Operation (Secondary Oscillator)
- FIGURE 5-6: External RC Modes
- TABLE 5-1: Peripheral Clock Sources
- FIGURE 5-7: Internal Oscillator Switch Timing
  - 5.3 Clock Switching
- TABLE 5-2: OSTS Bit Definition
  - 5.4 Two-Speed Clock Start-up Mode
- TABLE 5-3: Oscillator Switching Delays
- FIGURE 5-8: Two-Speed Start-up
  - 5.5 Fail-Safe Clock Monitor
- FIGURE 5-9: FSCM Block Diagram
- FIGURE 5-10: FSCM Timing Diagram
- TABLE 5-4: Summary of Registers Associated with Clock Sources
- 5.1 Overview
- TABLE 5-5: Summary of Configuration Word with Clock Sources
6.0 Resets
- FIGURE 6-1: Simplified Block Diagram of On-Chip Reset Circuit
  - 6.1 Power-On Reset (POR)
  - 6.2 Brown-Out Reset (BOR)
- TABLE 6-1: BOR Operating Modes
- FIGURE 6-2: Brown-out Situations
- TABLE 6-2: MCLR Configuration
- FIGURE 6-3: Reset Start-up Sequence
  - 6.12 Determining the Cause of a Reset
- TABLE 6-3: Reset Status Bits and Their Significance
- TABLE 6-4: Reset Condition for Special Registers
- TABLE 6-5: Summary of Registers Associated with Resets
- TABLE 6-6: Summary of Configuration Word with Resets
7.0 Interrupts
- FIGURE 7-1: Interrupt Logic
  - 7.1 Operation
  - 7.2 Interrupt Latency
- FIGURE 7-2: Interrupt Latency
- FIGURE 7-3: INT Pin Interrupt Timing
- TABLE 7-1: Summary of Registers Associated with Interrupts
8.0 Power-Down Mode (Sleep)
- FIGURE 8-1: Wake-up from Sleep through Interrupt
- TABLE 8-1: Summary of Registers Associated with Power-Down Mode
- 8.1 Wake-up from Sleep
9.0 Watchdog Timer (WDT)
- FIGURE 9-1: Watchdog Timer Block Diagram
  - 9.1 Independent Clock Source
  - 9.2 WDT Operating Modes
- TABLE 9-1: WDT Operating Modes
- TABLE 9-2: WDT Clearing Conditions
  - 9.6 Register Definitions: Watchdog Control
  - Register 9-1: WDTCON: Watchdog Timer Control Register
- TABLE 9-3: Summary of Registers Associated with Watchdog Timer
- TABLE 9-4: Summary of Configuration Word with Watchdog Timer
10.0 Flash Program Memory Control
- TABLE 10-1: Flash Memory Organization by Device
- FIGURE 10-1: Flash Program Memory Read Flowchart
- FIGURE 10-2: Flash Program Memory Read Cycle Execution
  - EXAMPLE 10-1: Flash Program Memory Read
- FIGURE 10-3: Flash Program Memory Unlock Sequence Flowchart
- FIGURE 10-4: Flash Program Memory Erase Flowchart
  - EXAMPLE 10-2: Erasing One Row of Program Memory
- FIGURE 10-5: Block Writes to Flash Program Memory with 32 Write latches
- FIGURE 10-6: Flash Program Memory Write Flowchart
  - EXAMPLE 10-3: Writing to Flash Program Memory (32 Write Latches)
  - 10.3 Modifying Flash Program Memory
- FIGURE 10-7: Flash Program Memory Modify Flowchart
  - 10.4 User ID, Device ID and Configuration Word Access
- TABLE 10-2: User ID, Device ID and Configuration Word Access (CFGS = 1)
  - EXAMPLE 10-4: Configuration Word and Device ID Access
  - 10.5 Write Verify
- 10.1 PMADRL and PMADRH Registers
- 10.2 Flash Program Memory Overview
- FIGURE 10-8: Flash Program Memory Verify Flowchart
- TABLE 10-3: Summary of Registers Associated with Flash Program Memory
- TABLE 10-4: Summary of Configuration Word with Flash Program Memory
11.0 I/O Ports
- TABLE 11-1: Port Availability Per Device
- FIGURE 11-1: Generic I/O Port Operation
- TABLE 11-2: PORTA Output Priority
- TABLE 11-3: Summary of Registers Associated with PORTA
- TABLE 11-4: Summary of Configuration Word with PORTA
  - 11.5 PORTB Registers
- TABLE 11-5: PORTB Output Priority
- TABLE 11-6: Summary of Registers Associated with PORTB
- TABLE 11-7: Summary of Configuration Word with PORTB
  - 11.7 PORTC Registers
- TABLE 11-8: PORTC Output Priority
- TABLE 11-9: Summary of Registers Associated with PORTC
12.0 Interrupt-On-Change
- FIGURE 12-1: Interrupt-On-Change Block Diagram (PORTA Example)
- TABLE 12-1: Summary of Registers Associated with Interrupt-on-Change
- 12.1 Enabling the Module
- 12.2 Individual Pin Configuration
- 12.3 Interrupt Flags
- 12.4 Clearing Interrupt Flags
- EXAMPLE 12-1: Clearing Interrupt Flags (PORTA Example)
- 12.5 Operation in Sleep
13.0 Fixed Voltage Reference (FVR)
- FIGURE 13-1: Voltage Reference Block Diagram
- TABLE 13-1: Peripherals Requiring the Fixed Voltage Reference (FVR)
  - 13.3 Register Definitions: FVR Control
  - Register 13-1: FVRCON: Fixed Voltage Reference Control Register
- TABLE 13-2: Summary of Registers Associated with the Fixed Voltage Reference
- 13.1 Independent Gain Amplifier
- 13.2 FVR Stabilization Period
14.0 Temperature Indicator Module
- FIGURE 14-1: Temperature Circuit Diagram
  - 14.2 Minimum Operating Vdd
- TABLE 14-1: Recommended Vdd vs. Range
  - 14.3 Temperature Output
  - 14.4 ADC Acquisition Time
- TABLE 14-2: Summary of Registers Associated with the Temperature Indicator
- 14.1 Circuit Operation
- EQUATION 14-1: Vout Ranges
15.0 Analog-to-Digital Converter (ADC) Module
- FIGURE 15-1: ADC Block Diagram
  - 15.1 ADC Configuration
- TABLE 15-1: ADC Clock Period (Tad) Vs. Device Operating Frequencies
- FIGURE 15-2: Analog-to-Digital Conversion Tad Cycles
- FIGURE 15-3: 10-Bit ADC Conversion Result Format
  - 15.2 ADC Operation
- TABLE 15-2: Auto-Conversion Sources
- FIGURE 15-4: Analog Input Model
- FIGURE 15-5: ADC Transfer Function
- TABLE 15-3: Summary of Registers Associated with ADC
16.0 5-Bit Digital-to-Analog Converter (DAC) Module
- FIGURE 16-1: Digital-to-Analog Converter Block Diagram
- TABLE 16-1: Summary of Registers Associated with the DAC Module
17.0 Comparator Module
- TABLE 17-1: Available Comparators
- FIGURE 17-1: Comparator Module Simplified Block Diagram
- FIGURE 17-2: Single Comparator
  - 17.2 Comparator Control
- TABLE 17-2: Comparator Output State vs. Input Conditions
  - 17.3 Analog Input Connection Considerations
- FIGURE 17-3: Analog Input Model
- FIGURE 17-4: Analog Input Model
- TABLE 17-3: Summary of Registers Associated with Comparator Module
- 17.1 Comparator Overview
18.0 Timer0 Module
- FIGURE 18-1: Timer0 Block Diagram
  - 18.2 Register Definitions: Option Register
  - Register 18-1: OPTION_REG: OPTION Register
- TABLE 18-1: Summary of Registers Associated with Timer0
- 18.1 Timer0 Operation
19.0 Timer1 Module with Gate Control
- FIGURE 19-1: Timer1 Block Diagram
  - 19.1 Timer1 Operation
- TABLE 19-1: Timer1 Enable Selections
  - 19.2 Clock Source Selection
- TABLE 19-2: Clock Source Selections
- TABLE 19-3: Timer1 Gate Enable Selections
- TABLE 19-4: Timer1 Gate Sources
  - 19.7 Timer1 Interrupt
  - 19.8 Timer1 Operation During Sleep
- FIGURE 19-2: Timer1 Incrementing Edge
- FIGURE 19-3: Timer1 Gate Enable Mode
- FIGURE 19-4: Timer1 Gate Toggle Mode
- FIGURE 19-5: Timer1 Gate Single-Pulse Mode
- FIGURE 19-6: Timer1 Gate Single-Pulse and Toggle Combined Mode
- TABLE 19-5: Summary of Registers Associated with Timer1
20.0 Timer2 Module
- FIGURE 20-1: Timer2 Block Diagram
- FIGURE 20-2: Timer2 Timing Diagram
- FIGURE 20-3: T2_match Timing Diagram
- TABLE 20-1: Summary of Registers Associated With Timer2
21.0 Master Synchronous Serial Port (MSSP) Module
- FIGURE 21-1: MSSP Block Diagram (SPI mode)
- FIGURE 21-2: MSSPx Block Diagram (I2C™ Master mode)
- FIGURE 21-3: MSSP Block Diagram (I2C™ Slave mode)
  - 21.2 SPI Mode Overview
- FIGURE 21-4: SPI Master and Multiple Slave Connection
- FIGURE 21-5: SPI Master/Slave Connection
- FIGURE 21-6: SPI Mode Waveform (Master Mode)
- FIGURE 21-7: SPI Daisy-Chain Connection
- FIGURE 21-8: Slave Select Synchronous Waveform
- FIGURE 21-9: SPI Mode Waveform (Slave Mode With CKE = 0)
- FIGURE 21-10: SPI Mode Waveform (SLAve Mode With CKE = 1)
- 21.1 MSSP Module Overview
- TABLE 21-1: Summary of Registers Associated with SPI Operation
  - 21.3 I2C Mode Overview
- FIGURE 21-11: I2C Master/ Slave Connection
  - 21.4 I2C Mode Operation
- TABLE 21-2: I2C Bus terms
- FIGURE 21-12: I2C Start and Stop Conditions
- FIGURE 21-13: I2C Restart Condition
  - 21.5 I2C Slave Mode Operation
- FIGURE 21-14: I2C Slave, 7-bit Address, Reception (SEN = 0, AHEN = 0, DHEN = 0)
- FIGURE 21-15: I2C Slave, 7-bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0)
- FIGURE 21-16: I2C Slave, 7-bit Address, Reception (SEN = 0, AHEN = 1, DHEN = 1)
- FIGURE 21-17: I2C Slave, 7-bit Address, Reception (SEN = 1, AHEN = 1, DHEN = 1)
- FIGURE 21-18: I2C Slave, 7-bit Address, Transmission (AHEN = 0)
- FIGURE 21-19: I2C Slave, 7-bit Address, Transmission (AHEN = 1)
- FIGURE 21-20: I2C Slave, 10-bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0)
- FIGURE 21-21: I2C Slave, 10-bit Address, Reception (SEN = 0, AHEN = 1, DHEN = 0)
- FIGURE 21-22: I2C Slave, 10-bit Address, Transmission (SEN = 0, AHEN = 0, DHEN = 0)
- FIGURE 21-23: Clock Synchronization Timing
- FIGURE 21-24: Slave Mode General Call Address Sequence
  - 21.6 I2C Master Mode
- FIGURE 21-25: Baud Rate Generator Timing with Clock Arbitration
- FIGURE 21-26: First Start Bit Timing
- FIGURE 21-27: Repeat Start Condition Waveform
- FIGURE 21-28: I2C Master Mode Waveform (Transmission, 7 or 10-bit Address)
- FIGURE 21-29: I2C Master Mode Waveform (Reception, 7-bit Address)
- FIGURE 21-30: Acknowledge Sequence Waveform
- FIGURE 21-31: Stop Condition Receive or Transmit Mode
- FIGURE 21-32: Bus Collision Timing for Transmit and Acknowledge
- FIGURE 21-33: Bus Collision During Start Condition (SDAx Only)
- FIGURE 21-34: Bus Collision During Start Condition (SCLx = 0)
- FIGURE 21-35: BRG Reset Due to SDA Arbitration During Start Condition
- FIGURE 21-36: Bus Collision During a Repeated Start Condition (Case 1)
- FIGURE 21-37: Bus Collision During Repeated Start Condition (Case 2)
- FIGURE 21-38: Bus Collision During a Stop Condition (Case 1)
- FIGURE 21-39: Bus Collision During a Stop Condition (Case 2)
- TABLE 21-3: Summary of Registers Associated with I2C™ Operation
  - 21.7 Baud Rate Generator
- FIGURE 21-40: Baud Rate Generator Block Diagram
- TABLE 21-4: MSSP Clock Rate w/BRG
  - 21.8 Register Definitions: MSSP Control
  - Register 21-1: SSPxSTAT: SSP STATUS Register
  - Register 21-2: SSPxCON1: SSP Control Register 1
  - Register 21-3: SSPxCON2: SSP Control Register 2(1)
  - Register 21-4: SSPxCON3: SSP Control Register 3
  - Register 21-5: SSPxMSK: SSP Mask Register
  - Register 21-6: SSPxADD: MSSP Address and Baud Rate Register (I2C Mode)
22.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)
- FIGURE 22-1: EUSART Transmit Block Diagram
- FIGURE 22-2: EUSART Receive Block Diagram
  - 22.1 EUSART Asynchronous Mode
- FIGURE 22-3: Asynchronous Transmission
- FIGURE 22-4: Asynchronous Transmission (Back-to-Back)
- TABLE 22-1: Summary of Registers Associated with Asynchronous Transmission
- FIGURE 22-5: Asynchronous Reception
- TABLE 22-2: Summary of Registers Associated with Asynchronous Reception
  - 22.2 Clock Accuracy with Asynchronous Operation
  - 22.3 Register Definitions: EUSART Control
  - Register 22-1: TXSTA: Transmit Status and Control Register
  - Register 22-2: RCSTA: Receive Status and Control Register
  - Register 22-3: BAUDCON: Baud Rate Control Register
  - 22.4 EUSART Baud Rate Generator (BRG)
  - EXAMPLE 22-1: Calculating Baud Rate Error
- TABLE 22-3: Baud Rate Formulas
- TABLE 22-4: Summary of Registers Associated with the Baud Rate Generator
- TABLE 22-5: BAUD Rates for Asynchronous Modes
- TABLE 22-6: BRG Counter Clock Rates
- FIGURE 22-6: Automatic Baud Rate Calibration
- FIGURE 22-7: Auto-Wake-up Bit (WUE) Timing During Normal Operation
- FIGURE 22-8: Auto-Wake-up Bit (WUE) Timings During Sleep
- FIGURE 22-9: Send Break Character Sequence
  - 22.5 EUSART Synchronous Mode
- FIGURE 22-10: Synchronous Transmission
- FIGURE 22-11: Synchronous Transmission (Through TXEN)
- TABLE 22-7: Summary of Registers Associated with Synchronous Master Transmission
- FIGURE 22-12: Synchronous Reception (Master Mode, SREN)
- TABLE 22-8: Summary of Registers Associated with Synchronous Master Reception
- TABLE 22-9: Summary of Registers Associated with Synchronous Slave Transmission
- TABLE 22-10: Summary of Registers Associated with Synchronous Slave Reception
23.0 Pulse Width Modulation (PWM) Module
- FIGURE 23-1: Simplified PWM Block Diagram
- FIGURE 23-2: PWM Output
  - EQUATION 23-4: PWM Resolution
- TABLE 23-1: Example PWM Frequencies and Resolutions (Fosc = 20 MHz)
- TABLE 23-2: Example PWM Frequencies and Resolutions (Fosc = 8 MHz)
- TABLE 23-3: Summary of Registers Associated with PWM
24.0 Configurable Logic Cell (CLC)
- FIGURE 24-1: Digital-to-Analog Converter Block Diagram
  - 24.1 CLCx Setup
- TABLE 24-1: CLCx Data Input Selection
- TABLE 24-2: Data Gating Logic
- FIGURE 24-2: Input Data Selection and Gating
- FIGURE 24-3: Programmable Logic Functions
- TABLE 24-3: Summary of Registers Associated with CLCx
25.0 Numerically Controlled Oscillator (NCO) Module
- FIGURE 25-1: Numerically Controlled Oscillator (NCOx) Module Simplified Block Diagram
- FIGURE 25-2: NCO – Fixed Duty Cycle (FDC) and Pulse Frequency Mode (PFM) Output Operation Diagram
- TABLE 25-1: Summary of Registers Associated with NCOx
- 25.1 NCOx Operation
- EQUATION 25-1:
26.0 Complementary Waveform Generator (CWG) Module
- TABLE 26-1: Selectable Input Sources
  - 26.4 Output Control
- FIGURE 26-1: Simplified CWG Block Diagram
- FIGURE 26-2: Typical CWG Operation with PWM1 (No Auto-shutdown)
- FIGURE 26-3: Dead-Band Operation, CWGxDBR = 01H, CWGxDBF = 02H
- FIGURE 26-4: Dead-Band Operation, CWGxDBR = 03H, CWGxDBF = 04H, Source Shorter Than Dead Band
- FIGURE 26-5: Shutdown Functionality, Auto-Restart Disabled (GxARSEN = 0,GxASDLA = 01, GxASDLB = 01)
- FIGURE 26-6: Shutdown Functionality, Auto-Restart Enabled (GxARSEN = 1,GxASDLA = 01, GxASDLB = 01)
- 26.1 Fundamental Operation
- 26.2 Clock Source
- 26.3 Selectable Input Sources
- TABLE 26-2: Summary of Registers Associated with CWG
27.0 In-Circuit Serial Programming™ (ICSP™)
- FIGURE 27-1: ICD RJ-11 Style Connector Interface
- FIGURE 27-2: PICkit™ Programmer Style Connector Interface
- FIGURE 27-3: Typical connection for ICSP™ Programming
- 27.1 High-Voltage Programming Entry Mode
- 27.2 Low-Voltage Programming Entry Mode
- 27.3 Common Programming Interfaces
28.0 Instruction Set Summary
- TABLE 28-1: Opcode Field Descriptions
- TABLE 28-2: Abbreviation Descriptions
- FIGURE 28-1: General Format for Instructions
- TABLE 28-3: Enhanced Mid-Range Instruction Set
- TABLE 28-3: Enhanced Mid-Range Instruction Set (Continued)
  - 28.2 Instruction Descriptions
- 28.1 Read-Modify-Write Operations
29.0 Electrical Specifications
- FIGURE 29-13: ADC Conversion Timing (ADC Clock from FRC)
  - FIGURE 29-15: USART Synchronous Receive (Master/Slave) Timing
  - TABLE 29-18: USART Synchronous Receive Requirements
  - FIGURE 29-16: SPI Master Mode Timing (CKE = 0, SMP = 0)
  - FIGURE 29-17: SPI Master Mode Timing (CKE = 1, SMP = 1)
  - FIGURE 29-18: SPI Slave Mode Timing (CKE = 0)
  - FIGURE 29-19: SPI Slave Mode Timing (CKE = 1)
  - TABLE 29-19: SPI Mode requirements
  - FIGURE 29-20: I2C™ Bus Start/Stop Bits Timing
  - TABLE 29-20: I2C™ Bus Start/Stop Bits Requirements
  - FIGURE 29-21: I2C™ Bus Data Timing
    - TABLE 29-21: I2C™ Bus Data Requirements
- TABLE 29-14: ADC Conversion Requirements
- TABLE 29-15: Comparator Specifications(1)
- TABLE 29-16: Digital-to-Analog Converter (DAC) Specifications(1)
- FIGURE 29-14: USART Synchronous Transmission (Master/Slave) Timing
- TABLE 29-17: USART Synchronous Transmission Requirements
- FIGURE 29-1: Voltage Frequency Graph, -40°C £ Ta £ +125°C, PIC16F1508/9 only
- FIGURE 29-2: Voltage Frequency Graph, -40°C £ Ta £ +125°C, PIC16LF1508/9 only
  - 29.3 DC Characteristics
- TABLE 29-1: Supply Voltage
- FIGURE 29-3: POR and POR Rearm with Slow Rising Vdd
- TABLE 29-2: Supply Current (Idd)(1,2)
- TABLE 29-3: Power-Down Currents (Ipd)(1,2)
- TABLE 29-4: I/O Ports
- TABLE 29-5: Memory Programming Specifications
- TABLE 29-6: Thermal Characteristics
  - 29.4 AC Characteristics
- FIGURE 29-4: Load Conditions
- FIGURE 29-5: Clock Timing
- TABLE 29-7: Clock Oscillator Timing Requirements
- TABLE 29-8: Oscillator Parameters
- 29.1 Absolute Maximum Ratings(†)
- 29.2 Standard Operating Conditions
- FIGURE 29-6: HFINTOSC Frequency Accuracy Over Vdd and Temperature
- FIGURE 29-7: CLKOUT and I/O Timing
- TABLE 29-9: CLKOUT and I/O Timing Parameters
- FIGURE 29-8: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing
- TABLE 29-10: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-Out Reset Parameters
- FIGURE 29-9: Brown-Out Reset Timing and Characteristics
- FIGURE 29-10: Timer0 and Timer1 External Clock Timings
- TABLE 29-11: Timer0 and Timer1 External Clock Requirements
- FIGURE 29-11: CLC Propagation Timing
- TABLE 29-12: Configuration Logic Cell (CLC) Characteristics
- TABLE 29-13: Analog-to-Digital Converter (ADC) Characteristics(1,2,3)
- FIGURE 29-12: ADC Conversion Timing (ADC Clock Fosc-based)
30.0 DC and AC Characteristics Graphs and Charts
- FIGURE 30-1: Idd, LP Oscillator, Fosc = 32 kHz, PIC16LF1508/9 ONLY
- FIGURE 30-2: Idd, LP Oscillator, Fosc = 32 kHz, PIC16F1508/9 ONLY
- FIGURE 30-3: Idd Typical, XT and EXTRC Oscillator, PIC16LF1508/9 ONLY
- FIGURE 30-4: Idd Maximum, XT and EXTRC Oscillator, PIC16LF1508/9 ONLY
- FIGURE 30-5: Idd Typical, XT and EXTRC Oscillator, PIC16F1508/9 ONLY
- FIGURE 30-6: Idd Maximum, XT and EXTRC Oscillator, PIC16F1508/9 ONLY
- FIGURE 30-7: Idd, External Clock (ECL), Low-Power Mode, Fosc = 32 kHz, PIC16LF1508/9 ONLY
- FIGURE 30-8: Idd, External Clock (ECL), Low-Power Mode, Fosc = 32 kHz, PIC16F1508/9 ONLY
- FIGURE 30-9: Idd, External Clock (ECL), Low-Power Mode, Fosc = 500 kHz, PIC16LF1508/9 ONLY
- FIGURE 30-10: Idd, External Clock (ECL), Low-Power Mode, Fosc = 500 kHz, PIC16F1508/9 ONLY
- FIGURE 30-13: Idd Typical, External Clock (ECM), Medium-Power Mode, PIC16F1508/9 ONLY
- FIGURE 30-14: Idd Maximum, External Clock (ECM), Medium-Power Mode, PIC16F1508/9 ONLY
- FIGURE 30-15: Idd Typical, External Clock (ECH), High-Power Mode, PIC16LF1508/9 ONLY
- FIGURE 30-16: Idd Maximum, External Clock (ECH), High-Power Mode, PIC16LF1508/9 ONLY
- FIGURE 30-17: Idd Typical, External Clock (ECH), High-Power Mode, PIC16F1508/9 ONLY
- FIGURE 30-18: Idd Maximum, External Clock (ECH), High-Power Mode, PIC16F1508/9 ONLY
- FIGURE 30-12: Idd Maximum, External Clock (ECM), Medium-Power Mode, PIC16LF1508/9 ONLY
- FIGURE 30-11: Idd Typical, External Clock (ECM), Medium-Power Mode, PIC16LF1508/9 ONLY
- FIGURE 30-19: Idd, LFINTOSC, Fosc = 31 kHz, PIC16LF1508/9 Only
- FIGURE 30-20: Idd, LFINTOSC, Fosc = 31 kHz, PIC16F1508/9 Only
- FIGURE 30-21: Idd, MFINTOSC, Fosc = 500 kHz, PIC16LF1508/9 ONLY
- FIGURE 30-22: Idd, MFINTOSC, Fosc = 500 kHz, PIC16F1508/9 ONLY
- FIGURE 30-23: Idd Typical, HFINTOSC, PIC16LF1508/9 ONLY
- FIGURE 30-24: Idd Maximum, HFINTOSC, PIC16LF1508/9 ONLY
- FIGURE 30-25: Idd Typical, HFINTOSC, PIC16F1508/9 ONLY
- FIGURE 30-26: Idd Maximum, HFINTOSC, PIC16F1508/9 ONLY
- FIGURE 30-27: Idd Typical, HS OScillator, PIC16LF1508/9 ONLY
- FIGURE 30-28: Idd Maximum, HS Oscillator, PIC16LF1508/9 ONLY
- FIGURE 30-29: Idd Typical, HS Oscillator, PIC16F1508/9 ONLY
- FIGURE 30-30: Idd Maximum, HS Oscillator, PIC16F1508/9 ONLY
- FIGURE 30-31: Ipd Base, Low-Power Sleep Mode, PIC16LF1508/9 ONly
- FIGURE 30-32: Ipd Base, Low-Power Sleep Mode, VREGPM = 1, PIC16F1508/9 ONLy
- FIGURE 30-33: Ipd, Watchdog Timer (WDT), PIC16LF1508/9 ONLy
- FIGURE 30-34: Ipd, Watchdog Timer (WDT), PIC16F1508/9 ONLy
- FIGURE 30-35: Ipd, Fixed Voltage Reference (FVR), PIC16LF1508/9 ONLy
- FIGURE 30-36: Ipd, Fixed Voltage Reference (FVR), PIC16F1508/9 ONLy
- FIGURE 30-37: Ipd, Brown-Out Reset (BOR), BORV = 0, PIC16LF1508/9 ONLY
- FIGURE 30-38: Ipd, Brown-Out Reset (BOR), BORV = 1, PIC16LF1508/9 Only
- FIGURE 30-39: Ipd, Brown-Out Reset (BOR), BORV = 0, PIC16F1508/9 Only
- FIGURE 30-40: Ipd, Brown-Out Reset (BOR), BORV = 1, PIC16F1508/9 Only
- FIGURE 30-41: Ipd, Secondary Oscillator, Fosc = 32 kHz, PIC16LF1508/9 Only
- FIGURE 30-42: Ipd, Secondary Oscillator, Fosc = 32 kHz, PIC16F1508/9 Only
- FIGURE 30-43: Ipd, Comparator, Low-Power Mode (CxSP = 0), PIC16LF1508/9 Only
- FIGURE 30-44: Ipd, Comparator, Low-Power Mode (CxSP = 0), PIC16F1508/9 Only
- FIGURE 30-45: Ipd, Comparator, Normal-Power Mode (CxSP = 1), PIC16LF1508/9 Only
- FIGURE 30-46: Ipd, Comparator, Normal-Power Mode (CxSP = 1), PIC16F1508/9 Only
- FIGURE 30-47: Voh vs. Ioh over Temperature, Vdd = 5.5V, PIC16F1508/9 Only
- FIGURE 30-48: Vol vs. Iol over Temperature, Vdd = 5.5V, PIC16F1508/9 Only
- FIGURE 30-49: Voh vs. Ioh over Temperature, Vdd = 3.0V
- FIGURE 30-50: Vol vs. Iol over Temperature, Vdd = 3.0V
- FIGURE 30-51: Voh vs. Ioh over Temperature, Vdd = 1.8V, PIC16LF1508/9 Only
- FIGURE 30-52: Vol vs. Iol over Temperature, Vdd = 1.8V, PIC16LF1508/9 Only
- FIGURE 30-53: POR Release Voltage
- FIGURE 30-54: POR Rearm Voltage, PIC16F1508/9 Only
- FIGURE 30-55: Brown-Out Reset Voltage, BORV = 1, PIC16LF1508/9 Only
- FIGURE 30-56: Brown-Out Reset Hysteresis, BORV = 1, PIC16LF1508/9 Only
- FIGURE 30-57: Brown-Out Reset Voltage, BORV = 1, PIC16F1508/9 Only
- FIGURE 30-58: Brown-Out Reset Hysteresis, BORV = 1, PIC16F1508/9 Only
- FIGURE 30-59: Brown-Out Reset Voltage, BORV = 0
- FIGURE 30-60: Brown-Out Reset Hysteresis, BORV = 0
- FIGURE 30-61: Low-Power Brown-Out Reset Voltage, LPBOR = 0
- FIGURE 30-62: Low-Power Brown-Out Reset Hysteresis, LPBOR = 0
- FIGURE 30-63: WDT Time-Out Period
- FIGURE 30-64: PWRT Period
- FIGURE 30-65: FVR Stabilization Period
- FIGURE 30-66: Comparator Hysteresis, Normal-Power Mode (CxSP = 1, CxHYS = 1)
- FIGURE 30-67: Comparator Hysteresis, Low-Power Mode (CxSP = 0, CxHYS = 1)
- FIGURE 30-68: Comparator Response Time, Normal-Power Mode (CxSP = 1)
- FIGURE 30-69: Comparator Response Time Over Temperature, Normal-Power Mode (CxSP = 1)
- FIGURE 30-70: Comparator Input Offset at 25°C, Normal-Power Mode (CxSP = 1), PIC16F1508/9 Only
- FIGURE 30-71: LFINTOSC Frequency Over Vdd and Temperature, PIC16LF1508/9 Only
- FIGURE 30-72: LFINTOSC Frequency Over Vdd and Temperature, PIC16F1508/9 Only
- FIGURE 30-73: HFINTOSC Accuracy Over Temperature, Vdd = 1.8V, PIC16LF1508/9 Only
- FIGURE 30-74: HFINTOSC Accuracy Over Temperature, 2.3V £ Vdd £ 5.5V
- FIGURE 30-75: Sleep Mode, Wake Period with HFINTOSC Source, PIC16LF1508/9 Only
- FIGURE 30-76: Low-Power Sleep Mode, Wake Period with HFINTOSC Source, VREGPM = 1, PIC16F1508/9 Only
- FIGURE 30-77: Sleep Mode, Wake Period with HFINTOSC Source, VREGPM = 0, PIC16F1508/9 Only
31.0 Development Support
- 31.1 MPLAB X Integrated Development Environment Software
- 31.2 MPLAB XC Compilers
- 31.3 MPASM Assembler
- 31.4 MPLINK Object Linker/ MPLIB Object Librarian
- 31.5 MPLAB Assembler, Linker and Librarian for Various Device Families
- 31.6 MPLAB X SIM Software Simulator
- 31.7 MPLAB REAL ICE In-Circuit Emulator System
- 31.8 MPLAB ICD 3 In-Circuit Debugger System
- 31.9 PICkit 3 In-Circuit Debugger/ Programmer
- 31.10 MPLAB PM3 Device Programmer
- 31.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits
- 31.12 Third-Party Development Tools
32.0 Packaging Information
- 32.1 Package Marking Information
- 32.2 Package Marking Information
- 32.3 Package Details
Appendix A: Data Sheet Revision History
Product ID System
Trademarks
Worldwide Sales and Service

 2011-2013 Microchip Technology Inc. DS40001609C-page 21

PIC16(L)F1508/9

TABLE 3-3: PIC16(L)F1509 MEMORY MAP, BANK 1-7

BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7

000h

Core Registers

(Table 3 -2)

080h

Core Registers

(Table 3 -2)

100h

Core Registers

(Table 3-2)

180h

Core Registers

(Table 3-2)

200h

Core Registers

(Table 3-2)

280h

Core Registers

(Table 3-2)

300h

Core Registers

(Table 3-2)

380h

Core Registers

(Table 3-2)

00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh

00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch

— 30Ch — 38Ch —

00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh

— 30Dh — 38Dh —

00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh

—28Eh—30Eh—38Eh—

00Fh

—08Fh—10Fh—18Fh—20Fh—28Fh—30Fh—38Fh—

010h

—090h—110h—190h—210h—290h

—

310h

— 390h —

011h PIR1 091h PIE1 111h CM1CON0 191h PMADRL 211h

SSP1BUF

291h

—

311h

—

391h IOCAP

012h PIR2 092h PIE2 112h CM1CON1 192h PMADRH 212h

SSP1ADD

292h

—

312h

—

392h IOCAN

013h PIR3 093h PIE3 113h CM2CON0 193h PMDATL 213h

SSP1MSK

293h

—

313h

—

393h

IOCAF

014h

—094h— 114h CM2CON1 194h PMDATH 214h

SSP1STAT

294h

—

314h

—

394h IOCBP

015h TMR0 095h OPTION_REG 115h CMOUT 195h PMCON1 215h

SSP1CON1

295h

—

315h

—

395h IOCBN

016h

TMR1L 096h PCON 116h BORCON 196h PMCON2 216h

SSP1CON2

296h

— 316h — 396h IOCBF

017h

TMR1H 097h WDTCON 117h FVRCON 197h VREGCON 217h

SSP1CON3

297h

— 317h — 397h —

018h

T1CON 098h

—118h

DAC1CON0

198h —218h

—

298h

— 318h — 398h —

019h

T1GCON 099h OSCCON 119h

DAC1CON1

199h

RCREG

219h

—299h— 319h — 399h —

01Ah

TMR2 09Ah OSCSTAT 11Ah

—19Ah

TXREG

21Ah —29Ah—31Ah—39Ah—

01Bh

PR2 09BhADRESL11Bh

—19Bh

SPBRG

21Bh —29Bh—31Bh

—

39Bh

—

01Ch

T2CON 09Ch ADRESH 11Ch

— 19Ch

SPBRGH

21Ch — 29Ch — 31Ch

—

39Ch

—

01Dh

— 09Dh ADCON0 11Dh APFCON 19Dh

RCSTA

21Dh

—

29Dh

—

31Dh

—

39Dh

—

01Eh

—

09Eh ADCON1 11Eh

—

19Eh

TXSTA

21Eh

—

29Eh

—

31Eh

—

39Eh

—

01Fh

—

09Fh ADCON2 11Fh

—19Fh

BAUDCON

21Fh

—

29Fh

—

31Fh

—

39Fh

—

020h

General

Purpose

80 Bytes

0A0h

General

Purpose

80 Bytes

120h

General

Purpose

80 Bytes

1A0h

Unimplemented

Read as ‘0’

220h

Unimplemented

Read as ‘0’

2A0h

Unimplemented

Read as ‘0’

320h

Unimplemented

Read as ‘0’

3A0h

Unimplemented

Read as ‘0’

0EFh

06Fh

16Fh 1EFh 26Fh 2EFh

36Fh 3EFh

070h

Common RAM

0F0h

Common RAM

(Accesses

70h – 7Fh)

170h

Common RAM

(Accesses

70h – 7Fh)

1F0h

Common RAM

(Accesses

70h – 7Fh)

270h

Common RAM

(Accesses

70h – 7Fh)

2F0h

Common RAM

(Accesses

70h – 7Fh)

370h

Common RAM

(Accesses

70h – 7Fh)

3F0h

Common RAM

(Accesses

70h – 7Fh)

07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh

Legend: = Unimplemented data memory locations, read as ‘0’.