Datasheet

PIC16(L)F1508/9
DS40001609C-page 182  2011-2013 Microchip Technology Inc.
The I
2
C interface supports the following modes and
features:
•Master mode
• Slave mode
• Byte NACKing (Slave mode)
• Limited Multi-master support
• 7-bit and 10-bit addressing
• Start and Stop interrupts
• Interrupt masking
• Clock stretching
• Bus collision detection
• General call address matching
•Address masking
• Address Hold and Data Hold modes
• Selectable SDAx hold times
Figure 21-2 is a block diagram of the I
2
C interface mod-
ule in Master mode. Figure 21-3 is a diagram of the I
2
C
interface module in Slave mode.
The PIC16(L)F1508/9 has one MSSP module.
FIGURE 21-2: MSSPX BLOCK DIAGRAM (I
2
C™ MASTER MODE)
Note 1: In devices with more than one MSSP
module, it is very important to pay close
attention to SSPxCONx register names.
SSPxCON1 and SSPxCON2 registers
control different operational aspects of
the same module, while SSPxCON1 and
SSP2CON1 control the same features for
two different modules.
2: Throughout this section, generic refer-
ences to an MSSPx module in any of its
operating modes may be interpreted as
being equally applicable to MSSPx or
MSSP2. Register names, module I/O sig-
nals, and bit names may use the generic
designator ‘x’ to indicate the use of a
numeral to distinguish a particular module
when required.
Read Write
SSPxBUF
8 8
SSPxSR
8
Internal data
bus
Start bit, Stop bit,
Acknowledge
Generate
(SSPxCON2)
Baud Rate
Generator
(SSPxADD)
Shift clock
Start bit detected
Stop bit detected
Write collsion detect
Clock arbitration
State counter for end
of XMIT/RCV
Address match detect
Clock Cntl
SCLx in
Bus collision
Receive Enable (RCEN)
MSb LSb
SDAx
SCLx
SDAx in
Clock arbitrate/BCOL detect
(Hold off clock source)
Set/Reset: S, P, SSPxSTAT,
WCOL, SSPOV
Reset SEN, PEN (SSPxCON2)
Set SSPxIF, BCLxIF
4
[SSPM <3:0>]
Rev. 10-000077A
7/30/2013