Datasheet

PIC16(L)F1508/9
DS40001609C-page 178  2011-2013 Microchip Technology Inc.
20.1 Timer2 Operation
The clock input to the Timer2 module is the system
instruction clock (F
OSC/4).
TMR2 increments from 00h on each clock edge.
A 4-bit counter/prescaler on the clock input allows direct
input, divide-by-4 and divide-by-16 prescale options.
These options are selected by the prescaler control bits,
T2CKPS<1:0> of the T2CON register. The value of
TMR2 is compared to that of the Period register, PR2, on
each clock cycle. When the two values match, the
comparator generates a match signal as the timer
output. This signal also resets the value of TMR2 to 00h
on the next cycle and drives the output counter/
postscaler (see Section 20.2 “Timer2 Interrupt”).
The TMR2 and PR2 registers are both directly readable
and writable. The TMR2 register is cleared on any
device Reset, whereas the PR2 register initializes to
FFh. Both the prescaler and postscaler counters are
cleared on the following events:
• a write to the TMR2 register
• a write to the T2CON register
• Power-On Reset (POR)
• Brown-Out Reset (BOR)
•MCLR
Reset
• Watchdog Timer (WDT) Reset
• Stack Overflow Reset
• Stack Underflow Reset
• RESET Instruction
20.2 Timer2 Interrupt
Timer2 can also generate an optional device interrupt.
The Timer2 output signal (T2_match) provides the input
for the 4-bit counter/postscaler. This counter generates
the TMR2 match interrupt flag which is latched in
TMR2IF of the PIR1 register. The interrupt is enabled by
setting the TMR2 Match Interrupt Enable bit, TMR2IE of
the PIE1 register.
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS<3:0>, of the T2CON register.
20.3 Timer2 Output
The output of TMR2 is T2_match. T2_match is available
to the following peripherals:
• Configurable Logic Cell (CLC)
• Master Synchronous Serial Port (MSSP)
• Numerically Controlled Oscillator (NCO)
• Pulse Width Modulator (PWM)
The T2_match signal is synchronous with the system
clock. Figure 20-3 shows two examples of the timing of
the T2_match signal relative to F
OSC and prescale
value, T2CKPS<1:0>. The upper diagram illustrates 1:1
prescale timing and the lower diagram, 1:X prescale
timing.
FIGURE 20-3: T2_MATCH TIMING
DIAGRAM
20.4 Timer2 Operation During Sleep
Timer2 cannot be operated while the processor is in
Sleep mode. The contents of the TMR2 and PR2
registers will remain unchanged while the processor is
in Sleep mode.
Note: TMR2 is not cleared when T2CON is
written.
T2_match
FOSC/4
TMR2 = PR2
match
TMR2 = 0
...
PRESCALE = 1:X
(T2CKPS<1:0>=01,10,11)
TCY1TCY2TCYX
...
...
Q1 Q2 Q3
FOSC
TMR2 = PR2
match
TMR2 = 0
Q1Q4
T2_match
F
OSC/4
PRESCALE = 1:1
(T2CKPS<1:0>=00)
TCY1
Rev. 10-000021A
7/30/2013