PIC16(L)F1508/9 20-Pin Flash, 8-Bit Microcontrollers with XLP Technology High-Performance RISC CPU: • C Compiler Optimized Architecture • Only 49 Instructions • Up to 8 Kwords Linear Program Memory Addressing • Up to 512 bytes Linear Data Memory Addressing • Operating Speed: - DC – 20 MHz clock input - DC – 200 ns instruction cycle • Interrupt Capability with Automatic Context Saving • 16-Level Deep Hardware Stack with Optional Overflow/Underflow Reset • Direct, Indirect and Relative Addressing modes: - Two
PIC16(L)F1508/9 Peripheral Features (Continued): • Numerically Controlled Oscillator (NCO): - 20-bit accumulator - 16-bit increment - True linear frequency control - High-speed clock input - Selectable Output modes - Fixed Duty Cycle (FDC) mode - Pulse Frequency (PF) mode • Complementary Waveform Generator (CWG): - Eight selectable signal sources - Selectable falling and rising edge dead-band control - Polarity control - Four auto-shutdown sources - Multiple input sources: PWM, CLC, NCO • Master Synchrono
PIC16(L)F1508/9 PIN DIAGRAMS Pin Diagram – 20-Pin PDIP, SOIC, SSOP 20 RA5 2 19 VSS RA0/ICSPDAT RA4 3 4 18 RA1/ICSPCLK 17 RA2 16 RC0 15 RC1 14 RC2 MCLR/VPP/RA3 PIC16(L)F1508 1 PIC16(L)F1509 VDD RC5 5 RC4 6 RC3 7 RC6 8 13 RB4 RC7 9 12 RB5 RB7 10 11 RB6 Note: See Table 1 for location of all peripheral functions.
PIC16(L)F1508/9 PIN ALLOCATION TABLE — — RA1 18 15 AN1 VREF+ C1IN0C2IN0- — — RA2 17 14 AN2 DAC1OUT2 C1OUT T0CKI RA3 4 1 — — — RA4 3 20 AN3 — RA5 2 19 — RB4 13 10 RB5 12 9 RB6 11 RB7 — — — — IOC Y ICSPDAT ICDDAT — — — CLC4IN1 — IOC Y ICSPCLK ICDCLK — — CWG1FLT — CLC1 PWM3 INT/ IOC Y — T1G(1) — SS(1) — — CLC1IN0 — IOC Y MCLR VPP — SOSCO T1G — — — — — — IOC Y CLKOUT OSC2 — — SOSCI T1CKI — — — NCO1CLK — — IOC Y CLK
PIC16(L)F1508/9 TABLE OF CONTENTS 1.0 Device Overview .......................................................................................................................................................................... 7 2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 13 3.0 Memory Organization ..............................................................................
PIC16(L)F1508/9 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.
PIC16(L)F1508/9 1.0 DEVICE OVERVIEW The PIC16(L)F1508/9 are described within this data sheet. The block diagram of these devices are shown in Figure 1-1, the available peripherals are shown in Table 1-1, and the pin out descriptions are shown in Tables 1-2 .
PIC16(L)F1508/9 FIGURE 1-1: PIC16(L)F1508/9 BLOCK DIAGRAM Rev. 10-000039A 8/1/2013 Program Flash Memory RAM PORTA OSC2/CLKOUT Timing Generation PORTB CPU OSC1/CLKIN INTRC Oscillator (Note 3) PORTC MCLR MSSP1 CWG1 TMR2 NCO1 TMR1 CLC4 TMR0 CLC3 CLC2 C2 C1 CLC1 Temp Indicator PWM4 ADC 10-bit PWM3 DAC PWM2 FVR PWM1 EUSART Note 1: See applicable chapters for more information on peripherals. 2: See Table 1-1 for peripherals available on specific devices. 3: See Figure 2-1.
PIC16(L)F1508/9 TABLE 1-2: PIC16(L)F1508/9 PINOUT DESCRIPTION Name RA0/AN0/C1IN+/DAC1OUT1/ ICSPDAT/ICDDAT RA1/AN1/CLC4IN1/VREF+/ C1IN0-/C2IN0-/ICSPCLK/ ICDCLK RA2/AN2/C1OUT/DAC1OUT2/ T0CKI/INT/PWM3/CLC1/ CWG1FLT RA3/CLC1IN0/VPP/T1G(1)/SS(1)/ MCLR RA4/AN3/SOSCO/ CLKOUT/T1G RA5/CLKIN/T1CKI/NCO1CLK/ SOSCI Function Input Type RA0 TTL AN0 AN Output Type Description CMOS General purpose I/O. — ADC Channel input. C1IN+ AN — Comparator positive input.
PIC16(L)F1508/9 TABLE 1-2: PIC16(L)F1508/9 PINOUT DESCRIPTION (CONTINUED) Name RB4/AN10/CLC3IN0/SDA/SDI RB5/AN11/CLC4IN0/RX/DT RB6/SCL/SCK RB7/CLC3/TX/CK RC0/AN4/CLC2/C2IN+ RC1/AN5/C1IN1-/C2IN1-/PWM4/ NCO1 RC2/AN6/C1IN2-/C2IN2- RC3/AN7/C1IN3-/C2IN3-/PWM2/ CLC2IN0 RC4/C2OUT/CLC2IN1/CLC4/ CWG1B Function Input Type RB4 TTL Output Type Description CMOS General purpose I/O. AN10 AN — ADC Channel input. CLC3IN0 ST — Configurable Logic Cell source input.
PIC16(L)F1508/9 TABLE 1-2: PIC16(L)F1508/9 PINOUT DESCRIPTION (CONTINUED) Name RC5/PWM1/CLC1(1)/ CWG1A RC6/AN8/NCO1(1)/CLC3IN1/ SS Function Input Type RC5 TTL Output Type Description CMOS General purpose I/O. PWM1 — CMOS PWM output. CLC1 — CMOS Configurable Logic Cell source output. CWG1A — CMOS CWG primary output. RC6 TTL CMOS General purpose I/O. AN8 AN NCO1 — CLC3IN1 ST — Configurable Logic Cell source input. SS ST — Slave Select input.
PIC16(L)F1508/9 NOTES: DS40001609C-page 12 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 2.0 ENHANCED MID-RANGE CPU This family of devices contain an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, Indirect, and Relative addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory.
PIC16(L)F1508/9 2.1 Automatic Interrupt Context Saving During interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. This saves stack space and user code. See Section 7.5 “Automatic Context Saving”, for more information. 2.2 16-Level Stack with Overflow and Underflow These devices have a hardware stack memory 15 bits wide and 16 words deep.
PIC16(L)F1508/9 3.0 MEMORY ORGANIZATION These devices contain the following types of memory: • Program Memory - Configuration Words - Device ID - User ID - Flash Program Memory • Data Memory - Core Registers - Special Function Registers - General Purpose RAM - Common RAM TABLE 3-1: The following features are associated with access and control of program memory and data memory: • PCL and PCLATH • Stack • Indirect Addressing 3.
PIC16(L)F1508/9 FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR PIC16(L)F1508 FIGURE 3-2: PROGRAM MEMORY MAP AND STACK FOR PIC16(L)F1509 Rev. 10-000040B 7/30/2013 Rev.
PIC16(L)F1508/9 3.1.1 READING PROGRAM MEMORY AS DATA There are two methods of accessing constants in program memory. The first method is to use tables of RETLW instructions. The second method is to set an FSR to point to the program memory. 3.1.1.1 RETLW Instruction The RETLW instruction can be used to provide access to tables of constants. The recommended way to create such a table is shown in Example 3-1.
PIC16(L)F1508/9 3.2 Data Memory Organization The data memory is partitioned in 32 memory banks with 128 bytes in a bank. Each bank consists of (Figure 3-3): • • • • 12 core registers 20 Special Function Registers (SFR) Up to 80 bytes of General Purpose RAM (GPR) 16 bytes of common RAM The active bank is selected by writing the bank number into the Bank Select Register (BSR). Unimplemented memory will read as ‘0’.
PIC16(L)F1508/9 3.2.1.1 STATUS Register The STATUS register, shown in Register 3-1, contains: • the arithmetic status of the ALU • the Reset status The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable.
PIC16(L)F1508/9 3.2.2 SPECIAL FUNCTION REGISTER The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). The registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet. 3.2.
2011-2013 Microchip Technology Inc.
PIC16(L)F1508 MEMORY MAP, BANK 1-7 BANK 0 000h BANK 1 080h Core Registers (Table 3-2) 00Bh 00Ch 00Dh 00Eh 00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh BANK 2 100h Core Registers (Table 3-2) BANK 3 180h Core Registers (Table 3-2) PORTA PORTB PORTC — — PIR1 PIR2 PIR3 — TMR0 TMR1L TMR1H T1CON T1GCON TMR2 PR2 T2CON 08Bh 08Ch 08Dh 08Eh 08Fh 090h 091h 092h 093h 094h 095h 096h 097h 098h 099h 09Ah 09Bh 09Ch TRISA TRISB TRISC — — PIE1 PIE2 PIE3 — OPTION_REG PCON WDTC
2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 MEMORY MAP, BANK 24-31 BANK 24 C00h BANK 25 C80h Core Registers (Table 3-2) C0Bh C0Ch C0Dh C0Eh C0Fh C10h C11h C12h C13h C14h C15h C16h C17h C18h C19h C1Ah C1Bh C1Ch C1Dh C1Eh C1Fh C20h — — — — — — — — — — — — — — — — — — — — Core Registers (Table 3-2) C8Bh C8Ch C8Dh C8Eh C8Fh C90h C91h C92h C93h C94h C95h C96h C97h C98h C99h C9Ah C9Bh C9Ch C9Dh C9Eh C9Fh CA0h Unimplemented Read as ‘0’ C6Fh C70h 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 TABLE 3-7: PIC16(L)F1508/9 MEMORY MAP, BANK 30-31 Bank 30 F0Ch F0Dh F0Eh F0Fh F10h F11h F12h F13h F14h F15h F16h F17h F18h F19h F1Ah F1Bh F1Ch F1Dh F1Eh F1Fh F20h F21h F22h F23h F24h F25h F26h F27h F28h F29h F2Ah F2Bh F2Ch F2Dh F2Eh F2Fh F30h F6Fh Legend: — — — CLCDATA CLC1CON CLC1POL CLC1SEL0 CLC1SEL1 CLC1GLS0 CLC1GLS1 CLC1GLS2 CLC1GLS3 CLC2CON CLC2POL CLC2SEL0 CLC2SEL1 CLC2GLS0 CLC2GLS1 CLC2GLS2 CLC2GLS3 CLC3CON CLC3POL CLC3SEL0 CLC3SEL1 CLC3GLS0 CLC3GLS1 CLC3GLS2 CLC3GLS3 CLC4CON CLC4
PIC16(L)F1508/9 3.2.6 CORE FUNCTION REGISTERS SUMMARY The Core Function registers listed in Table 3-8 can be addressed from any Bank.
PIC16(L)F1508/9 TABLE 3-9: Address SPECIAL FUNCTION REGISTER SUMMARY Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 0 00Ch PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --xx xxxx 00Dh PORTB RB7 RB6 RB5 RB4 — — — — xxxx ---- xxxx ---- 00Eh PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx xxxx xxxx 00Fh — Unimplemented — — 010h — Unimplemented — — 011h PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF — TMR2IF
PIC16(L)F1508/9 TABLE 3-9: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 2 10Ch LATA — — LATA5 LATA4 — LATA2 LATA1 LATA0 --xx -xxx --uu -uuu 10Dh LATB LATB7 LATB6 LATB5 LATB4 — — — — xxxx ---- uuuu ---- 10Eh LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx uuuu uuuu 10Fh — Unimplemented — — 110h — Unimplemented — — 111h CM1CON0
PIC16(L)F1508/9 TABLE 3-9: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 4 20Ch WPUA — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 --11 1111 --11 1111 20Dh WPUB WPUB7 WPUB6 WPUB5 WPUB4 — — — — 1111 ---- 1111 ---- 20Eh to 210h — Unimplemented 211h SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 212h SSP1ADD ADD<7:0> 0000 0000
PIC16(L)F1508/9 TABLE 3-9: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on POR, BOR Value on all other Resets Unimplemented — — Unimplemented — — Unimplemented — — Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bank 10 50Ch to 51Fh — Bank 11 58Ch to 59Fh — Bank 12 60Ch to 610h — 611h PWM1DCL 612h PWM1DCH 613h PWM1CON0 614h PWM2DCL 615h PWM2DCH 616h PWM2CON0 617h PWM3DCL 618h PWM3DCH 619h PWM3CON0 61Ah PWM4DCL 61Bh PWM4DCH 61Ch PWM4CON0
PIC16(L)F1508/9 TABLE 3-9: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on POR, BOR Value on all other Resets Unimplemented — — Unimplemented — — Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Banks 14-29 x0Ch/ x8Ch — x1Fh/ x9Fh — Bank 30 F0Ch to F0Eh — F0Fh CLCDATA — — — — F10h CLC1CON LC1EN LC1OE LC1OUT LC1INTP F11h CLC1POL LC1POL — — — F12h CLC1SEL0 — LC1D2S<2:0> — LC1D1S<2:0> F13h CLC1SEL1 — LC1D4S<2:0> — LC1D3S<2:0> F14h CLC1GLS0
PIC16(L)F1508/9 TABLE 3-9: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets — — Bank 31 F8Ch — FE3h — FE4h STATUS_ Unimplemented — — — — — Z_SHAD DC_SHAD C_SHAD ---- -xxx ---- -uuu SHAD FE5h WREG_ Working Register Shadow xxxx xxxx uuuu uuuu SHAD FE6h BSR_ — — — Bank Select Register Shadow ---x xxxx ---u uuuu SHAD FE7h PCLATH_ — Program Counter Latch High Register S
PIC16(L)F1508/9 3.3 PCL and PCLATH 3.3.2 The Program Counter (PC) is 15 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<14:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 3-4 shows the five situations for the loading of the PC. FIGURE 3-4: LOADING OF PC IN DIFFERENT SITUATIONS Rev.
PIC16(L)F1508/9 3.4 Stack 3.4.1 All devices have a 16-level x 15-bit wide hardware stack (refer to Figures 3-5 through 3-8). The stack space is not part of either program or data space. The PC is PUSHed onto the stack when CALL or CALLW instructions are executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation.
PIC16(L)F1508/9 FIGURE 3-6: ACCESSING THE STACK EXAMPLE 2 Rev. 10-000043B 7/30/2013 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A This figure shows the stack configuration after the first CALL or a single interrupt. If a RETURN instruction is executed, the return address will be placed in the Program Counter and the Stack Pointer decremented to the empty state (0x1F). 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 TOSH:TOSL FIGURE 3-7: 0x00 Return Address STKPTR = 0x00 ACCESSING THE STACK EXAMPLE 3 Rev.
PIC16(L)F1508/9 FIGURE 3-8: ACCESSING THE STACK EXAMPLE 4 Rev. 10-000043D 7/30/2013 TOSH:TOSL 3.4.
PIC16(L)F1508/9 FIGURE 3-9: INDIRECT ADDRESSING Rev. 10-000044A 7/30/2013 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x1000 0x0FFF Reserved 0x1FFF 0x2000 Linear Data Memory 0x29AF 0x29B0 Reserved FSR Address Range 0x7FFF 0x8000 0x0000 Program Flash Memory 0xFFFF Note: 0x7FFF Not all memory regions are completely implemented. Consult device memory tables for memory limits. 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 3.5.1 TRADITIONAL DATA MEMORY The traditional data memory is a region from FSR address 0x000 to FSR address 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers. FIGURE 3-10: TRADITIONAL DATA MEMORY MAP Rev.
PIC16(L)F1508/9 3.5.2 LINEAR DATA MEMORY The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the banks. Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the FSR beyond one bank will go directly to the GPR memory of the next bank.
PIC16(L)F1508/9 NOTES: DS40001609C-page 40 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 4.0 DEVICE CONFIGURATION Device configuration consists of Configuration Words, Code Protection and Device ID. 4.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h. Note: The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers and programmers.
PIC16(L)F1508/9 4.
PIC16(L)F1508/9 REGISTER 4-1: bit 2-0 Note 1: 2: 3: CONFIG1: CONFIGURATION WORD 1 (CONTINUED) FOSC<2:0>: Oscillator Selection bits 111 = ECH:External clock, High-Power mode: on CLKIN pin 110 = ECM: External clock, Medium-Power mode: on CLKIN pin 101 = ECL: External clock, Low-Power mode: on CLKIN pin 100 = INTOSC oscillator: I/O function on CLKIN pin 011 = EXTRC oscillator: External RC circuit connected to CLKIN pin 010 = HS oscillator: High-speed crystal/resonator connected between OSC1 and OSC2 pins 00
PIC16(L)F1508/9 REGISTER 4-2: CONFIG2: CONFIGURATION WORD 2 R/P-1 (1) LVP R/P-1 DEBUG R/P-1 (3) LPBOR R/P-1 (2) BORV R/P-1 U-1 STVREN — bit 13 bit 8 U-1 U-1 U-1 U-1 U-1 U-1 — — — — — — R/P-1 R/P-1 WRT<1:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase bit 13 LVP: Low-Voltage Programming Enable bit(1) 1 = Low-voltage programming enabled 0 = High-
PIC16(L)F1508/9 4.3 Code Protection Code protection allows the device to be protected from unauthorized access. Internal access to the program memory is unaffected by any code protection setting. 4.3.1 PROGRAM MEMORY PROTECTION The entire program memory space is protected from external reads and writes by the CP bit in Configuration Words. When CP = 0, external reads and writes of program memory are inhibited and a read will return all ‘0’s.
PIC16(L)F1508/9 4.6 Device ID and Revision ID The memory location 8006h is where the Device ID and Revision ID are stored. The upper nine bits hold the Device ID. The lower five bits hold the Revision ID. See Section 10.4 “User ID, Device ID and Configuration Word Access” for more information on accessing these memory locations. Development tools, such as device programmers and debuggers, may be used to read the Device ID and Revision ID. 4.
PIC16(L)F1508/9 5.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR) 5.1 Overview The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 5-1 illustrates a block diagram of the oscillator module. Clock sources can be supplied from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits.
PIC16(L)F1508/9 FIGURE 5-1: SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM Rev.
PIC16(L)F1508/9 5.2 Clock Source Types Clock sources can be classified as external, internal or peripheral. External clock sources rely on external circuitry for the clock source to function. Examples are: oscillator modules (ECH, ECM, ECL modes), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (EXTRC) mode circuits. Internal clock sources are contained within the oscillator module.
PIC16(L)F1508/9 FIGURE 5-3: QUARTZ CRYSTAL OPERATION (LP, XT OR HS MODE) FIGURE 5-4: CERAMIC RESONATOR OPERATION (XT OR HS MODE) Rev. 10-000060A 7/30/2013 Rev. 10-000059A 7/30/2013 PIC® MCU Ceramic Resonator PIC® MCU OSC1/CLKIN OSC1/CLKIN C1 C1 C2 To Internal Logic Quartz Crystal RF(2) RS(1) OSC2/CLKOUT RP(3) C2 A series resistor (Rs) may be required for quartz crystals with low drive level. 2: Sleep Note 1: Quartz crystal characteristics vary according to type, package and manufacturer.
PIC16(L)F1508/9 5.2.1.4 5.2.1.5 Secondary Oscillator External RC Mode The secondary oscillator is a separate crystal oscillator that is associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the SOSCO and SOSCI device pins. The External Resistor-Capacitor (EXTRC) mode supports the use of an external RC circuit.
PIC16(L)F1508/9 5.2.2 INTERNAL CLOCK SOURCES The device may be configured to use the internal oscillator block as the system clock by performing one of the following actions: • Program the FOSC<2:0> bits in Configuration Words to select the INTOSC clock source, which will be used as the default system clock upon a device Reset. • Write the SCS<1:0> bits in the OSCCON register to switch the system clock source to the internal oscillator during run-time. See Section 5.
PIC16(L)F1508/9 5.2.2.4 Peripheral Clock Sources 5.2.2.5 The clock sources described in this chapter and the Timer’s are available to different peripherals. Table 5-1 lists the clocks and timers available for each peripheral.
PIC16(L)F1508/9 FIGURE 5-7: INTERNAL OSCILLATOR SWITCH TIMING HFINTOSC LFINTOSC (FSCM and WDT disabled) HFINTOSC Oscillator Delay(1) 2-cycle Sync Running LFINTOSC 0 IRCF <3:0> 0 System Clock LFINTOSC (Either FSCM or WDT enabled) HFINTOSC HFINTOSC 2-cycle Sync Running LFINTOSC 0 IRCF <3:0> 0 System Clock LFINTOSC HFINTOSC LFINTOSC turns off unless WDT or FSCM is enabled(2) LFINTOSC Oscillator Delay(1) 2-cycle Sync Running HFINTOSC IRCF <3:0> =0 0 System Clock Note 1: 2:
PIC16(L)F1508/9 5.3 Clock Switching The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bits of the OSCCON register. The following clock sources can be selected using the SCS bits: • Default system oscillator determined by FOSC bits in Configuration Words • Secondary oscillator 32 kHz crystal • Internal Oscillator Block (INTOSC) 5.3.
PIC16(L)F1508/9 5.4 Two-Speed Clock Start-up Mode Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device.
PIC16(L)F1508/9 FIGURE 5-8: TWO-SPEED START-UP INTOSC TOST OSC1 0 1 1022 1023 OSC2 Program Counter PC - N PC PC + 1 System Clock 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 5.5 Fail-Safe Clock Monitor 5.5.3 The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator or external clock fail. If an oscillator mode is selected, the FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. When an external clock mode is selected, the FSCM can detect failure as soon as the device is released from Reset. FSCM is enabled by setting the FCMEN bit in the Configuration Words.
PIC16(L)F1508/9 SCS<1:0> = 00: SCS<1:0> = 01: Change the SCS bits in the OSCCON register to select the FOSC Configuration Word clock selection. Since the OST is not applicable with external clocks, the clock module will immediately switch to the external clock, and the fail-safe condition will be cleared. If the Fail-Safe condition still exists, the OSFIF bit will again be set by hardware. 5.5.3.
PIC16(L)F1508/9 5.
PIC16(L)F1508/9 REGISTER 5-2: OSCSTAT: OSCILLATOR STATUS REGISTER R-1/q U-0 R-q/q R-0/q U-0 U-0 R-0/q R-0/q SOSCR — OSTS HFIOFR — — LFIOFR HFIOFS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Conditional bit 7 SOSCR: Secondary Oscillator Ready bit If T1OSCEN = 1: 1 = Secondary oscillator is ready 0 = S
PIC16(L)F1508/9 TABLE 5-4: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page OSCCON — OSCSTAT SOSCR — OSTS HFIOFR — — LFIOFR HFIOFS 61 PIE2 OSFIE C2IE C1IE — BCL1IE NCO1IE — — 78 PIR2 OSFIF — BCL1IF NCO1IF — — 81 T1OSCEN T1SYNC — TMR1ON 173 T1CON IRCF<3:0> C2IF TMR1CS<1:0> C1IF — T1CKPS<1:0> SCS<1:0> 60 Legend: — = unimplemented location, read as ‘0’.
PIC16(L)F1508/9 6.0 RESETS There are multiple ways to reset this device: • • • • • • • • • Power-On Reset (POR) Brown-Out Reset (BOR) Low-Power Brown-Out Reset (LPBOR) MCLR Reset WDT Reset RESET instruction Stack Overflow Stack Underflow Programming mode exit To allow VDD to stabilize, an optional power-up timer can be enabled to extend the Reset time after a BOR or POR event. A simplified block diagram of the On-chip Reset Circuit is shown in Figure 6-1.
PIC16(L)F1508/9 6.1 Power-On Reset (POR) 6.2 Brown-Out Reset (BOR) The POR circuit holds the device in Reset until VDD has reached an acceptable level for minimum operation. Slow rising VDD, fast operating speeds or analog performance may require greater than minimum VDD. The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met. The BOR circuit holds the device in Reset when VDD reaches a selectable minimum level.
PIC16(L)F1508/9 FIGURE 6-2: BROWN-OUT SITUATIONS VDD VBOR Internal Reset TPWRT(1) VDD VBOR Internal Reset < TPWRT TPWRT(1) VDD VBOR Internal Reset Note 1: 6.3 TPWRT(1) TPWRT delay only if PWRTE bit is programmed to ‘0’.
PIC16(L)F1508/9 6.4 Low-Power Brown-Out Reset (LPBOR) The Low-Power Brown-Out Reset (LPBOR) operates like the BOR to detect low voltage conditions on the VDD pin. When too low of a voltage is detected, the device is held in Reset. When this occurs, a register bit (BOR) is changed to indicate that a BOR Reset has occurred. The BOR bit in PCON is used for both BOR and the LPBOR. Refer to Register 6-2.
PIC16(L)F1508/9 FIGURE 6-3: RESET START-UP SEQUENCE Rev. 10-000032A 7/30/2013 VDD Internal POR TPWRT Power-up Timer MCLR Internal RESET Int. Oscillator FOSC Begin Execution code execution (1) Internal Oscillator, PWRTEN = 0 code execution (1) Internal Oscillator, PWRTEN = 1 VDD Internal POR TPWRT Power-up Timer MCLR Internal RESET Ext.
PIC16(L)F1508/9 6.12 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON registers are updated to indicate the cause of the Reset. Table 6-3 and Table 6-4 show the Reset conditions of these registers.
PIC16(L)F1508/9 6.13 Power Control (PCON) Register The Power Control (PCON) register contains flag bits to differentiate between a: • • • • • • • Power-On Reset (POR) Brown-Out Reset (BOR) Reset Instruction Reset (RI) MCLR Reset (RMCLR) Watchdog Timer Reset (RWDT) Stack Underflow Reset (STKUNF) Stack Overflow Reset (STKOVF) The PCON register bits are shown in Register 6-2. 6.
PIC16(L)F1508/9 TABLE 6-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BORCON SBOREN BORFS — — — — — BORRDY 65 PCON STKOVF STKUNF — RWDT RMCLR RI POR BOR 69 STATUS — — — TO PD Z DC C 19 WDTCON — — SWDTEN 91 WDTPS<4:0> Legend: — = unimplemented bit, reads as ‘0’. Shaded cells are not used by Resets.
PIC16(L)F1508/9 7.0 INTERRUPTS The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode. This chapter contains the following information for Interrupts: • • • • • Operation Interrupt Latency Interrupts During Sleep INT Pin Automatic Context Saving Many peripherals produce interrupts. Refer to the corresponding chapters for details.
PIC16(L)F1508/9 7.1 Operation Interrupts are disabled upon any device Reset. They are enabled by setting the following bits: • GIE bit of the INTCON register • Interrupt Enable bit(s) for the specific interrupt event(s) • PEIE bit of the INTCON register (if the Interrupt Enable bit of the interrupt event is contained in the PIE1, PIE2 and PIE3 registers) 7.
PIC16(L)F1508/9 FIGURE 7-2: INTERRUPT LATENCY Fosc Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKR Interrupt Sampled during Q1 Interrupt GIE PC Execute PC-1 PC 1-Cycle Instruction at PC PC+1 0004h 0005h NOP NOP Inst(0004h) PC+1/FSR ADDR New PC/ PC+1 0004h 0005h Inst(PC) NOP NOP Inst(0004h) FSR ADDR PC+1 PC+2 0004h 0005h INST(PC) NOP NOP NOP Inst(0004h) Inst(0005h) FSR ADDR PC+1 0004h 0005h INST(PC) NOP NOP Inst(00
PIC16(L)F1508/9 FIGURE 7-3: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 FOSC CLKOUT (3) INT pin (1) (1) INTF Interrupt Latency (2) (4) GIE INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: PC Inst (PC) Inst (PC – 1) PC + 1 Inst (PC + 1) Inst (PC) PC + 1 — Forced NOP 0004h 0005h Inst (0004h) Inst (0005h) Forced NOP Inst (0004h) INTF flag is sampled here (every Q1).
PIC16(L)F1508/9 7.3 Interrupts During Sleep Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction.
PIC16(L)F1508/9 7.
PIC16(L)F1508/9 REGISTER 7-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 TMR1GIE ADIE RCIE TXIE SSP1IE — TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit 1 = Enables the Timer1 gate acqui
PIC16(L)F1508/9 REGISTER 7-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 U-0 U-0 OSFIE C2IE C1IE — BCL1IE NCO1IE — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSFIE: Oscillator Fail Interrupt Enable bit 1 = Enables the Oscillator Fail interrupt 0 = Dis
PIC16(L)F1508/9 REGISTER 7-4: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — — — CLC4IE CLC3IE CLC2IE CLC1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 CLC4IE: Configurable Logic Block 4 Interrupt Enable bit 1 =
PIC16(L)F1508/9 REGISTER 7-5: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 TMR1GIF ADIF RCIF TXIF SSP1IF — TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit 1 = Interrupt is pending 0 = Inter
PIC16(L)F1508/9 REGISTER 7-6: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 U-0 U-0 OSFIF C2IF C1IF — BCL1IF NCO1IF — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSFIF: Oscillator Fail Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pend
PIC16(L)F1508/9 REGISTER 7-7: PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — — — CLC4IF CLC3IF CLC2IF CLC1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 CLC4IF: Configurable Logic Block 4 Interrupt Flag bit 1 = I
PIC16(L)F1508/9 TABLE 7-1: Name INTCON SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 76 OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PIE1 TMR1GIE ADIE RCIE TXIE PSA PS<2:0> SSP1IE — TMR2IE 163 TMR1IE 77 PIE2 OSFIE C2IE C1IE — BCL1IE NCO1IE — — 78 PIE3 — — — — CLC4IE CLC3IE CLC2IE CLC1IE 79 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF — TMR2IF TMR1IF 80
PIC16(L)F1508/9 NOTES: DS40001609C-page 84 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 8.0 POWER-DOWN MODE (SLEEP) The Power-down mode is entered by executing a SLEEP instruction. Upon entering Sleep mode, the following conditions exist: 1. WDT will be cleared but keeps running, if enabled for operation during Sleep. PD bit of the STATUS register is cleared. TO bit of the STATUS register is set. CPU clock is disabled. 31 kHz LFINTOSC is unaffected and peripherals that operate from it may continue operation in Sleep.
PIC16(L)F1508/9 FIGURE 8-1: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKIN(1) T1OSC(3) CLKOUT(2) Interrupt Latency (4) Interrupt flag GIE bit (INTCON reg.) Instruction Flow PC Instruction Fetched Instruction Executed Note 8.
PIC16(L)F1508/9 8.
PIC16(L)F1508/9 NOTES: DS40001609C-page 88 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 9.0 WATCHDOG TIMER (WDT) The Watchdog Timer is a system timer that generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The Watchdog Timer is typically used to recover the system from unexpected events.
PIC16(L)F1508/9 9.1 Independent Clock Source 9.3 The WDT derives its time base from the 31 kHz LFINTOSC internal oscillator. Time intervals in this chapter are based on a nominal interval of 1 ms. See Section 29.0 “Electrical Specifications” for the LFINTOSC tolerances. 9.2 The Watchdog Timer module has four operating modes controlled by the WDTE<1:0> bits in Configuration Words. See Table 9-1. 9.2.1 WDT IS ALWAYS ON When the WDTE bits of Configuration Words are set to ‘11’, the WDT is always on.
PIC16(L)F1508/9 9.
PIC16(L)F1508/9 TABLE 9-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER Bit 7 OSCCON Bit 6 — Bit 5 Bit 4 Bit 3 IRCF<3:0> STKUNF — RWDT STATUS — — — TO WDTCON — — Legend: CONFIG1 Legend: Bit 0 SCS<1:0> RMCLR RI POR PD Z DC WDTPS<4:0> Register on Page 60 BOR 69 C 19 SWDTEN 91 x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Watchdog Timer.
PIC16(L)F1508/9 10.0 FLASH PROGRAM MEMORY CONTROL The Flash program memory is readable and writable during normal operation over the full VDD range. Program memory is indirectly addressed using Special Function Registers (SFRs).
PIC16(L)F1508/9 TABLE 10-1: FLASH MEMORY ORGANIZATION BY DEVICE Device PIC16(L)F1509 PIC16(L)F1508 10.2.1 Row Erase (words) 32 FIGURE 10-1: FLASH PROGRAM MEMORY READ FLOWCHART Write Latches (words) 32 READING THE FLASH PROGRAM MEMORY Rev. 10-000046A 7/30/2013 Start Read Operation Select Program or Configuration Memory (CFGS) To read a program memory location, the user must: 1. 2. 3. Write the desired address to the PMADRH:PMADRL register pair. Clear the CFGS bit of the PMCON1 register.
PIC16(L)F1508/9 FIGURE 10-2: FLASH PROGRAM MEMORY READ CYCLE EXECUTION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC Flash ADDR Flash Data PC + 1 INSTR (PC) INSTR(PC - 1) executed here PMADRH,PMADRL INSTR (PC + 1) BSF PMCON1,RD executed here PC +3 PC+3 PMDATH,PMDATL INSTR(PC + 1) instruction ignored Forced NOP executed here PC + 5 PC + 4 INSTR (PC + 3) INSTR(PC + 2) instruction ignored Forced NOP executed here INSTR (PC + 4) INSTR(PC + 3) executed here INSTR
PIC16(L)F1508/9 10.2.2 FLASH MEMORY UNLOCK SEQUENCE The unlock sequence is a mechanism that protects the Flash program memory from unintended self-write programming or erasing.
PIC16(L)F1508/9 10.2.3 ERASING FLASH PROGRAM MEMORY While executing code, program memory can only be erased by rows. To erase a row: 1. 2. 3. 4. 5. Load the PMADRH:PMADRL register pair with any address within the row to be erased. Clear the CFGS bit of the PMCON1 register. Set the FREE and WREN bits of the PMCON1 register. Write 55h, then AAh, to PMCON2 (Flash programming unlock sequence). Set control bit WR of the PMCON1 register to begin the erase operation. See Example 10-2.
PIC16(L)F1508/9 EXAMPLE 10-2: ERASING ONE ROW OF PROGRAM MEMORY Required Sequence ; This row erase routine assumes the following: ; 1. A valid address within the erase row is loaded in ADDRH:ADDRL ; 2.
PIC16(L)F1508/9 10.2.4 WRITING TO FLASH PROGRAM MEMORY Program memory is programmed using the following steps: 1. 2. 3. 4. Load the address in PMADRH:PMADRL of the row to be programmed. Load each write latch with data. Initiate a programming operation. Repeat steps 1 through 3 until all data is written. The following steps should be completed to load the write latches and program a row of program memory. These steps are divided into two parts.
7 BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES 6 0 7 5 4 PMADRH - r9 r8 r7 r6 r5 0 7 PMADRL r4 r3 r2 r1 r0 c4 c3 c2 c1 - 5 - 0 7 PMDATH PMDATL 6 c0 Rev. 10-000004A 7/30/2013 0 8 14 Program Memory Write Latches 5 10 14 PMADRL<4:0> Write Latch #0 00h 14 CFGS = 0 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 FIGURE 10-6: FLASH PROGRAM MEMORY WRITE FLOWCHART Rev. 10-000049A 7/30/2013 Start Write Operation Determine number of words to be written into Program or Configuration Memory. The number of words cannot exceed the number of words per row (word_cnt) Enable Write/Erase Operation (WREN = 1) Load the value to write (PMDATH:PMDATL) Disable Interrupts (GIE = 0) Update the word counter (word_cnt--) Write Latches to Flash (LWLO = 0) Select Program or Config.
PIC16(L)F1508/9 EXAMPLE 10-3: ; ; ; ; ; ; ; WRITING TO FLASH PROGRAM MEMORY (32 WRITE LATCHES) This write routine assumes the following: 1. 64 bytes of data are loaded, starting at the address in DATA_ADDR 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR, stored in little endian format 3. A valid starting address (the Least Significant bits = 00000) is loaded in ADDRH:ADDRL 4.
PIC16(L)F1508/9 10.3 Modifying Flash Program Memory When modifying existing data in a program memory row, and data within that row must be preserved, it must first be read and saved in a RAM image. Program memory is modified using the following steps: 1. 2. 3. 4. 5. 6. 7. Load the starting address of the row to be modified. Read the existing data from the row into a RAM image. Modify the RAM image to contain the new data to be written into program memory.
PIC16(L)F1508/9 10.4 User ID, Device ID and Configuration Word Access Instead of accessing program memory, the User ID’s, Device ID/Revision ID and Configuration Words can be accessed when CFGS = 1 in the PMCON1 register. This is the region that would be pointed to by PC<15> = 1, but not all addresses are accessible. Different access may exist for reads and writes. Refer to Table 10-2.
PIC16(L)F1508/9 10.5 Write Verify It is considered good programming practice to verify that program memory writes agree with the intended value. Since program memory is stored as a full page then the stored program memory contents are compared with the intended data stored in RAM after the last write is complete. FIGURE 10-8: FLASH PROGRAM MEMORY VERIFY FLOWCHART Rev. 10-000051A 7/30/2013 Start Verify Operation This routine assumes that the last row of data written was from an image saved on RAM.
PIC16(L)F1508/9 10.
PIC16(L)F1508/9 REGISTER 10-5: PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER U-1 R/W-0/0 R/W-0/0 R/W/HC-0/0 R/W/HC-x/q(2) R/W-0/0 R/S/HC-0/0 R/S/HC-0/0 —(1) CFGS LWLO FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 Unimplemented: Read as ‘1’ bit 6
PIC16(L)F1508/9 REGISTER 10-6: W-0/0 PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 Program Memory Control Register 2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Flash Memory Unlock Pattern bits To unlock writes, a 55h must be written first, followed by an AAh, before
PIC16(L)F1508/9 11.0 I/O PORTS FIGURE 11-1: GENERIC I/O PORT OPERATION Each port has three standard registers for its operation. These registers are: Rev. 10-000052A 7/30/2013 • TRISx registers (data direction) • PORTx registers (reads the levels on the pins of the device) • LATx registers (output latch) Some ports may have one or more of the following additional registers.
PIC16(L)F1508/9 11.1 Alternate Pin Function The Alternate Pin Function Control (APFCON) register is used to steer specific peripheral input and output functions between different pins. The APFCON register is shown in Register 11-1. For this device family, the following functions can be moved between different pins. • • • • These bits have no effect on the values of any TRIS register. PORT and TRIS overrides will be routed to the correct pin. The unselected pin will be unaffected. SS T1G CLC1 NCO1 11.
PIC16(L)F1508/9 11.3 PORTA Registers 11.3.1 DATA REGISTER PORTA is a 6-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 11-3). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin).
PIC16(L)F1508/9 11.
PIC16(L)F1508/9 REGISTER 11-4: LATA: PORTA DATA LATCH REGISTER U-0 U-0 R/W-x/u R/W-x/u U-0 R/W-x/u R/W-x/u R/W-x/u — — LATA5 LATA4 — LATA2 LATA1 LATA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 LATA<5:4>: RA<5:4> Output Latch Value bits(1) bit 3 Unimplemente
PIC16(L)F1508/9 REGISTER 11-6: WPUA: WEAK PULL-UP PORTA REGISTER U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 WPUA<5:0>: Weak Pull-up Register bits(3) 1 = Pull-up ena
PIC16(L)F1508/9 11.5 11.5.1 PORTB Registers DATA REGISTER PORTB is a 4-bit wide, bidirectional port. The corresponding data direction register is TRISB (Register 11-8). Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., disable the output driver). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). Example 11-1 shows how to initialize an I/O port.
PIC16(L)F1508/9 11.
PIC16(L)F1508/9 REGISTER 11-9: LATB: PORTB DATA LATCH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u U-0 U-0 U-0 U-0 LATB7 LATB6 LATB5 LATB4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 LATB<7:4>: RB<7:4> Output Latch Value bits(1) bit 3-0 Unimplemented: Read as ‘0’ Note 1: Writes to PORTB ar
PIC16(L)F1508/9 REGISTER 11-11: WPUB: WEAK PULL-UP PORTB REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 U-0 U-0 U-0 U-0 WPUB7 WPUB6 WPUB5 WPUB4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 WPUB<7:4>: Weak Pull-up Register bits 1 = Pull-up enabled 0 = Pull-up disabled bit 3-0 Unimplemented: Read a
PIC16(L)F1508/9 11.7 11.7.1 PORTC Registers DATA REGISTER PORTC is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISC (Register 11-13). Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., disable the output driver). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). Example 11-1 shows how to initialize an I/O port.
PIC16(L)F1508/9 11.
PIC16(L)F1508/9 REGISTER 11-15: ANSELC: PORTC ANALOG SELECT REGISTER R/W-1/1 R/W-1/1 U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 ANSC7 ANSC6 — — ANSC3 ANSC2 ANSC1 ANSC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 ANSC<7:6>: Analog Select between Analog or Digital Function on pins RC<7:6>, respectively 1
PIC16(L)F1508/9 NOTES: DS40001609C-page 122 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 12.0 INTERRUPT-ON-CHANGE The PORTA and PORTB pins can be configured to operate as Interrupt-On-Change (IOC) pins. An interrupt can be generated by detecting a signal that has either a rising edge or a falling edge. Any individual port pin, or combination of port pins, can be configured to generate an interrupt.
PIC16(L)F1508/9 FIGURE 12-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM (PORTA EXAMPLE) Rev. 10-000037A 7/30/2013 IOCANx D Q R Q4Q1 edge detect RAx IOCAPx D data bus = 0 or 1 Q write IOCAFx R D S to data bus IOCAFx Q R IOCIE Q2 IOC interrupt to CPU core from all other IOCnFx individual pin detectors FOSC Q1 Q1 Q3 Q2 Q3 Q4 Q4Q1 Q1 Q2 Q2 Q3 Q4 Q4Q1 DS40001609C-page 124 Q4 Q4Q1 Q4Q1 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 12.
PIC16(L)F1508/9 REGISTER 12-4: IOCBP: INTERRUPT-ON-CHANGE PORTB POSITIVE EDGE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 IOCBP7 IOCBP6 IOCBP5 IOCBP4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 IOCBP<7:4>: Interrupt-on-Change PORTB Positive Edge Enable bits 1 = Interrupt-on-Ch
PIC16(L)F1508/9 TABLE 12-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 113 INTCON Name GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 76 IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 125 IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 125 IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 125 IOCBF IOCBF7 IOCBF6 IOCBF5
PIC16(L)F1508/9 NOTES: DS40001609C-page 128 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 13.0 FIXED VOLTAGE REFERENCE (FVR) The ADFVR<1:0> bits of the FVRCON register are used to enable and configure the gain amplifier settings for the reference supplied to the ADC module. Reference Section 15.0 “Analog-to-Digital Converter (ADC) Module” for additional information. The Fixed Voltage Reference (FVR) is a stable voltage reference, independent of VDD, with a nominal output level (VFVR) of 1.024V.
PIC16(L)F1508/9 TABLE 13-1: PERIPHERALS REQUIRING THE FIXED VOLTAGE REFERENCE (FVR) Peripheral HFINTOSC BOR LDO Conditions Description FOSC<2:0> = 010 and IRCF<3:0> = 000x INTOSC is active and device is not in Sleep. BOREN<1:0> = 11 BOR always enabled. BOREN<1:0> = 10 and BORFS = 1 BOR disabled in Sleep mode, BOR Fast Start enabled. BOREN<1:0> = 01 and BORFS = 1 BOR under software control, BOR Fast Start enabled.
PIC16(L)F1508/9 13.
PIC16(L)F1508/9 NOTES: DS40001609C-page 132 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 14.0 TEMPERATURE INDICATOR MODULE FIGURE 14-1: This family of devices is equipped with a temperature circuit designed to measure the operating temperature of the silicon die. The circuit’s range of operating temperature falls between -40°C and +85°C. The output is a voltage that is proportional to the device temperature. The output of the temperature indicator is internally connected to the device ADC. Rev.
PIC16(L)F1508/9 TABLE 14-2: Name FVRCON Legend: SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR Bit 7 Bit 6 Bit 5 Bit 4 FVREN FVRRDY TSEN TSRNG Bit 3 Bit 2 CDAFVR<1:0> Bit 1 Bit 0 ADFVR<1:0> Register on page 118 Shaded cells are unused by the temperature indicator module. DS40001609C-page 134 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 15.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The ADC voltage reference is software selectable to be either internally generated or externally supplied. The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter.
PIC16(L)F1508/9 15.1 ADC Configuration When configuring and using the ADC the following functions must be considered: • • • • • • Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Result formatting 15.1.1 PORT CONFIGURATION The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits. Refer to Section 11.
PIC16(L)F1508/9 TABLE 15-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES ADC Clock Period (TAD) ADC Clock Source Device Frequency (FOSC) ADCS<2:0 > 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz Fosc/2 000 100 ns 125 ns 250 ns 500 ns 2.0 s Fosc/4 100 200 ns 250 ns 500 ns 1.0 s 4.0 s Fosc/8 001 400 ns 500 ns 1.0 s 2.0 s 8.0 s Fosc/16 101 800 ns 1.0 s 2.0 s 4.0 s 16.0 s Fosc/32 010 1.6 s 2.0 s 4.0 s 8.0 s 32.0 s Fosc/64 110 3.2 s 4.0 s 8.0 s 16.
PIC16(L)F1508/9 15.1.5 INTERRUPTS 15.1.6 The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. RESULT FORMATTING The 10-bit ADC conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON1 register controls the output format.
PIC16(L)F1508/9 15.2 15.2.1 ADC Operation STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a ‘1’. Setting the GO/ DONE bit of the ADCON0 register to a ‘1’ will start the Analog-to-Digital conversion. Note: 15.2.2 The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 15.2.6 “ADC Conversion Procedure”. COMPLETION OF A CONVERSION 15.2.4 ADC OPERATION DURING SLEEP The ADC module can operate during Sleep.
PIC16(L)F1508/9 15.2.6 ADC CONVERSION PROCEDURE This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. 2. 3. 4. 5. 6. 7. 8.
PIC16(L)F1508/9 15.
PIC16(L)F1508/9 REGISTER 15-2: R/W-0/0 ADCON1: ADC CONTROL REGISTER 1 R/W-0/0 ADFM R/W-0/0 R/W-0/0 ADCS<2:0> U-0 U-0 — — R/W-0/0 bit 7 R/W-0/0 ADPREF<1:0> bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: ADC Result Format Select bit 1 = Right justified.
PIC16(L)F1508/9 REGISTER 15-3: R/W-0/0 ADCON2: ADC CONTROL REGISTER 2 R/W-0/0 R/W-0/0 TRIGSEL<3:0> R/W-0/0 (1) U-0 U-0 U-0 U-0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 TRIGSEL<3:0>: Auto-Conversion Trigger Selection bits(1) 0000 = No auto-conversion trigger selected 0001 = Reserved 0010 =
PIC16(L)F1508/9 REGISTER 15-4: R/W-x/u ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ADRES<9:2>: ADC Result Register bits Upper eight bits of 10-bit conversion result REGISTER 15-5: R/W-x/u
PIC16(L)F1508/9 REGISTER 15-6: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — — — — — R/W-x/u R/W-x/u ADRES<9:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Reserved: Do not use.
PIC16(L)F1508/9 15.4 ADC Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 15-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), refer to Figure 15-4.
PIC16(L)F1508/9 FIGURE 15-4: ANALOG INPUT MODEL Rev. 10-000070A 8/2/2013 VDD RS Analog Input pin VT § 0.6V RIC 1K Sampling switch SS RSS ILEAKAGE(1) VA Legend: CHOLD CPIN ILEAKAGE RIC RSS SS VT Note 1: FIGURE 15-5: CPIN 5pF CHOLD = 10 pF VT § 0.
PIC16(L)F1508/9 TABLE 15-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH ADC Bit 7 ADCON0 — ADCON1 ADFM ADCON2 Bit 6 Bit 5 TRIGSEL<3:0> ADC Result Register High ADRESL ADC Result Register Low — Bit 3 Bit 2 — — ADPREF<1:0> — — — CHS<4:0> ADCS<2:0> ADRESH ANSELA Bit 4 Bit 1 Bit 0 GO/DONE ADON — Register on Page 141 142 143 144, 145 144, 145 — — ANSA4 — ANSA2 ANSA1 ANSA0 113 ANSELB — — ANSB5 ANSB4 — — — — 117 ANSELC ANSC7 ANSC6 — — ANSC3 ANSC2 ANSC1 ANSC0 121
PIC16(L)F1508/9 16.0 5-BIT DIGITAL-TO-ANALOG CONVERTER (DAC) MODULE The Digital-to-Analog Converter supplies a variable voltage reference, ratiometric with the input source, with 32 selectable output levels.
PIC16(L)F1508/9 16.1 Output Voltage Selection The DAC has 32 voltage level ranges. The 32 levels are set with the DACR<4:0> bits of the DACxCON1 register. The DAC output voltage can be determined by using Equation 16-1. 16.2 Ratiometric Output Level The DAC output value is derived using a resistor ladder with each end of the ladder tied to a positive and negative voltage reference input source. If the voltage of either input source fluctuates, a similar fluctuation will result in the DAC output value.
PIC16(L)F1508/9 16.
PIC16(L)F1508/9 NOTES: DS40001609C-page 152 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 17.0 COMPARATOR MODULE 17.1 Comparator Overview Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. Comparators are very useful mixed signal building blocks because they provide analog functionality independent of program execution.
PIC16(L)F1508/9 FIGURE 17-2: SINGLE COMPARATOR VIN+ + VIN- – Output VINVIN+ • • • • CxIN+ analog pin DAC1_output FVR_buffer2 VSS See Section 13.0 “Fixed Voltage Reference (FVR)” for more information on the Fixed Voltage Reference module. See Section 16.0 “5-Bit Digital-to-Analog Converter (DAC) Module” for more information on the DAC input signal. Any time the comparator is disabled (CxON = 0), all comparator inputs are disabled. 17.2.3 Output Note: 17.
PIC16(L)F1508/9 17.2.5 COMPARATOR OUTPUT POLARITY Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by setting the CxPOL bit of the CMxCON0 register. Clearing the CxPOL bit results in a non-inverted output. Table 17-2 shows the output state versus input conditions, including polarity control. TABLE 17-2: COMPARATOR OUTPUT STATE VS.
PIC16(L)F1508/9 FIGURE 17-4: ANALOG INPUT MODEL VDD Rs < 10K Analog Input pin VT 0.6V RIC To Comparator VA CPIN 5 pF VT 0.6V ILEAKAGE(1) Vss Legend: CPIN = Input Capacitance ILEAKAGE = Leakage Current at the pin due to various junctions = Interconnect Resistance RIC = Source Impedance RS VA = Analog Voltage = Threshold Voltage VT Note 1: DS40001609C-page 156 See Section 29.0 “Electrical Specifications”. 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 17.4 Comparator Hysteresis A selectable amount of separation voltage can be added to the input pins of each comparator to provide a hysteresis function to the overall operation. Hysteresis is enabled by setting the CxHYS bit of the CMxCON0 register. The associated interrupt flag bit, CxIF bit of the PIR2 register, must be cleared in software. If another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence. Note: See Section 29.
PIC16(L)F1508/9 17.
PIC16(L)F1508/9 REGISTER 17-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1 R/W-0/0 R/W-0/0 CxINTP CxINTN R/W-0/0 R/W-0/0 CxPCH<1:0> U-0 R/W-0/0 R/W-0/0 R/W-0/0 CxNCH<2:0> — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CxINTP: Comparator Interrupt on Positive Going Edge Enable bits 1 = The CxIF interrupt f
PIC16(L)F1508/9 TABLE 17-3: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 113 Name ANSELC ANSC7 ANSC6 — — ANSC3 ANSC2 ANSC1 ANSC0 121 CM1CON0 C1ON C1OUT C1OE C1POL — C1SP C1HYS C1SYNC 158 CM2CON0 C2ON C2OUT C2OE C2POL — C2SP C2HYS C2SYNC 158 CM1CON1 C1NTP C1INTN CM2CON1 C2NTP C2INTN — — — — — DAC1CON0 DACEN — DACOE1 DACOE2 — DAC1
PIC16(L)F1508/9 18.0 TIMER0 MODULE 18.1.2 In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin.
PIC16(L)F1508/9 18.1.3 SOFTWARE PROGRAMMABLE PRESCALER A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION_REG register. Note: The Watchdog Timer (WDT) uses its own independent prescaler. There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION_REG register.
PIC16(L)F1508/9 18.
PIC16(L)F1508/9 NOTES: DS40001609C-page 164 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 19.
PIC16(L)F1508/9 19.1 Timer1 Operation 19.2 The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and increments on every selected edge of the external source.
PIC16(L)F1508/9 19.3 Timer1 Prescaler Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L. 19.4 Timer1 (Secondary) Oscillator A dedicated low-power 32.768 kHz oscillator circuit is built-in between pins S1OSI (input) and S1OSO (amplifier output).
PIC16(L)F1508/9 19.6.2.1 T1G Pin Gate Operation The T1G pin is one source for Timer1 gate control. It can be used to supply an external source to the Timer1 gate circuitry. 19.6.2.2 Timer0 Overflow Gate Operation When Timer0 increments from FFh to 00h, a low-tohigh pulse will automatically be generated and internally supplied to the Timer1 gate circuitry. 19.6.
PIC16(L)F1508/9 19.7 Timer1 Interrupt The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: • • • • TMR1ON bit of the T1CON register TMR1IE bit of the PIE1 register PEIE bit of the INTCON register GIE bit of the INTCON register 19.8.
PIC16(L)F1508/9 FIGURE 19-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL t1g_in T1CKI T1GVAL Timer1 N FIGURE 19-4: N+1 N+2 N+3 N+4 TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM t1g_in T1CKI T1GVAL Timer1 N DS40001609C-page 170 N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 FIGURE 19-5: TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G t1g_in T1CKI T1GVAL Timer1 TMR1GIF N Cleared by software 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 FIGURE 19-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G t1g_in T1CKI T1GVAL Timer1 TMR1GIF DS40001609C-page 172 N Cleared by software N+1 N+2 N+3 Set by hardware on falling edge of T1GVAL N+4 Cleared by software 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 19.
PIC16(L)F1508/9 REGISTER 19-2: T1GCON: TIMER1 GATE CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ DONE T1GVAL R/W-0/u R/W-0/u T1GSS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 TMR1GE: Timer1 Gate Enable bit If
PIC16(L)F1508/9 TABLE 19-5: Name SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Bit 7 Bit 6 Bit 5 Bit 4 ANSELA — — — APFCON — — — INTCON Bit 3 Bit 2 ANSA4 — ANSA2 SSSEL T1GSEL — Bit 0 Register on Page ANSA1 ANSA0 113 CLC1SEL NCO1SEL 110 Bit 1 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 76 SOSCR — OSTS HFIOFR — — LFIOFR HFIOFS 61 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE — TMR2IE TMR1IE 77 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF — TMR2IF TMR1IF 81 OSCSTA
PIC16(L)F1508/9 NOTES: DS40001609C-page 176 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 20.0 TIMER2 MODULE The Timer2 module incorporates the following features: • 8-bit Timer and Period registers (TMR2 and PR2, respectively) • Readable and writable (both registers) • Software programmable prescaler (1:1, 1:4, 1:16, and 1:64) • Software programmable postscaler (1:1 to 1:16) • Interrupt on TMR2 match with PR2 See Figure 20-1 for a block diagram of Timer2. FIGURE 20-1: TIMER2 BLOCK DIAGRAM Rev.
PIC16(L)F1508/9 20.1 Timer2 Operation 20.3 Timer2 Output The clock input to the Timer2 module is the system instruction clock (FOSC/4). The output of TMR2 is T2_match. T2_match is available to the following peripherals: TMR2 increments from 00h on each clock edge. • • • • A 4-bit counter/prescaler on the clock input allows direct input, divide-by-4 and divide-by-16 prescale options. These options are selected by the prescaler control bits, T2CKPS<1:0> of the T2CON register.
PIC16(L)F1508/9 20.
PIC16(L)F1508/9 NOTES: DS40001609C-page 180 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 21.0 21.1 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE The SPI interface supports the following modes and features: • • • • • MSSP Module Overview The Master Synchronous Serial Port (MSSPx) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc.
PIC16(L)F1508/9 The I2C interface supports the following modes and features: • • • • • • • • • • • • • The PIC16(L)F1508/9 has one MSSP module.
PIC16(L)F1508/9 FIGURE 21-3: MSSP BLOCK DIAGRAM (I2C™ SLAVE MODE) Rev. 10-000078A 7/30/2013 Internal data bus Read Write 8 8 SSPxBUF 8 8 SCLx Shift clock SDAx SSPxSR MSb LSb 8 SSPxMSK 8 Match detect Addr Match 8 SSPxADD Start and Stop bit Detect 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 21.2 SPI Mode Overview The Serial Peripheral Interface (SPI) bus is a synchronous serial data communication bus that operates in Full-Duplex mode. Devices communicate in a master/slave environment where the master device initiates the communication. A slave device is controlled through a Chip Select known as Slave Select.
PIC16(L)F1508/9 FIGURE 21-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION Rev. 10-000079A 8/1/2013 SPI Master SCKx SCKx SDOx SDIx SDIx General I/O General I/O General I/O SDOx SPI Slave #1 SSx SCKx SDIx SDOx SPI Slave #2 SSx SCKx SDIx SDOx SPI Slave #3 SSx 21.2.1 SPI MODE REGISTERS The MSSP module has five registers for SPI mode operation. These are: • • • • • • During transmission, the SSPxBUF is not buffered. A write to SSPxBUF will write to both SSPxBUF and SSPxSR.
PIC16(L)F1508/9 21.2.2 SPI MODE OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>).
PIC16(L)F1508/9 FIGURE 21-5: SPI MASTER/SLAVE CONNECTION Rev. 10-000080A 7/30/2013 SPI Slave SSPM<3:0> = 010x SPI Master SSPM<3:0> = 00xx = 1010 SDOx SDIx Serial Input Buffer (SSPxBUF) Serial Input Buffer (SSPxBUF) SDIx Shift Register (SSPxSR) MSb LSb SCKx General I/O Processor 1 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 21.2.3 SPI MASTER MODE The master can initiate the data transfer at any time because it controls the SCKx line. The master determines when the slave (Processor 2, Figure 21-5) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPxBUF register is written to. If the SPI is only going to receive, the SDOx output could be disabled (programmed as an input).
PIC16(L)F1508/9 21.2.4 SPI SLAVE MODE In Slave mode, the data is transmitted and received as external clock pulses appear on SCKx. When the last bit is latched, the SSPxIF interrupt flag bit is set. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCKx pin. The Idle state is determined by the CKP bit of the SSPxCON1 register.
PIC16(L)F1508/9 FIGURE 21-7: SPI DAISY-CHAIN CONNECTION Rev.
PIC16(L)F1508/9 FIGURE 21-9: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SSx Optional SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF Valid SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDIx bit 0 bit 7 Input Sample SSPxIF Interrupt Flag SSPxSR to SSPxBUF Write Collision detection active FIGURE 21-10: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SSx Not Optional SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) Write to SSPxBUF Valid SDOx bit 7 bit 6 bit 5 bit 4 bit 3 b
PIC16(L)F1508/9 21.2.6 SPI OPERATION IN SLEEP MODE In SPI Master mode, module clocks may be operating at a different speed than when in Full-Power mode; in the case of the Sleep mode, all clocks are halted. Special care must be taken by the user when the MSSP clock is much faster than the system clock. In Slave mode, when MSSP interrupts are enabled, after the master completes sending data, an MSSP interrupt will wake the controller from Sleep.
PIC16(L)F1508/9 21.3 I2C MODE OVERVIEW FIGURE 21-11: The Inter-Integrated Circuit Bus (I2C) is a multi-master serial data communication bus. Devices communicate in a master/slave environment where the master devices initiate the communication. A slave device is controlled through addressing. Rev.
PIC16(L)F1508/9 When one device is transmitting a logical one, or letting the line float, and a second device is transmitting a logical zero, or holding the line low, the first device can detect that the line is not a logical one. This detection, when used on the SCLx line, is called clock stretching. Clock stretching gives slave devices a mechanism to control the flow of data. When this detection is used on the SDAx line, it is called arbitration.
PIC16(L)F1508/9 21.4 I2C MODE OPERATION All MSSP I2C communication is byte oriented and shifted out MSb first. Six SFR registers and two interrupt flags interface the module with the PIC® microcontroller and user software. Two pins, SDAx and SCLx, are exercised by the module to communicate with other external I2C devices. 21.4.1 BYTE FORMAT All communication in I2C is done in 9-bit segments. A byte is sent from a master to a slave or vice-versa, followed by an Acknowledge bit sent back.
PIC16(L)F1508/9 21.4.5 21.4.7 START CONDITION The I2C specification defines a Start condition as a transition of SDAx from a high to a low state while SCLx line is high. A Start condition is always generated by the master and signifies the transition of the bus from an Idle to an Active state. Figure 21-12 shows wave forms for Start and Stop conditions. A Restart is valid any time that a Stop would be valid.
PIC16(L)F1508/9 21.4.9 ACKNOWLEDGE SEQUENCE 21.5.1.1 I2C Slave 7-bit Addressing Mode The ninth SCLx pulse for any transferred byte in I2C is dedicated as an Acknowledge. It allows receiving devices to respond back to the transmitter by pulling the SDAx line low. The transmitter must release control of the line during this time to shift in the response.
PIC16(L)F1508/9 21.5.2.1 7-bit Addressing Reception This section describes a standard sequence of events for the MSSP module configured as an I2C slave in 7-bit Addressing mode. Figure 21-14 and Figure 21-15 are used as visual references for this description. This is a step by step process of what typically must be done to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Start bit detected. S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled.
2011-2013 Microchip Technology Inc. SSPOV BF SSPxIF S 1 A7 2 A6 3 A5 4 A4 5 A3 Receiving Address 6 A2 7 A1 8 9 ACK 1 D7 2 D6 4 5 D3 6 D2 7 D1 SSPxBUF is read Cleared by software 3 D4 Receiving Data D5 8 9 2 D6 First byte of data is available in SSPxBUF 1 D0 ACK D7 4 5 D3 6 D2 7 D1 SSPOV set because SSPxBUF is still full. ACK is not sent.
DS40001609C-page 200 CKP SSPOV BF SSPxIF 1 SCLx S A7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 9 R/W=0 ACK SEN 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 CKP is written to ‘1’ in software, releasing SCLx SSPxBUF is read Cleared by software Clock is held low until CKP is set to ‘1’ 1 D7 Receive Data 9 ACK SEN 3 D5 4 D4 5 D3 First byte of data is available in SSPxBUF 6 D2 7 D1 SSPOV set because SSPxBUF is still full. ACK is not sent.
2011-2013 Microchip Technology Inc.
DS40001609C-page 202 P S ACKTIM CKP ACKDT BF SSPxIF S Receiving Address 4 5 6 7 8 When AHEN = 1; on the 8th falling edge of SCLx of an address byte, CKP is cleared Slave software clears ACKDT to ACK the received byte Received address is loaded into SSPxBUF 2 3 ACKTIM is set by hardware on 8th falling edge of SCLx 1 A7 A6 A5 A4 A3 A2 A1 9 ACK Receive Data 2 3 4 5 6 7 8 ACKTIM is cleared by hardware on 9th rising edge of SCLx When DHEN = 1; on the 8th falling edge of SCLx of a rec
PIC16(L)F1508/9 21.5.3 SLAVE TRANSMISSION 21.5.3.2 7-bit Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPxSTAT register is set. The received address is loaded into the SSPxBUF register, and an ACK pulse is sent by the slave on the ninth bit. A master device can transmit a read request to a slave, and then clock data out of the slave.
DS40001609C-page 204 P S D/A R/W ACKSTAT CKP BF SSPxIF S 1 2 5 6 7 8 Received address is read from SSPxBUF 4 Indicates an address has been received R/W is copied from the matching address byte When R/W is set SCLx is always held low after 9th SCLx falling edge 3 9 Automatic 2 3 4 5 Set by software Data to transmit is loaded into SSPxBUF Cleared by software 1 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK Transmitting Data 2 3 4 5 7 8 CKP is not held for not ACK 6 Masters n
PIC16(L)F1508/9 21.5.3.3 7-bit Transmission with Address Hold Enabled Setting the AHEN bit of the SSPxCON3 register enables additional clock stretching and interrupt generation after the eighth falling edge of a received matching address. Once a matching address has been clocked in, CKP is cleared and the SSPxIF interrupt is set. Figure 21-19 displays a standard waveform of a 7-bit Address Slave Transmission with AHEN enabled. 1. 2. Bus starts idle.
DS40001609C-page 206 D/A R/W ACKTIM CKP ACKSTAT ACKDT BF SSPxIF S Receiving Address 2 4 5 6 7 8 Slave clears ACKDT to ACK address ACKTIM is set on 8th falling edge of SCLx 9 ACK When R/W = 1; CKP is always cleared after ACK R/W = 1 Received address is read from SSPxBUF 3 When AHEN = 1; CKP is cleared by hardware after receiving matching address.
PIC16(L)F1508/9 21.5.4 SLAVE MODE 10-BIT ADDRESS RECEPTION This section describes a standard sequence of events for the MSSP module configured as an I2C slave in 10-bit Addressing mode. Figure 21-20 is used as a visual reference for this description. This is a step by step process of what must be done by slave software to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. Bus starts idle. Master sends Start condition; S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled.
DS40001609C-page 208 CKP UA BF SSPxIF S 1 1 2 1 5 6 7 0 A9 A8 8 Set by hardware on 9th falling edge 4 1 When UA = 1; SCLx is held low 9 ACK If address matches SSPxADD it is loaded into SSPxBUF 3 1 Receive First Address Byte 1 3 4 5 6 7 8 Software updates SSPxADD and releases SCLx 2 9 A7 A6 A5 A4 A3 A2 A1 A0 ACK Receive Second Address Byte 1 3 4 5 6 7 8 9 1 3 4 5 6 7 Data is read from SSPxBUF SCLx is held low while CKP = 0 2 8 9 D7 D6 D5 D4 D3 D2 D1 D0 AC
2011-2013 Microchip Technology Inc.
DS40001609C-page 210 D/A R/W ACKSTAT CKP UA BF SSPxIF 4 5 6 7 Set by hardware 3 Indicates an address has been received UA indicates SSPxADD must be updated SSPxBUF loaded with received address 2 8 9 1 SCLx S Receiving Address R/W = 0 1 1 1 1 0 A9 A8 ACK 1 3 4 5 6 7 8 After SSPxADD is updated, UA is cleared and SCLx is released Cleared by software 2 9 A7 A6 A5 A4 A3 A2 A1 A0 ACK Receiving Second Address Byte 1 4 5 6 7 8 Set by hardware 2 3 R/W is copied from the match
PIC16(L)F1508/9 21.5.6 CLOCK STRETCHING 21.5.6.2 Clock stretching occurs when a device on the bus holds the SCLx line low, effectively pausing communication. The slave may stretch the clock to allow more time to handle data or prepare a response for the master device. A master device is not concerned with stretching as anytime it is active on the bus and not transferring data it is stretching.
PIC16(L)F1508/9 21.5.8 GENERAL CALL ADDRESS SUPPORT In 10-bit Address mode, the UA bit will not be set on the reception of the general call address. The slave will prepare to receive the second byte as data, just as it would in 7-bit mode. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master device. The exception is the general call address which can address all devices.
PIC16(L)F1508/9 21.6 I2C MASTER MODE Master mode is enabled by setting and clearing the appropriate SSPM bits in the SSPxCON1 register and by setting the SSPEN bit. In Master mode, the SDAx and SCKx pins must be configured as inputs. The MSSP peripheral hardware will override the output driver TRIS controls when necessary to drive the pins low. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions.
PIC16(L)F1508/9 21.6.2 CLOCK ARBITRATION Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, releases the SCLx pin (SCLx allowed to float high). When the SCLx pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCLx pin is actually sampled high. When the SCLx pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and begins counting.
PIC16(L)F1508/9 21.6.4 I2C MASTER MODE START by hardware; the Baud Rate Generator is suspended, leaving the SDAx line held low and the Start condition is complete. CONDITION TIMING To initiate a Start condition (Figure 21-26), the user sets the Start Enable bit, SEN bit of the SSPxCON2 register. If the SDAx and SCLx pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and starts its count.
PIC16(L)F1508/9 21.6.5 I2C MASTER MODE REPEATED automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDAx pin held low. As soon as a Start condition is detected on the SDAx and SCLx pins, the S bit of the SSPxSTAT register will be set. The SSPxIF bit will not be set until the Baud Rate Generator has timed out.
PIC16(L)F1508/9 21.6.6 I2C MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPxBUF register. This action will set the Buffer Full flag bit, BF, and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDAx pin after the falling edge of SCLx is asserted.
DS40001609C-page 218 S R/W PEN SEN BF (SSPxSTAT<0>) SSPxIF SCLx SDAx A6 A5 A4 A3 A2 A1 3 4 5 Cleared by software 2 6 7 8 9 After Start condition, SEN cleared by hardware SSPxBUF written 1 D7 1 SCLx held low while CPU responds to SSPxIF ACK = 0 R/W = 0 SSPxBUF written with 7-bit address and R/W start transmit A7 Transmit Address to Slave 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 SSPxBUF is written by software Cleared by software service routine from SSP interrupt 2 D6 Tran
PIC16(L)F1508/9 21.6.7 I2C MASTER MODE RECEPTION Master mode reception (Figure 21-29) is enabled by programming the Receive Enable bit, RCEN bit of the SSPxCON2 register. Note: The MSSPx module must be in an Idle state before the RCEN bit is set or the RCEN bit will be disregarded. The Baud Rate Generator begins counting and on each rollover, the state of the SCLx pin changes (high-to-low/low-to-high) and data is shifted into the SSPxSR.
DS40001609C-page 220 RCEN ACKEN SSPOV BF (SSPxSTAT<0>) SDAx = 0, SCLx = 1 while CPU responds to SSPxIF SSPxIF S 1 A7 2 4 5 6 Cleared by software 3 A6 A5 A4 A3 A2 Transmit Address to Slave 7 8 9 ACK Receiving Data from Slave 2 3 5 6 7 8 D0 9 ACK Receiving Data from Slave 2 3 4 RCEN cleared automatically 5 6 7 Cleared by software Set SSPxIF interrupt at end of Acknowledge sequence Data shifted in on falling edge of CLK 1 ACK from Master SDAx = ACKDT = 0 Cleared in sof
PIC16(L)F1508/9 21.6.8 ACKNOWLEDGE SEQUENCE TIMING 21.6.9 A Stop bit is asserted on the SDAx pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN bit of the SSPxCON2 register. At the end of a receive/transmit, the SCLx line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDAx line low. When the SDAx line is sampled low, the Baud Rate Generator is reloaded and counts down to ‘0’.
PIC16(L)F1508/9 FIGURE 21-31: STOP CONDITION RECEIVE OR TRANSMIT MODE SCLx = 1 for TBRG, followed by SDAx = 1 for TBRG after SDAx sampled high. P bit (SSPxSTAT<4>) is set. Write to SSPxCON2, set PEN PEN bit (SSPxCON2<2>) is cleared by hardware and the SSPxIF bit is set Falling edge of 9th clock TBRG SCLx ACK SDAx P TBRG TBRG TBRG SCLx brought high after TBRG SDAx asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period. 21.6.
PIC16(L)F1508/9 FIGURE 21-32: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCLx = 0 SDAx line pulled low by another source SDAx released by master Sample SDAx. While SCLx is high, data does not match what is driven by the master. Bus collision has occurred. SDAx SCLx Set bus collision interrupt (BCLxIF) BCLxIF 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 21.6.13.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDA or SCL are sampled low at the beginning of the Start condition (Figure 21-33). SCL is sampled low before SDAx is asserted low (Figure 21-34). During a Start condition, both the SDAx and the SCL pins are monitored. If the SDAx pin is sampled low during this count, the BRG is reset and the SDAx line is asserted early (Figure 21-35).
PIC16(L)F1508/9 FIGURE 21-34: BUS COLLISION DURING START CONDITION (SCLX = 0) SDAx = 0, SCLx = 1 TBRG TBRG SDAx Set SEN, enable Start sequence if SDAx = 1, SCLx = 1 SCLx SCLx = 0 before SDAx = 0, bus collision occurs. Set BCLxIF. SEN SCLx = 0 before BRG time-out, bus collision occurs. Set BCLxIF.
PIC16(L)F1508/9 21.6.13.2 Bus Collision During a Repeated Start Condition If SDAx is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, Figure 21-36). If SDAx is sampled high, the BRG is reloaded and begins counting. If SDAx goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDAx at exactly the same time.
PIC16(L)F1508/9 21.6.13.3 Bus Collision During a Stop Condition The Stop condition begins with SDAx asserted low. When SDAx is sampled low, the SCLx pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPxADD and counts down to 0. After the BRG times out, SDAx is sampled. If SDAx is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 21-38).
PIC16(L)F1508/9 TABLE 21-3: Name INTCON SUMMARY OF REGISTERS ASSOCIATED WITH I2C™ OPERATION Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: INTE IOCIE TMR0IF INTF IOCIF 76 Bit 7 Bit 6 Bit 5 Bit 4 GIE PEIE TMR0IE PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE — TMR2IE TMR1IE 77 PIE2 OSFIE C2IE C1IE — BCL1IE NCO1IE — — 78 — PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF TMR2IF TMR1IF 80 PIR2 OSFIF C2IF C1IF — BCL1IF NCO1IF — — 81 — — TRISA5 TRISA4 —(1) TRISA2 TRISA1 TRI
PIC16(L)F1508/9 21.7 BAUD RATE GENERATOR module clock line. The logic dictating when the reload signal is asserted depends on the mode the MSSP is being operated in. The MSSP module has a Baud Rate Generator available for clock generation in both I2C and SPI Master modes. The Baud Rate Generator (BRG) reload value is placed in the SSPxADD register (Register 21-6). When a write occurs to SSPxBUF, the Baud Rate Generator will automatically begin counting down.
PIC16(L)F1508/9 21.
PIC16(L)F1508/9 REGISTER 21-1: bit 0 SSPxSTAT: SSP STATUS REGISTER (CONTINUED) BF: Buffer Full Status bit Receive (SPI and I2 C modes): 1 = Receive complete, SSPxBUF is full 0 = Receive not complete, SSPxBUF is empty Transmit (I2 C mode only): 1 = Data transmit in progress (does not include the ACK and Stop bits), SSPxBUF is full 0 = Data transmit complete (does not include the ACK and Stop bits), SSPxBUF is empty 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 REGISTER 21-2: SSPxCON1: SSP CONTROL REGISTER 1 R/C/HS-0/0 R/C/HS-0/0 R/W-0/0 R/W-0/0 WCOL SSPOV(1) SSPEN CKP R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SSPM<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared bit 7 WCOL: Write Collision Detect bit Master mode
PIC16(L)F1508/9 SSPxCON2: SSP CONTROL REGISTER 2(1) REGISTER 21-3: R/W-0/0 R-0/0 R/W-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/W/HS-0/0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware S = User set bit 7 GCEN: General Call Enable bit
PIC16(L)F1508/9 REGISTER 21-4: SSPxCON3: SSP CONTROL REGISTER 3 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ACKTIM(3) PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only)(3) 1 = Indicates the I2C bus is
PIC16(L)F1508/9 REGISTER 21-5: R/W-1/1 SSPxMSK: SSP MASK REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 MSK<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 MSK<7:1>: Mask bits 1 = The received address bit n is compared to SSPxADD to detect I2C address match 0 = The received address bi
PIC16(L)F1508/9 NOTES: DS40001609C-page 236 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 22.
PIC16(L)F1508/9 FIGURE 22-2: EUSART RECEIVE BLOCK DIAGRAM Rev.
PIC16(L)F1508/9 22.1 EUSART Asynchronous Mode The EUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a VOH mark state which represents a ‘1’ data bit, and a VOL space state which represents a ‘0’ data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission.
PIC16(L)F1508/9 22.1.1.5 TSR Status 22.1.1.7 The TRMT bit of the TXSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied to this bit, so the user has to poll this bit to determine the TSR status. Note: 22.1.1.6 1. 2. 3.
PIC16(L)F1508/9 TABLE 22-1: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 249 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 76 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE — TMR2IE TMR1IE 77 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF — TMR2IF TMR1IF 80 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 248* Name BAUDCON INTCON RCSTA SPBRGL BRG<7:0> 250* SPBRG
PIC16(L)F1508/9 22.1.2 EUSART ASYNCHRONOUS RECEIVER The Asynchronous mode is typically used in RS-232 systems. The receiver block diagram is shown in Figure 22-2. The data is received on the RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate.
PIC16(L)F1508/9 22.1.2.4 Receive Framing Error Each character in the receive FIFO buffer has a corresponding framing error Status bit. A framing error indicates that a Stop bit was not seen at the expected time. The framing error status is accessed via the FERR bit of the RCSTA register. The FERR bit represents the status of the top unread character in the receive FIFO. Therefore, the FERR bit must be read before reading the RCREG.
PIC16(L)F1508/9 22.1.2.8 Asynchronous Reception Set-up: 22.1.2.9 1. Initialize the SPBRGH, SPBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 22.4 “EUSART Baud Rate Generator (BRG)”). 2. Clear the ANSEL bit for the RX pin (if applicable). 3. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. 4. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register.
PIC16(L)F1508/9 TABLE 22-2: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 249 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 76 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE — TMR2IE TMR1IE 77 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF — TMR2IF TMR1IF 80 SPEN RX9 SREN OERR RX9D Name BAUDCON INTCON RCREG RCSTA EUSART Receive Data Register SPBRGL CREN ADDEN
PIC16(L)F1508/9 22.2 Clock Accuracy with Asynchronous Operation The factory calibrates the internal oscillator block output (INTOSC). However, the INTOSC frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. The Auto-Baud Detect feature (see Section 22.4.1 “Auto-Baud Detect”) can be used to compensate for changes in the INTOSC frequency.
PIC16(L)F1508/9 22.
PIC16(L)F1508/9 REGISTER 22-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pin
PIC16(L)F1508/9 REGISTER 22-3: BAUDCON: BAUD RATE CONTROL REGISTER R-0/0 R-1/1 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-ba
PIC16(L)F1508/9 22.4 EUSART Baud Rate Generator (BRG) The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit of the BAUDCON register selects 16-bit mode. The SPBRGH, SPBRGL register pair determines the period of the free running baud rate timer.
PIC16(L)F1508/9 TABLE 22-3: BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula 0 8-bit/Asynchronous FOSC/[64 (n+1)] 0 1 8-bit/Asynchronous 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous 1 x 16-bit/Synchronous SYNC BRG16 BRGH 0 0 0 1 Legend: Name BAUDCON SUMMARY OF REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ABDOVF RCIDL — SCKP BRG16 — WUE
PIC16(L)F1508/9 TABLE 22-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 20.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 18.432 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 16.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 — — — — — — — — — — — — 1200 1221 1.73 255 1200 0.00 239 1202 0.16 207 1200 0.00 143 2400 2404 0.16 129 2400 0.
PIC16(L)F1508/9 TABLE 22-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 8.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 4.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 3.6864 MHz Actual Rate FOSC = 1.000 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 300 1200 — — — — — — — 1202 — 0.16 — 207 — 1200 — 0.00 — 191 300 1202 0.16 0.16 207 51 2400 2404 0.16 207 2404 0.
PIC16(L)F1508/9 TABLE 22-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 1200 300.0 1200 0.00 -0.01 16665 4166 300.0 1200 0.00 0.00 15359 3839 300.0 1200.1 0.00 0.01 13332 3332 300.0 1200 0.00 0.00 9215 2303 2400 2400 0.02 2082 2400 0.00 1919 2399.5 -0.02 1666 2400 0.
PIC16(L)F1508/9 22.4.1 AUTO-BAUD DETECT The EUSART module supports automatic detection and calibration of the baud rate. In the Auto-Baud Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RX signal, the RX signal is timing the BRG. The Baud Rate Generator is used to time the period of a received 55h (ASCII “U”) which is the Sync character for the LIN bus. The unique feature of this character is that it has five rising edges including the Stop bit edge.
PIC16(L)F1508/9 22.4.2 AUTO-BAUD OVERFLOW During the course of automatic baud detection, the ABDOVF bit of the BAUDCON register will be set if the baud rate counter overflows before the fifth rising edge is detected on the RX pin. The ABDOVF bit indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the SPBRGH:SPBRGL register pair. After the ABDOVF bit has been set, the counter continues to count until the fifth rising edge is detected on the RX pin.
PIC16(L)F1508/9 FIGURE 22-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Auto Cleared Bit set by user WUE bit RX/DT Line RCIF Note 1: Cleared due to User Read of RCREG The EUSART remains in Idle while the WUE bit is set.
PIC16(L)F1508/9 22.4.4 BREAK CHARACTER SEQUENCE The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. A Break character consists of a Start bit, followed by 12 ‘0’ bits and a Stop bit. To send a Break character, set the SENDB and TXEN bits of the TXSTA register. The Break character transmission is then initiated by a write to the TXREG. The value of data written to TXREG will be ignored and all ‘0’s will be transmitted.
PIC16(L)F1508/9 22.5 EUSART Synchronous Mode Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line.
PIC16(L)F1508/9 FIGURE 22-10: SYNCHRONOUS TRANSMISSION RX/DT pin bit 0 bit 1 Word 1 bit 2 bit 7 bit 0 bit 1 Word 2 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit TXEN bit ‘1’ Note: ‘1’ Sync Master mode, SPBRGL = 0, continuous transmission of two 8-bit words.
PIC16(L)F1508/9 22.5.1.5 Synchronous Master Reception Data is received at the RX/DT pin. The RX/DT pin output driver is automatically disabled when the EUSART is configured for synchronous master receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCSTA register) or the Continuous Receive Enable bit (CREN of the RCSTA register).
PIC16(L)F1508/9 FIGURE 22-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RCREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
PIC16(L)F1508/9 22.5.2 SYNCHRONOUS SLAVE MODE The following bits are used to configure the EUSART for synchronous slave operation: • • • • • SYNC = 1 CSRC = 0 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 1. 2. 3. 4. Setting the SYNC bit of the TXSTA register configures the device for synchronous operation. Clearing the CSRC bit of the TXSTA register configures the device as a slave.
PIC16(L)F1508/9 22.5.2.3 EUSART Synchronous Slave Reception 22.5.2.4 The operation of the Synchronous Master and Slave modes is identical (Section 22.5.1.5 “Synchronous Master Reception”), with the following exceptions: • Sleep • CREN bit is always set, therefore the receiver is never idle • SREN bit, which is a “don’t care” in Slave mode 1. 2. 3. A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep.
PIC16(L)F1508/9 23.0 PULSE WIDTH MODULATION (PWM) MODULE Figure 23-1 shows a simplified block diagram of PWM operation. For a step-by-step procedure on how to set up this module for PWM operation, refer to Section 23.1.9 “Setup for PWM Operation using PWMx Pins”.
PIC16(L)F1508/9 23.1 PWMx Pin Configuration All PWM outputs are multiplexed with the PORT data latch. The user must configure the pins as outputs by clearing the associated TRIS bits. Note: 23.1.1 Clearing the PWMxOE bit will relinquish control of the PWMx pin. FUNDAMENTAL OPERATION The PWM module produces a 10-bit resolution output. Timer2 and PR2 set the period of the PWM. The PWMxDCL and PWMxDCH registers configure the duty cycle.
PIC16(L)F1508/9 23.1.5 PWM RESOLUTION The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is ten bits when PR2 is 255. The resolution is a function of the PR2 register value as shown by Equation 23-4.
PIC16(L)F1508/9 23.1.9 SETUP FOR PWM OPERATION USING PWMx PINS The following steps should be taken when configuring the module for PWM operation using the PWMx pins: 1. 2. 3. 4. 5. 6. 7. 8. Disable the PWMx pin output driver(s) by setting the associated TRIS bit(s). Clear the PWMxCON register. Load the PR2 register with the PWM period value. Clear the PWMxDCH register and bits <7:6> of the PWMxDCL register. Configure and start Timer2: • Clear the TMR2IF interrupt flag bit of the PIR1 register.
PIC16(L)F1508/9 23.
PIC16(L)F1508/9 REGISTER 23-2: R/W-x/u PWMxDCH: PWM DUTY CYCLE HIGH BITS R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u PWMxDCH<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PWMxDCH<7:0>: PWM Duty Cycle Most Significant bits These bits are the MSbs of the PWM duty cycle.
PIC16(L)F1508/9 24.0 CONFIGURABLE LOGIC CELL (CLC) The Configurable Logic Cell (CLCx) provides programmable logic that operates outside the speed limitations of software execution. The logic cell takes up to 16 input signals, and through the use of configurable gates, reduces the 16 inputs to four logic lines that drive one of eight selectable single-output logic functions.
PIC16(L)F1508/9 24.1 CLCx Setup Programming the CLCx module is performed by configuring the four stages in the logic signal flow. The four stages are: • • • • Data selection Data gating Logic function selection Output polarity Each stage is setup at run time by writing to the corresponding CLCx Special Function Registers. This has the added advantage of permitting logic reconfiguration on-the-fly during program execution. 24.1.
PIC16(L)F1508/9 24.1.2 DATA GATING Outputs from the input multiplexers are directed to the desired logic function input through the data gating stage. Each data gate can direct any combination of the four selected inputs. Note: Data gating is undefined at power-up. The gate stage is more than just signal direction. The gate can be configured to direct each input signal as inverted or non-inverted data. Directed signals are ANDed together in each gate.
PIC16(L)F1508/9 24.1.5 CLCx SETUP STEPS The following steps should be followed when setting up the CLCx: • Disable CLCx by clearing the LCxEN bit. • Select desired inputs using CLCxSEL0 and CLCxSEL1 registers (See Table 24-1). • Clear any associated ANSEL bits. • Set all TRIS bits associated with inputs. • Clear all TRIS bits associated with outputs. • Enable the chosen inputs through the four gates using CLCxGLS0, CLCxGLS1, CLCxGLS2, and CLCxGLS3 registers.
PIC16(L)F1508/9 FIGURE 24-2: LCx_in[0] INPUT DATA SELECTION AND GATING Data Selection 00000 Data GATE 1 LCx_in[31] lcxd1T LCxD1G1T lcxd1N LCxD1G1N 11111 LCxD2G1T LCxD1S<4:0> LCxD2G1N LCx_in[0] lcxg1 00000 LCxD3G1T lcxd2T LCxG1POL LCxD3G1N lcxd2N LCx_in[31] LCxD4G1T 11111 LCxD2S<4:0> LCx_in[0] LCxD4G1N 00000 Data GATE 2 lcxg2 lcxd3T (Same as Data GATE 1) lcxd3N LCx_in[31] Data GATE 3 11111 lcxg3 LCxD3S<4:0> LCx_in[0] (Same as Data GATE 1) Data GATE 4 00000 lcxg4 lcxd4T (Sam
PIC16(L)F1508/9 FIGURE 24-3: PROGRAMMABLE LOGIC FUNCTIONS Rev.
PIC16(L)F1508/9 24.
PIC16(L)F1508/9 REGISTER 24-2: CLCxPOL: SIGNAL POLARITY CONTROL REGISTER R/W-0/0 U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxPOL — — — LCxG4POL LCxG3POL LCxG2POL LCxG1POL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxPOL: LCOUT Polarity Control bit 1 = The output of the logic cell is inverted 0
PIC16(L)F1508/9 REGISTER 24-3: U-0 CLCxSEL0: MULTIPLEXER DATA 1 AND 2 SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u (1) — LCxD2S<2:0> U-0 — R/W-x/u R/W-x/u R/W-x/u (1) LCxD1S<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-4 LCxD2S<2:0>: Input Data 2 Selection Control bits(1)
PIC16(L)F1508/9 REGISTER 24-4: U-0 CLCxSEL1: MULTIPLEXER DATA 3 AND 4 SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u (1) — LCxD4S<2:0> U-0 — R/W-x/u R/W-x/u R/W-x/u (1) LCxD3S<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-4 LCxD4S<2:0>: Input Data 4 Selection Control bits(1)
PIC16(L)F1508/9 REGISTER 24-5: CLCxGLS0: GATE 1 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG1D4T LCxG1D4N LCxG1D3T LCxG1D3N LCxG1D2T LCxG1D2N LCxG1D1T LCxG1D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxG1D4T: Gate 1 Data 4 True (non-inverted) bit 1
PIC16(L)F1508/9 REGISTER 24-6: CLCxGLS1: GATE 2 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG2D4T LCxG2D4N LCxG2D3T LCxG2D3N LCxG2D2T LCxG2D2N LCxG2D1T LCxG2D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxG2D4T: Gate 2 Data 4 True (non-inverted) bit 1
PIC16(L)F1508/9 REGISTER 24-7: CLCxGLS2: GATE 3 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG3D4T LCxG3D4N LCxG3D3T LCxG3D3N LCxG3D2T LCxG3D2N LCxG3D1T LCxG3D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxG3D4T: Gate 3 Data 4 True (non-inverted) bit 1
PIC16(L)F1508/9 REGISTER 24-8: CLCxGLS3: GATE 4 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG4D4T LCxG4D4N LCxG4D3T LCxG4D3N LCxG4D2T LCxG4D2N LCxG4D1T LCxG4D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxG4D4T: Gate 4 Data 4 True (non-inverted) bit 1
PIC16(L)F1508/9 REGISTER 24-9: CLCDATA: CLC DATA OUTPUT U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 — — — — MLC4OUT MLC3OUT MLC2OUT MLC1OUT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 MLC4OUT: Mirror copy of LC4OUT bit bit 2 MLC3OUT: Mirror copy of LC3OUT bit bit 1 MLC2O
PIC16(L)F1508/9 TABLE 24-3: Name ANSELA SUMMARY OF REGISTERS ASSOCIATED WITH CLCx Bit7 Bit6 — — Bit4 BIt3 Bit2 Bit1 Bit0 Register on Page — ANSA4 — ANSA2 ANSA1 ANSA0 113 ANSB4 — — — — 117 ANSC2 ANSC1 ANSC0 121 Bit5 ANSELB — — ANSB5 ANSELC ANSC7 ANSC6 — — ANSC3 CLC1CON LC1EN LC1OE LC1OUT LC1INTP LC1INTN CLCDATA — — — — — MLC3OUT MLC2OUT MLC1OUT LC1MODE<2:0> 277 285 CLC1GLS0 LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N
PIC16(L)F1508/9 25.0 NUMERICALLY CONTROLLED OSCILLATOR (NCO) MODULE The Numerically Controlled Oscillator (NCOx) module is a timer that uses the overflow from the addition of an increment value to divide the input frequency. The advantage of the addition method over simple counter driven timer is that the resolution of division does not vary with the divider value. The NCOx is most useful for applications that require frequency accuracy and fine resolution at a fixed duty cycle.
NUMERICALLY CONTROLLED OSCILLATOR (NCOx) MODULE SIMPLIFIED BLOCK DIAGRAM NCOxINCH NCOxINCL Rev. 10-000028A 7/30/2013 16 (1) INCBUFH INCBUFL 16 NCO_overflow HFINTOSC 00 FOSC 01 LCx_out 10 20 Adder 20 NCOx_clk NCOxACCU NCOxACCH NCOxACCL 20 11 NCO1CLK NxCKS<1:0> NCO_interrupt set bit NCOxIF 2 Fixed Duty Cycle Mode Circuitry D Q D Q 0 _ 1 Q NxPFM NxOE TRIS bit NCOx NxPOL NCOx_out 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 25.2 Fixed Duty Cycle (FDC) Mode In Fixed Duty Cycle (FDC) mode, every time the accumulator overflows (NCO_overflow), the output is toggled. This provides a 50% duty cycle, provided that the increment value remains constant. For more information, see Figure 25-2. The FDC mode is selected by clearing the NxPFM bit in the NCOxCON register. 25.
NCO – FIXED DUTY CYCLE (FDC) AND PULSE FREQUENCY MODE (PFM) OUTPUT OPERATION DIAGRAM Rev. 10-000 029A_A0 NCOx Clock Source NCOx Increment Value NCOx Accumulator Value NCO_overflow NCO_interrupt 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 25.
PIC16(L)F1508/9 REGISTER 25-3: R/W-0/0 NCOxACCL: NCOx ACCUMULATOR REGISTER – LOW BYTE R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 NCOxACC<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 NCOxACC<7:0>: NCOx Accumulator, Low Byte REGISTER 25-4: R/W-0/0 NCOxACCH: NCOx ACCUMULATOR REGISTER – HIGH
PIC16(L)F1508/9 REGISTER 25-6: R/W-0/0 NCOxINCL: NCOx INCREMENT REGISTER – LOW BYTE(1) R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-1/1 NCOxINC<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: NCOxINC<7:0>: NCOx Increment, Low Byte Write the NCOxINCH register first, then the NCOxINCL registe
PIC16(L)F1508/9 NOTES: DS40001609C-page 294 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 26.0 COMPLEMENTARY WAVEFORM GENERATOR (CWG) MODULE The Complementary Waveform Generator (CWG) produces a complementary waveform with dead-band delay from a selection of input sources. 26.3 Selectable Input Sources The CWG generates the output waveforms from the input sources in Table 26-1.
SIMPLIFIED CWG BLOCK DIAGRAM GxASDLA GxCS 00 1 FOSC 2 ‘0’ 10 ‘1’ 11 cwg_clock GxASDLA = 01 GxOEA CWGxDBR HFINTOSC 6 GxIS 1 3 C1OUT_async C2OUT_async PWM1_out PWM2_out PWM3_out PWM4_out NCO1_out LC1_out EN R S Q R Q = 0 Input Source 6 EN GxOEB R TRISx = 0 1 GxASDLB = 01 00 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 FIGURE 26-2: TYPICAL CWG OPERATION WITH PWM1 (NO AUTO-SHUTDOWN) cwg_clock PWM1 CWGxA Rising Edge Dead Band Falling Edge Dead Band Rising Edge Dead Band Rising Edge D Falling Edge Dead Band CWGxB 26.5 Dead-Band Control Dead-band control provides for non-overlapping output signals to prevent shoot-through current in power switches. The CWG contains two 6-bit dead-band counters. One dead-band counter is used for the rising edge of the input source control.
DEAD-BAND OPERATION, CWGxDBR = 01H, CWGxDBF = 02H cwg_clock Input Source CWGxA CWGxB FIGURE 26-4: DEAD-BAND OPERATION, CWGxDBR = 03H, CWGxDBF = 04H, SOURCE SHORTER THAN DEAD BAND cwg_clock Input Source CWGxA CWGxB 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 26.8 Dead-Band Uncertainty 26.9 Auto-Shutdown Control When the rising and falling edges of the input source triggers the dead-band counters, the input may be asynchronous. This will create some uncertainty in the deadband time delay. The maximum uncertainty is equal to one CWG clock period. Refer to Equation 26-1 for more detail. Auto-shutdown is a method to immediately override the CWG output levels with specific overrides that allow for safe shutdown of the circuit.
PIC16(L)F1508/9 26.10 Operation During Sleep The CWG module operates independently from the system clock and will continue to run during Sleep, provided that the clock and input sources selected remain active. The HFINTOSC remains active during Sleep, provided that the CWG module is enabled, the input source is active, and the HFINTOSC is selected as the clock source, regardless of the system clock source selected.
2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 26.
PIC16(L)F1508/9 REGISTER 26-2: R/W-x/u CWGxCON1: CWG CONTROL REGISTER 1 R/W-x/u R/W-x/u GxASDLB<1:0> R/W-x/u U-0 GxASDLA<1:0> — R/W-0/0 R/W-0/0 R/W-0/0 GxIS<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-6 GxASDLB<1:0>: CWGx Shutdown State for CWGxB When an auto shutdown
PIC16(L)F1508/9 REGISTER 26-3: CWGxCON2: CWG CONTROL REGISTER 2 R/W-0/0 R/W-0/0 GxASE GxARSEN U-0 — U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — GxASDC2 GxASDC1 GxASDFLT GxASDCLC2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 GxASE: Auto-Shutdown Event Status bit 1 = An auto-sh
PIC16(L)F1508/9 REGISTER 26-4: U-0 CWGxDBR: COMPLEMENTARY WAVEFORM GENERATOR (CWGx) RISING DEAD-BAND COUNT REGISTER U-0 — R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u CWGxDBR<5:0> — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 CWGxDBR
PIC16(L)F1508/9 TABLE 26-2: Name ANSELA CWG1CON0 CWG1CON1 CWG1CON2 CWG1DBF SUMMARY OF REGISTERS ASSOCIATED WITH CWG Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — — ANSA4 — ANSA2 ANSA1 ANSA0 113 G1EN G1OEB G1OEA G1POLB G1POLA — — G1CS0 — — G1ASDC2 G1ASDC1 G1ASDLB<1:0> G1ASDLA<1:0> G1IS<1:0> 302 303 G1ASE G1ARSEN — — CWG1DBF<5:0> 305 CWG1DBR<5:0> 305 — — G1ASDSFLT G1ASDSCLC2 304 CWG1DBR — — TRISA — — TRISA5 TRISA4 —(1) TRISA2 TRI
PIC16(L)F1508/9 27.0 IN-CIRCUIT SERIAL PROGRAMMING™ (ICSP™) ICSP™ programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can be done after the assembly process allowing the device to be programmed with the most recent firmware or a custom firmware. Five pins are needed for ICSP™ programming: • ICSPCLK • ICSPDAT • MCLR/VPP • VDD • VSS In Program/Verify mode the program memory, user IDs and the Configuration Words are programmed through serial communications.
PIC16(L)F1508/9 FIGURE 27-2: PICkit™ PROGRAMMER STYLE CONNECTOR INTERFACE Rev. 10-000128A 7/30/2013 Pin 1 Indicator Pin Description* 1 = VPP/MCLR 1 2 3 4 5 6 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT 5 = ICSPCLK 6 = No connect * The 6-pin header (0.100" spacing) accepts 0.025" square pins For additional interface recommendations, refer to your specific device programmer manual prior to PCB design.
PIC16(L)F1508/9 28.0 INSTRUCTION SET SUMMARY 28.1 Read-Modify-Write Operations • Byte Oriented • Bit Oriented • Literal and Control Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction, or the destination designator ‘d’. A read operation is performed on a register even if the instruction writes to that register.
PIC16(L)F1508/9 FIGURE 28-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 OPCODE d f (FILE #) 0 d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 OPCODE b (BIT #) f (FILE #) 0 b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE 8 7 0 k (literal) k = 8-bit immediate value CALL and GOTO instructions only 13 11 10 OPCODE 0 k (literal)
PIC16(L)F1508/9 TABLE 28-3: ENHANCED MID-RANGE INSTRUCTION SET Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ADDWFC ANDWF ASRF LSLF LSRF CLRF CLRW COMF DECF INCF IORWF MOVF MOVWF RLF RRF SUBWF SUBWFB SWAPF XORWF f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d f, d Add W and f Add with Carry W and f AND W with f Arithmetic Right Shift Logical Left Shift Logical Right Shift Clear f
PIC16(L)F1508/9 TABLE 28-3: ENHANCED MID-RANGE INSTRUCTION SET (CONTINUED) Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes CONTROL OPERATIONS BRA BRW CALL CALLW GOTO RETFIE RETLW RETURN k – k – k k k – Relative Branch Relative Branch with W Call Subroutine Call Subroutine with W Go to address Return from interrupt Return with literal in W Return from Subroutine CLRWDT NOP OPTION RESET SLEEP TRIS – – – – – f Clear Watchdog Timer No Operation Load OPTION_REG reg
PIC16(L)F1508/9 28.2 Instruction Descriptions ADDFSR Add Literal to FSRn ANDLW AND literal with W Syntax: [ label ] ADDFSR FSRn, k Syntax: [ label ] ANDLW Operands: -32 k 31 n [ 0, 1] Operands: 0 k 255 Operation: (W) .AND. (k) (W) Operation: FSR(n) + k FSR(n) Status Affected: Z Status Affected: None Description: Description: The signed 6-bit literal ‘k’ is added to the contents of the FSRnH:FSRnL register pair.
PIC16(L)F1508/9 BCF Bit Clear f Syntax: [ label ] BCF BTFSC f,b Bit Test f, Skip if Clear Syntax: [ label ] BTFSC f,b 0 f 127 0b7 Operands: 0 f 127 0b7 Operands: Operation: 0 (f) Operation: skip if (f) = 0 Status Affected: None Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared. Description: If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed.
PIC16(L)F1508/9 CALL Call Subroutine CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0 k 2047 Operands: None Operation: (PC)+ 1 TOS, k PC<10:0>, (PCLATH<6:3>) PC<14:11> Operation: Status Affected: None 00h WDT 0 WDT prescaler, 1 TO 1 PD Description: Call Subroutine. First, return address (PC + 1) is pushed onto the stack. The 11-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH.
PIC16(L)F1508/9 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f) - 1 (destination); skip if result = 0 Operation: (f) + 1 (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in the W register.
PIC16(L)F1508/9 LSLF Logical Left Shift MOVF Syntax: [ label ] LSLF Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f<7>) C (f<6:0>) dest<7:1> 0 dest<0> Operation: (f) (dest) f {,d} Status Affected: C, Z Description: The contents of register ‘f’ are shifted one bit to the left through the Carry flag. A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’.
PIC16(L)F1508/9 MOVIW Move INDFn to W MOVLP Syntax: [ label ] MOVIW ++FSRn [ label ] MOVIW --FSRn [ label ] MOVIW FSRn++ [ label ] MOVIW FSRn-[ label ] MOVIW k[FSRn] Syntax: [ label ] MOVLP k Operands: 0 k 127 Operands: n [0,1] mm [00,01, 10, 11] -32 k 31 Operation: INDFn W Effective address is determined by • FSR + 1 (preincrement) • FSR - 1 (predecrement) • FSR + k (relative offset) After the Move, the FSR value will be either: • FSR + 1 (all increments) • FSR - 1 (all decrements
PIC16(L)F1508/9 MOVWI Move W to INDFn NOP No Operation Syntax: [ label ] MOVWI ++FSRn [ label ] MOVWI --FSRn [ label ] MOVWI FSRn++ [ label ] MOVWI FSRn-[ label ] MOVWI k[FSRn] Syntax: [ label ] Operands: None n [0,1] mm [00,01, 10, 11] -32 k 31 Description: No operation.
PIC16(L)F1508/9 RETFIE Return from Interrupt RETURN Return from Subroutine Syntax: [ label ] Syntax: [ label ] None RETFIE RETURN Operands: None Operands: Operation: TOS PC, 1 GIE Operation: TOS PC Status Affected: None Status Affected: None Description: Description: Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a 2-cycle instruction.
PIC16(L)F1508/9 SUBLW Subtract W from literal Syntax: [ label ] RRF Rotate Right f through Carry Syntax: [ label ] Operands: 0 f 127 d [0,1] Operation: See description below Status Affected: C, DC, Z Status Affected: C Description: Description: The contents of register ‘f’ are rotated one bit to the right through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’.
PIC16(L)F1508/9 SWAPF Swap Nibbles in f XORLW Exclusive OR literal with W Syntax: [ label ] Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 k 255 (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) Operation: (W) .XOR. k W) Status Affected: Z Description: The contents of the W register are XOR’ed with the 8-bit literal ‘k’. The result is placed in the W register.
PIC16(L)F1508/9 29.0 ELECTRICAL SPECIFICATIONS 29.1 Absolute Maximum Ratings(†) Ambient temperature under bias...................................................................................................... -40°C to +125°C Storage temperature ........................................................................................................................ -65°C to +150°C Voltage on pins with respect to VSS on VDD pin PIC16F1508/9 ..............................................................
PIC16(L)F1508/9 29.2 Standard Operating Conditions The standard operating conditions for any device are defined as: Operating Voltage: Operating Temperature: VDDMIN VDD VDDMAX TA_MIN TA TA_MAX VDD — Operating Supply Voltage(1) PIC16LF1508/9 VDDMIN (Fosc 16 MHz).......................................................................................................... +1.8V VDDMIN (16 MHz < Fosc 20 MHz) .........................................................................................
PIC16(L)F1508/9 FIGURE 29-1: VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C, PIC16F1508/9 ONLY Rev. 10-000130A 8/6/2013 VDD (V) 5.5 2.5 2.3 0 16 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 29-7 for each Oscillator mode’s supported frequencies. FIGURE 29-2: VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C, PIC16LF1508/9 ONLY Rev. 10-000131A 8/5/2013 VDD (V) 3.6 2.5 1.
PIC16(L)F1508/9 29.3 DC Characteristics TABLE 29-1: SUPPLY VOLTAGE PIC16LF1508/9 Standard Operating Conditions (unless otherwise stated) PIC16F1508/9 Param. No. D001 Sym. VDD Characteristic Min. Typ† Max. Units VDDMIN 1.8 2.5 — — VDDMAX 3.6 3.6 V V FOSC 16 MHz FOSC 20 MHz 2.3 2.5 — — 5.5 5.5 V V FOSC 16 MHz FOSC 20 MHz 1.5 — — V Device in Sleep mode 1.7 — — V Device in Sleep mode — 1.6 — V — 1.6 — V — 0.8 — V — 1.5 — V -4 — +4 % 0.
PIC16(L)F1508/9 FIGURE 29-3: POR AND POR REARM WITH SLOW RISING VDD VDD VPOR VPORR SVDD VSS NPOR(1) POR REARM VSS TVLOW(2) Note 1: 2: 3: TPOR(3) When NPOR is low, the device is held in Reset. TPOR 1 s typical. TVLOW 2.7 s typical. 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 TABLE 29-2: SUPPLY CURRENT (IDD)(1,2) PIC16LF1508/9 Standard Operating Conditions (unless otherwise stated) PIC16F1508/9 Param. No. Device Characteristics D010 D010 D011 D011 Conditions Min. Typ† Max. Units — 8 20 A 1.8 — 10 25 A 3.0 — 15 31 A 2.3 — 17 33 A 3.0 — 21 39 A 5.0 — 60 100 A 1.8 — 100 180 A 3.0 — 100 180 A 2.3 — 130 220 A 3.0 VDD — 170 280 A 5.0 D012 — 140 240 A 1.8 — 250 360 A 3.
PIC16(L)F1508/9 TABLE 29-2: SUPPLY CURRENT (IDD)(1,2) (CONTINUED) PIC16LF1508/9 Standard Operating Conditions (unless otherwise stated) PIC16F1508/9 Param. No. D015 D015 Device Characteristics Conditions Min. Typ† Max. Units — 3.2 12 A 1.8 — 5.4 20 A 3.0 — 13 28 A 2.3 — 15 30 A 3.0 VDD — 17 36 A 5.0 D016 — 215 360 A 1.8 — 275 480 A 3.0 D016 — 270 450 A 2.3 — 300 500 A 3.0 — 350 620 A 5.0 — 410 660 A 1.8 — 630 970 A 3.
PIC16(L)F1508/9 TABLE 29-2: SUPPLY CURRENT (IDD)(1,2) (CONTINUED) PIC16LF1508/9 Standard Operating Conditions (unless otherwise stated) PIC16F1508/9 Param. No. Device Characteristics D019B D019B D019C D019C D020 D020 Conditions Min. Typ† Max. Units — 6 16 A 1.8 — 8 22 A 3.0 — 13 28 A 2.3 — 15 31 A 3.0 VDD — 16 36 A 5.0 — 19 35 A 1.8 — 32 55 A 3.0 — 31 52 A 2.3 — 38 65 A 3.0 — 44 74 A 5.0 — 140 210 A 1.8 — 250 330 A 3.
PIC16(L)F1508/9 TABLE 29-3: POWER-DOWN CURRENTS (IPD)(1,2) PIC16LF1508/9 Operating Conditions: (unless otherwise stated) Low-Power Sleep Mode PIC16F1508/9 Low-Power Sleep Mode, VREGPM = 1 Param. No. Device Characteristics Min. Typ† Max. +85°C Max. +125°C Units A Conditions VDD D022 Base IPD — 0.020 1.0 8.0 — 0.025 2.0 9.0 A 3.0 D022 Base IPD — 0.25 3.0 10 A 2.3 — 0.30 4.0 12 A 3.0 — 0.40 6.0 15 A 5.0 — 9.8 16 18 A 2.3 — 10.3 18 20 A 3.0 — 11.
PIC16(L)F1508/9 TABLE 29-3: POWER-DOWN CURRENTS (IPD)(1,2) (CONTINUED) PIC16LF1508/9 Operating Conditions: (unless otherwise stated) Low-Power Sleep Mode PIC16F1508/9 Low-Power Sleep Mode, VREGPM = 1 Param. No. Device Characteristics D025 D025 Conditions Min. Typ† Max. +85°C Max. +125°C Units — 0.7 4.0 9.0 A 1.8 — 2.3 8.0 12 A 3.0 — 1.0 6.0 11 A 2.3 — 2.4 8.5 20 A 3.0 VDD — 6.9 20 25 A 5.0 D026 — 0.11 1.5 9.0 A 1.8 — 0.12 2.7 10 A 3.
PIC16(L)F1508/9 TABLE 29-4: I/O PORTS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. VIL Characteristic Min. Typ† Max. Units — — with Schmitt Trigger buffer with I2C™ levels Conditions — 0.8 V 4.5V VDD 5.5V — 0.15 VDD V 1.8V VDD 4.5V — — 0.2 VDD V 2.0V VDD 5.5V — — 0.3 VDD V Input Low Voltage I/O PORT: D030 with TTL buffer D030A D031 — — 0.8 V 2.7V VDD 5.5V D032 MCLR, OSC1 (EXTRC mode) — — 0.
PIC16(L)F1508/9 TABLE 29-5: MEMORY PROGRAMMING SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ† Max. Units Conditions Program Memory Programming Specifications D110 VIHH Voltage on MCLR/VPP pin 8.0 — 9.0 V D111 IDDP Supply Current during Programming — — 10 mA D112 VBE VDD for Bulk Erase D113 VPEW VDD for Write or Row Erase D114 (Note 2) 2.
PIC16(L)F1508/9 TABLE 29-6: THERMAL CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param. No. TH01 TH02 Sym. Characteristic JA Thermal Resistance Junction to Ambient JC TH03 TJMAX TH04 PD TH05 Thermal Resistance Junction to Case Maximum Junction Temperature Power Dissipation PINTERNAL Internal Power Dissipation Typ. Units Conditions 62.2 C/W 20-pin DIP package 77.7 C/W 20-pin SOIC package 87.
PIC16(L)F1508/9 29.4 AC Characteristics Timing Parameter Symbology has been created with one of the following formats: 1. TppS2ppS 2.
PIC16(L)F1508/9 FIGURE 29-5: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 CLKIN OS12 OS02 OS11 OS03 CLKOUT (CLKOUT mode) Note 1: See Table 29-9. TABLE 29-7: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. OS01 Sym.
PIC16(L)F1508/9 TABLE 29-8: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Freq. Tolerance Min. Typ† Max. Units Conditions OS08 HFOSC Internal Calibrated HFINTOSC Frequency(1) ±2% — 16.0 — MHz VDD = 3.
PIC16(L)F1508/9 FIGURE 29-7: CLKOUT AND I/O TIMING Cycle Write Fetch Read Execute Q4 Q1 Q2 Q3 FOSC OS12 OS11 OS20 OS21 CLKOUT OS19 OS18 OS16 OS13 OS17 I/O pin (Input) OS14 OS15 I/O pin (Output) New Value Old Value OS18, OS19 TABLE 29-9: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ† Max. Units Conditions OS11 TosH2ckL FOSC to CLKOUT(1) — — 70 ns 3.3V VDD 5.
PIC16(L)F1508/9 FIGURE 29-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR PWRT Time-out 33 32 OSC Start-up Time Internal Reset(1) Watchdog Timer Reset(1) 34 31 34 I/O pins Note 1: Asserted low. DS40001609C-page 340 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 TABLE 29-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ† Max.
PIC16(L)F1508/9 FIGURE 29-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 49 47 TMR0 or TMR1 TABLE 29-11: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. TT0H 40* Characteristic T0CKI High Pulse Width Min. No Prescaler With Prescaler 41* TT0L T0CKI Low Pulse Width No Prescaler With Prescaler Typ† Max. Units 0.5 TCY + 20 — — ns 10 — — ns 0.
PIC16(L)F1508/9 FIGURE 29-11: CLC PROPAGATION TIMING Rev. 10-000031A 7/30/2013 CLCxINn CLC Input time CLCxINn CLC Input time LCx_in[n](1) LCx_in[n](1) CLC Module LCx_out(1) CLC Output time CLCx CLC Module LCx_out(1) CLC Output time CLCx CLC01 CLC02 CLC03 Note 1: See FIGURE 24-1: Digital-to-Analog Converter Block Diagram to identify specific CLC signals. TABLE 29-12: CONFIGURATION LOGIC CELL (CLC) CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param. No. Sym.
PIC16(L)F1508/9 TABLE 29-13: ANALOG-TO-DIGITAL CONVERTER (ADC) CHARACTERISTICS(1,2,3) Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25°C Param. Sym. No. Characteristic Min. Typ† Max. Units Conditions AD01 NR Resolution — — 10 AD02 EIL Integral Error — ±1 ±1.7 AD03 EDL Differential Error — ±1 ±1 AD04 EOFF Offset Error — ±1 ±2.5 LSb VREF = 3.0V AD05 EGN Gain Error — ±1 ±2.0 LSb VREF = 3.0V AD06 VREF Reference Voltage 1.
PIC16(L)F1508/9 FIGURE 29-12: ADC CONVERSION TIMING (ADC CLOCK FOSC-BASED) BSF ADCON0, GO AD133 1 TCY AD131 Q4 AD130 ADC_clk 9 ADC Data 8 7 6 3 2 1 0 NEW_DATA OLD_DATA ADRES 1 TCY ADIF GO Sample DONE Sampling Stopped AD132 FIGURE 29-13: ADC CONVERSION TIMING (ADC CLOCK FROM FRC) BSF ADCON0, GO AD133 1 TCY AD131 Q4 AD130 ADC_clk 9 ADC Data 8 7 6 OLD_DATA ADRES 2 1 0 NEW_DATA 1 TCY ADIF GO Sample 3 DONE AD132 Sampling Stopped Note 1: If the ADC clock source is selected
PIC16(L)F1508/9 TABLE 29-14: ADC CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. Sym. No. AD130* TAD AD131 TCNV Characteristic Min. Typ† Max. Units Conditions ADC Clock Period (TADC) 1.0 — 6.0 s FOSC-based ADC Internal FRC Oscillator Period (TFRC) 1.0 2.0 6.0 s ADCS<2:0> = x11 (ADC FRC mode) Conversion Time (not including Acquisition Time)(1) — 11 — TAD Set GO/DONE bit to conversion complete s AD132* TACQ Acquisition Time — 5.
PIC16(L)F1508/9 TABLE 29-15: COMPARATOR SPECIFICATIONS(1) Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25°C Param. No. Sym. Characteristics Min. Typ. Max. Units — ±7.
PIC16(L)F1508/9 FIGURE 29-14: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING CK US121 US121 DT US122 US120 Note: Refer to Figure 29-4 for load conditions. TABLE 29-17: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. Symbol US120 TCKH2DTV US121 US122 TCKRF TDTRF FIGURE 29-15: Characteristic Min. Max. Units Conditions SYNC XMIT (Master and Slave) Clock high to data-out valid — 80 ns 3.0V VDD 5.5V — 100 ns 1.
PIC16(L)F1508/9 FIGURE 29-16: SPI MASTER MODE TIMING (CKE = 0, SMP = 0) SS SP81 SCK (CKP = 0) SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 bit 6 - - - - - -1 MSb SDO LSb SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 29-4 for load conditions.
PIC16(L)F1508/9 FIGURE 29-18: SPI SLAVE MODE TIMING (CKE = 0) SS SP70 SCK (CKP = 0) SP83 SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 MSb SDO LSb bit 6 - - - - - -1 SP77 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 29-4 for load conditions.
PIC16(L)F1508/9 TABLE 29-19: SPI MODE REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. Symbol Characteristic Min. Typ† Max. Units 2.
PIC16(L)F1508/9 I2C™ BUS START/STOP BITS TIMING FIGURE 29-20: SCL SP93 SP91 SP90 SP92 SDA Stop Condition Start Condition Note: Refer to Figure 29-4 for load conditions. TABLE 29-20: I2C™ BUS START/STOP BITS REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. Symbol Characteristic SP90* TSU:STA Start condition SP91* THD:STA SP92* TSU:STO SP93 THD:STO Stop condition Typ 4700 — Max.
PIC16(L)F1508/9 TABLE 29-21: I2C™ BUS DATA REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. Symbol SP100* THIGH Characteristic Clock high time Min. Max. Units 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz 1.5TCY — 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a minimum of 10 MHz 1.
PIC16(L)F1508/9 NOTES: DS40001609C-page 354 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 30.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range.
PIC16(L)F1508/9 FIGURE 30-1: IDD, LP OSCILLATOR, FOSC = 32 kHz, PIC16LF1508/9 ONLY 18 Max: 85°C + 3ı Typical: 25°C 16 Max. 14 IDD (µA) 12 Typical 10 8 6 4 2 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) IDD, LP OSCILLATOR, FOSC = 32 kHz, PIC16F1508/9 ONLY FIGURE 30-2: 30 Max. Max: 85°C + 3ı Typical: 25°C 25 Typical IDD (µA) 20 15 10 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) DS40001609C-page 356 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 FIGURE 30-3: IDD TYPICAL, XT AND EXTRC OSCILLATOR, PIC16LF1508/9 ONLY 350 Typical: 25°C 300 4 MHz EXTRC IDD (µA) 250 200 4 MHz XT 150 1 MHz XT 100 50 1 MHz EXTRC 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 30-4: IDD MAXIMUM, XT AND EXTRC OSCILLATOR, PIC16LF1508/9 ONLY 400 Max: 85°C + 3ı 350 4 MHz XT 300 IDD (µA) 250 200 4 MHz EXTRC 150 1 MHz XT 100 50 1 MHz EXTRC 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.
PIC16(L)F1508/9 FIGURE 30-5: IDD TYPICAL, XT AND EXTRC OSCILLATOR, PIC16F1508/9 ONLY 400 4 MHz EXTRC Typical: 25°C 350 4 MHz XT 300 IDD (µA) 250 200 1 MHz XT 150 100 1 MHz EXTRC 50 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) IDD MAXIMUM, XT AND EXTRC OSCILLATOR, PIC16F1508/9 ONLY FIGURE 30-6: 500 450 4 MHz XT Max: 85°C + 3ı 400 4 MHz EXTRC 350 IDD (µA) 300 1 MHz XT 250 200 150 1 MHz EXTRC 100 50 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.
PIC16(L)F1508/9 FIGURE 30-7: IDD, EXTERNAL CLOCK (ECL), LOW-POWER MODE, FOSC = 32 kHz, PIC16LF1508/9 ONLY 14 Max. 12 10 IDD (µA) Typical 8 6 4 Max: 85°C + 3ı Typical: 25°C 2 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 30-8: IDD, EXTERNAL CLOCK (ECL), LOW-POWER MODE, FOSC = 32 kHz, PIC16F1508/9 ONLY 25 Max. 20 IDD (µA) Typical 15 10 Max: 85°C + 3ı Typical: 25°C 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 FIGURE 30-9: IDD, EXTERNAL CLOCK (ECL), LOW-POWER MODE, FOSC = 500 kHz, PIC16LF1508/9 ONLY 50 45 Max: 85°C + 3ı Typical: 25°C 40 Max. 35 IDD (µA) 30 Typical 25 20 15 10 5 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 30-10: IDD, EXTERNAL CLOCK (ECL), LOW-POWER MODE, FOSC = 500 kHz, PIC16F1508/9 ONLY 60 Max. 50 IDD (µA) 40 Typical 30 20 Max: 85°C + 3ı Typical: 25°C 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.
PIC16(L)F1508/9 FIGURE 30-11: IDD TYPICAL, EXTERNAL CLOCK (ECM), MEDIUM-POWER MODE, PIC16LF1508/9 ONLY 300 Typical: 25°C 250 4 MHz IDD (µA) 200 150 100 1 MHz 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 30-12: IDD MAXIMUM, EXTERNAL CLOCK (ECM), MEDIUM-POWER MODE, PIC16LF1508/9 ONLY 350 Max: 85°C + 3ı 300 IDD (µA) 250 4 MHz 200 150 100 1 MHz 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 FIGURE 30-13: IDD TYPICAL, EXTERNAL CLOCK (ECM), MEDIUM-POWER MODE, PIC16F1508/9 ONLY 350 4 MHz Typical: 25°C 300 IDD (µA) 250 200 150 1 MHz 100 50 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 30-14: IDD MAXIMUM, EXTERNAL CLOCK (ECM), MEDIUM-POWER MODE, PIC16F1508/9 ONLY 400 4 MHz Max: 85°C + 3ı 350 300 IDD (µA) 250 200 1 MHz 150 100 50 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) DS40001609C-page 362 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 FIGURE 30-15: IDD TYPICAL, EXTERNAL CLOCK (ECH), HIGH-POWER MODE, PIC16LF1508/9 ONLY 1.4 20 MHz Typical: 25°C 1.2 16 MHz IDD (mA) 1.0 0.8 0.6 8 MHz 0.4 0.2 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 30-16: IDD MAXIMUM, EXTERNAL CLOCK (ECH), HIGH-POWER MODE, PIC16LF1508/9 ONLY( ) 1.6 1.4 20 MHz Max: 85°C + 3ı 1.2 16 MHz IDD (mA) 1.0 0.8 8 MHz 0.6 0.4 0.2 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.
PIC16(L)F1508/9 FIGURE 30-17: IDD TYPICAL, EXTERNAL CLOCK (ECH), HIGH-POWER MODE, PIC16F1508/9 ONLY 1.4 20 MHz Typical: 25°C 1.2 16 MHz IDD (mA) 1.0 0.8 8 MHz 0.6 0.4 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 30-18: IDD MAXIMUM, EXTERNAL CLOCK (ECH), HIGH-POWER MODE, PIC16F1508/9 ONLY 1.6 20 MHz Max: 85°C + 3ı 1.4 16 MHz 1.2 IDD (mA) 1.0 0.8 8 MHz 0.6 0.4 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.
PIC16(L)F1508/9 FIGURE 30-19: IDD, LFINTOSC, FOSC = 31 kHz, PIC16LF1508/9 ONLY 12 Max. Max: 85°C + 3ı Typical: 25°C 10 IDD (µA) 8 Typical 6 4 2 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 30-20: IDD, LFINTOSC, FOSC = 31 kHz, PIC16F1508/9 ONLY 25 Max. 20 IDD (µA) Typical 15 10 Max: 85°C + 3ı Typical: 25°C 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 FIGURE 30-21: IDD, MFINTOSC, FOSC = 500 kHz, PIC16LF1508/9 ONLY 400 Max: 85°C + 3ı Typical: 25°C 350 Max. 300 IDD (µA) 250 Typical 200 150 100 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 30-22: IDD, MFINTOSC, FOSC = 500 kHz, PIC16F1508/9 ONLY 450 Max: 85°C + 3ı Typical: 25°C 400 Max. 350 Typical IDD (µA) 300 250 200 150 100 50 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) DS40001609C-page 366 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 FIGURE 30-23: IDD TYPICAL, HFINTOSC, PIC16LF1508/9 ONLY 1.4 Typical: 25°C 1.2 16 MHz IDD (mA) 1.0 0.8 8 MHz 0.6 4 MHz 0.4 0.2 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 30-24: IDD MAXIMUM, HFINTOSC, PIC16LF1508/9 ONLY 1.6 Max: 85°C + 3ı 1.4 16 MHz IDD (mA) 1.2 1.0 8 MHz 0.8 4 MHz 0.6 0.4 0.2 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 FIGURE 30-25: IDD TYPICAL, HFINTOSC, PIC16F1508/9 ONLY 1.2 16 MHz 1.0 IDD (mA) 0.8 8 MHz 0.6 4 MHz 0.4 Typical: 25°C 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) IDD MAXIMUM, HFINTOSC, PIC16F1508/9 ONLY FIGURE 30-26: 1.4 1.2 16 MHz IDD (mA) 1.0 0.8 8 MHz 0.6 4 MHz 0.4 Max: 85°C + 3ı 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) DS40001609C-page 368 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 FIGURE 30-27: IDD TYPICAL, HS OSCILLATOR, PIC16LF1508/9 ONLY 1.6 1.4 Typical: 25°C 20 MHz 1.2 IDD (mA) 1.0 0.8 0.6 8 MHz 0.4 4 MHz 0.2 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 3.4 3.6 3.8 VDD (V) FIGURE 30-28: , IDD MAXIMUM, HS OSCILLATOR, PIC16LF1508/9 ONLY 1.8 Max: 85°C + 3ı 1.6 20 MHz 1.4 IDD (mA) 1.2 1.0 0.8 8 MHz 0.6 0.4 4 MHz 0.2 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 VDD (V) 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 FIGURE 30-29: IDD TYPICAL, HS OSCILLATOR, PIC16F1508/9 ONLY 1.8 20 MHz Typical: 25°C 1.6 1.4 1.2 IDD (mA) 1.0 0.8 8 MHz 0.6 4 MHz 0.4 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 30-30: , IDD MAXIMUM, HS OSCILLATOR, PIC16F1508/9 ONLY 2.5 Max: 85°C + 3ı 20 MHz 2.0 IDD (mA) 1.5 8 MHz 1.0 4 MHz 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) DS40001609C-page 370 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 FIGURE 30-31: IPD BASE, LOW-POWER SLEEP MODE, PIC16LF1508/9 ONLY 450 Max: 85°C + 3 M 3ı Typical: 25°C 400 Max. 350 IPD D (nA) 300 250 200 150 100 Typical 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 30-32: IPD BASE, LOW-POWER SLEEP MODE, VREGPM = 1, PIC16F1508/9 ONLY 600 Max. Max: 85°C + 3ı Typical: 25°C 500 IPD (nA) 400 300 Typical 200 100 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 FIGURE 30-33: IPD, WATCHDOG TIMER (WDT), PIC16LF1508/9 ONLY 2.0 1.8 Max: 85°C + 3ı Typical: 25°C 1.6 Max. IPD (µA (µA) 1.4 1.2 1.0 0.8 08 0.6 Typical 0.4 0.2 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 30-34: IPD, WATCHDOG TIMER (WDT), PIC16F1508/9 ONLY 1.4 Max Max. 1.2 IPD (µA A) 1.0 0.8 Typical 0.6 0.4 Max: 85°C + 3ı Typical: 25°C 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.
PIC16(L)F1508/9 FIGURE 30-35: IPD, FIXED VOLTAGE REFERENCE (FVR), PIC16LF1508/9 ONLY 45 Max: 85°C + 3ı Typical: 25°C 40 35 Max. IPD (µA A) 30 Typical 25 20 15 10 5 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 30-36: IPD, FIXED VOLTAGE REFERENCE (FVR), PIC16F1508/9 ONLY 30 Max. 25 IPD (µA) 20 Typical 15 10 Max: 85°C + 3ı Typical: 25°C 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 FIGURE 30-37: IPD, BROWN-OUT RESET (BOR), BORV = 0, PIC16LF1508/9 ONLY 10 Max. 9 Max: 85°C + 3ı Typical: 25°C 8 7 Typical IPD D (µA) 6 5 4 3 2 1 0 16 1.6 1 1.8 8 2 2.0 0 2 2.2 2 2 2.4 4 2 2.6 6 2 2.8 8 3 3.0 0 3 3.2 2 3 3.4 4 3 3.6 6 3 3.8 8 VDD (V) IPD, BROWN-OUT RESET (BOR), BORV = 1, PIC16LF1508/9 ONLY FIGURE 30-38: 12 Max. Max: 85°C + 3ı Typical: 25°C 10 8 IPD (µA) Typical 6 4 2 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.
PIC16(L)F1508/9 FIGURE 30-39: IPD, BROWN-OUT RESET (BOR), BORV = 0, PIC16F1508/9 ONLY 12 M Max. Max: 85°C + 3ı Typical: 25°C 10 8 IPD (µA) Typical 6 4 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 30-40: IPD, BROWN-OUT RESET (BOR), BORV = 1, PIC16F1508/9 ONLY 14 Max Max. Max: 85°C + 3ı Typical: 25°C 12 IPD (µA) 10 Typical 8 6 4 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 FIGURE 30-41: IPD, SECONDARY OSCILLATOR, FOSC = 32 kHz, PIC16LF1508/9 ONLY 8.0 Max: 85°C + 3ı Typical: 25°C 7.0 6.0 Max. IPD (µA A) 5.0 4.0 3.0 30 Typical 2.0 1.0 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) IPD, SECONDARY OSCILLATOR, FOSC = 32 kHz, PIC16F1508/9 ONLY FIGURE 30-42: 16 Max: 85°C + 3ı Typical: 25°C 14 Max. 12 IPD (µA) 10 8 Typical 6 4 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.
PIC16(L)F1508/9 FIGURE 30-43: IPD, COMPARATOR, LOW-POWER MODE (CxSP = 0), PIC16LF1508/9 ONLY 14 12 Max. IPD (µA) 10 8 Typical 6 4 Max: 85°C + 3ı Typical: 25°C 2 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 30-44: IPD, COMPARATOR, LOW-POWER MODE (CxSP = 0), PIC16F1508/9 ONLY 30 25 Max. IPD (µA) 20 Typical yp 15 10 Max: 85°C + 3ı Typical: 25°C 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 FIGURE 30-45: IPD, COMPARATOR, NORMAL-POWER MODE (CxSP = 1), PIC16LF1508/9 ONLY 40 35 Max. 30 IPD (µA A) 25 20 Typical 15 10 Max: 85°C + 3ı Typical: 25 C 25°C 5 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 30-46: IPD, COMPARATOR, NORMAL-POWER MODE (CxSP = 1), PIC16F1508/9 ONLY 60 50 Max. IPD (µA A) 40 30 Typical 20 Max: 85°C + 3ı Typical: 25°C 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.
PIC16(L)F1508/9 FIGURE 30-47: VOH vs. IOH OVER TEMPERATURE, VDD = 5.5V, PIC16F1508/9 ONLY 6 Max: 125°C + 3ı Typical: 25°C Min: -40°C - 3ı 5 VOH (V) 4 Min. (-40°C) 3 Typical (25°C) 2 Max. (125°C) 1 0 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 IOH (mA) VOL vs. IOL OVER TEMPERATURE, VDD = 5.5V, PIC16F1508/9 ONLY FIGURE 30-48: 5 Max: 125°C + 3ı Typical: 25°C Min: -40°C - 3ı 4 Max. (125°C) VOL (V) Typical (25°C) 3 Min. (-40°C) 2 1 0 0 10 20 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 FIGURE 30-49: VOH vs. IOH OVER TEMPERATURE, VDD = 3.0V 3.5 Max: 125°C + 3ı Typical: 25°C Min: -40°C - 3ı 3.0 VOH (V) 2.5 2.0 1.5 1.0 Min. (-40°C) Typical (25°C) Max. (125°C) 0.5 0.0 -15 -13 -11 -9 -7 -5 -3 -1 IOH (mA) VOL vs. IOL OVER TEMPERATURE, VDD = 3.0V FIGURE 30-50: 3.0 Max: 125°C + 3ı Typical: 25°C Min: -40°C - 3ı 2.5 VOL (V) 2.0 Max. (125°C) Typical (25°C) Min. (-40°C) 1.5 1.0 0.5 0.
PIC16(L)F1508/9 FIGURE 30-51: VOH vs. IOH OVER TEMPERATURE, VDD = 1.8V, PIC16LF1508/9 ONLY 2.0 1.8 Max: 125°C + 3ı Typical: 25°C Min: -40°C - 3ı 1.6 VOH (V) 1.4 1.2 Min. (-40°C) Max. (125°C) Typical (25°C) 1.0 0.8 0.6 0.4 0.2 0.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 IOH (mA) VOL vs. IOL OVER TEMPERATURE, VDD = 1.8V, PIC16LF1508/9 ONLY FIGURE 30-52: 1.8 Max: 125°C + 3ı Typical: 25°C Min: -40°C - 3ı 1.6 1.4 VOL (V) 1.2 1.0 0.8 Max. (125°C) Min. (-40°C) Typical (25°C) 0.
PIC16(L)F1508/9 FIGURE 30-53: POR RELEASE VOLTAGE 1.70 1.68 Max. 1.66 Voltage (V) 1.64 Typical 1.62 Min. 1.60 1.58 1.56 Max: Typical + 3ı Typical: 25°C Min: Typical - 3ı 1.54 1.52 1.50 -60 -40 -20 0 20 40 60 80 100 120 140 120 140 Temperature (°C) FIGURE 30-54: POR REARM VOLTAGE, PIC16F1508/9 ONLY 1.54 Max: Typical + 3ı Typical: 25°C Min: Typical - 3ı 1.52 1.50 Max. Voltage (V) 1.48 1.46 1.44 Typical 1.42 1.40 Min. 1.38 1.36 1.
PIC16(L)F1508/9 FIGURE 30-55: BROWN-OUT RESET VOLTAGE, BORV = 1, PIC16LF1508/9 ONLY 2.00 Max. Voltage (V) 1.95 Typical 1.90 1.85 Min. Max: Typical + 3ı Min: Typical - 3ı 1.80 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 30-56: BROWN-OUT RESET HYSTERESIS, BORV = 1, PIC16LF1508/9 ONLY 60 50 Max. Max: Typical + 3ı Typical: 25°C Min: Typical - 3ı Voltage (mV) 40 Typical 30 20 Min.
PIC16(L)F1508/9 FIGURE 30-57: BROWN-OUT RESET VOLTAGE, BORV = 1, PIC16F1508/9 ONLY 2.60 Max. 2.55 Voltage (V) 2.50 Typical 2.45 Min. 2.40 Max: Typical + 3ı Min: Typical - 3ı 2.35 2.30 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 30-58: BROWN-OUT RESET HYSTERESIS, BORV = 1, PIC16F1508/9 ONLY 70 Max. 60 Max: Typical + 3ı Typical: 25°C Min: Typical - 3ı Voltage (mV) 50 40 Typical 30 20 Min.
PIC16(L)F1508/9 FIGURE 30-59: BROWN-OUT RESET VOLTAGE, BORV = 0 2.80 2.75 Voltage (V) Max. 2.70 Typical 2.65 Min. Max: Typical + 3ı Min: Typical - 3ı 2.60 2.55 -60 -40 -20 0 20 40 60 80 100 120 140 120 140 Temperature (°C) FIGURE 30-60: BROWN-OUT RESET HYSTERESIS, BORV = 0 90 80 Min. 70 Voltage (mV) 60 Typical 50 40 Max: Typical + 3ı Typical: 25°C Min: Typical - 3ı 30 20 Max. 10 0 -60 -40 -20 0 20 40 60 80 100 Temperature (°C) 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 FIGURE 30-61: LOW-POWER BROWN-OUT RESET VOLTAGE, LPBOR = 0 2.50 Max. Max: Typical + 3ı Min: Typical - 3ı 2.40 Voltage (V) 2.30 Typical 2.20 2.10 2.00 Min. 1.90 1.80 -60 -40 -20 0 20 40 60 80 100 120 140 120 140 Temperature (°C) FIGURE 30-62: LOW-POWER BROWN-OUT RESET HYSTERESIS, LPBOR = 0 45 Max: Typical + 3ı Typical: 25°C Min: Typical - 3ı 40 35 Max. Typical Voltage (mV) 30 25 Min.
PIC16(L)F1508/9 FIGURE 30-63: WDT TIME-OUT PERIOD 24 22 Max. Time (ms) 20 18 Typical 16 Min. 14 Max: Typical + 3ı (-40°C to +125°C) Typical: statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C) 12 10 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 30-64: PWRT PERIOD 100 Max: Typical + 3ı (-40°C to +125°C) Typical: statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C) 90 Max. Time (ms) 80 70 Typical 60 Min. 50 40 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PIC16(L)F1508/9 FIGURE 30-65: FVR STABILIZATION PERIOD 60 Max: Typical + 3ı Typical: statistical mean @ 25°C 50 Max. Time (us) 40 Typical 30 20 Note: The FVR Stabilization Period applies when: 1) coming out of RESET or exiting Sleep mode for PIC12/16LFxxxx devices. 2) when exiting sleep mode with VREGPM = 1 for PIC12/16Fxxxx devices In all other cases, the FVR is stable when released from RESET. 10 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.
PIC16(L)F1508/9 FIGURE 30-66: COMPARATOR HYSTERESIS, NORMAL-POWER MODE (CxSP = 1, CxHYS = 1) 40 35 Max. Hysteresis (mV) 30 25 Typical 20 15 Min. 10 Max: Typical + 3ı Typical: 25°C Min: Typical - 3ı 5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 30-67: COMPARATOR HYSTERESIS, LOW-POWER MODE (CxSP = 0, CxHYS = 1) 8 7 Max. Hysteresis (mV) 6 5 Typical 4 3 2 Max: Typical + 3ı Typical: 25°C Min: Typical - 3ı 1 Min. 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.
PIC16(L)F1508/9 FIGURE 30-68: COMPARATOR RESPONSE TIME, NORMAL-POWER MODE (CxSP = 1) 350 300 Time (ns) 250 Max. 200 Typical 150 100 Max: Typical + 3ı Typical: 25°C 50 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 30-69: COMPARATOR RESPONSE TIME OVER TEMPERATURE, NORMAL-POWER MODE (CxSP = 1) 400 Max: 125°C + 3ı Typical: 25°C Min: -45°C - 3ı 350 Time (ns) 300 250 Max. (125°C) 200 150 Typical (25°C) 100 Min. (-40°C) 50 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.
PIC16(L)F1508/9 FIGURE 30-70: COMPARATOR INPUT OFFSET AT 25°C, NORMAL-POWER MODE (CxSP = 1), PIC16F1508/9 ONLY 50 40 30 Max. Offset Voltage (mV) 20 10 Typical 0 Min. -10 -20 Max: Typical + 3ı Typical: 25°C Min: Typical - 3ı -30 -40 -50 0.0 1.0 2.0 3.0 4.0 5.0 Common Mode Voltage (V) 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 FIGURE 30-71: LFINTOSC FREQUENCY OVER VDD AND TEMPERATURE, PIC16LF1508/9 ONLY 36 34 Max. Frequency (kHz) 32 30 Typical 28 Min. 26 24 Max: Typical + 3ı (-40°C to +125°C) Typical: statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C) 22 20 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) LFINTOSC FREQUENCY OVER VDD AND TEMPERATURE, PIC16F1508/9 ONLY FIGURE 30-72: 36 34 Max. Frequency (kHz) 32 30 Typical 28 26 Min.
PIC16(L)F1508/9 FIGURE 30-73: HFINTOSC ACCURACY OVER TEMPERATURE, VDD = 1.8V, PIC16LF1508/9 ONLY 8% 6% Max: Typical + 3ı Typical: statistical mean Min: Typical - 3ı Accuracy (%) 4% Max. 2% 0% Typical -2% -4% Min. -6% -8% -10% -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 30-74: HFINTOSC ACCURACY OVER TEMPERATURE, 2.3V VDD 5.5V 8% 6% Max: Typical + 3ı Typical: statistical mean Min: Typical - 3ı Accuracy (%) 4% Max. 2% Typical 0% -2% Min.
PIC16(L)F1508/9 FIGURE 30-75: SLEEP MODE, WAKE PERIOD WITH HFINTOSC SOURCE, PIC16LF1508/9 ONLY 5.0 4.5 Max. 4.0 Time (us) 3.5 Typical 3.0 2.5 2.0 1.5 Max: 85°C + 3ı Typical: 25°C 1.0 0.5 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) DS40001609C-page 394 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 FIGURE 30-76: LOW-POWER SLEEP MODE, WAKE PERIOD WITH HFINTOSC SOURCE, VREGPM = 1, PIC16F1508/9 ONLY 35 Max. 30 Typical Time (us) 25 20 15 10 Max: 85°C + 3ı Typical: 25°C 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 30-77: SLEEP MODE, WAKE PERIOD WITH HFINTOSC SOURCE, VREGPM = 0, PIC16F1508/9 ONLY 12 Max. 10 Time (us) 8 Typical 6 4 Max: 85°C + 3ı Typical: 25°C 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 NOTES: DS40001609C-page 396 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 31.
PIC16(L)F1508/9 31.2 MPLAB XC Compilers The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16, and 32-bit MCU and DSC devices. These compilers provide powerful integration capabilities, superior code optimization and ease of use. MPLAB XC Compilers run on Windows, Linux or MAC OS X. For easy source level debugging, the compilers provide debug information that is optimized to the MPLAB X IDE.
PIC16(L)F1508/9 31.6 MPLAB X SIM Software Simulator The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC16(L)F1508/9 31.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification.
PIC16(L)F1508/9 32.0 PACKAGING INFORMATION 32.1 Package Marking Information 20-Lead PDIP (300 mil) XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 20-Lead SOIC (7.50 mm) Example PIC16F1508 -E/P e3 1120123 Example PIC16F1508 -E/SO e3 1120123 Legend: XX...
PIC16(L)F1508/9 32.2 Package Marking Information 20-Lead SSOP (5.30 mm) Example PIC16F1508 -E/SS e3 1120123 20-Lead QFN (4x4x0.9 mm) PIN 1 DS40001609C-page 402 Example PIN 1 PIC16 F1508 E/ML e3 120123 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 32.3 Package Details The following sections give the technical details of the packages.
PIC16(L)F1508/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001609C-page 404 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 /HDG 3ODVWLF 6KULQN 6PDOO 2XWOLQH 66 ± PP %RG\ >6623@ 1RWH 6 ) * $) % ) 7 & - $+ $ $ ) " 7 ( ) ) & ) )) 588--- * *8 7 D N E E1 NOTE 1 1 2 e b c A2 A φ A1 L1 9 )$ * $ < * )$ :%*, ( " $ : " ) =# ; ) L << 1 1 : := > D 4 / ? ? & & " 7 7 $$ ! D ! ! B ) & (( ! ? ? =# @ &) 1 B B & & " 7
PIC16(L)F1508/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 /HDG 3ODVWLF 4XDG )ODW 1R /HDG 3DFNDJH 0/ ± [ [ PP %RG\ >4)1@ 1RWH 6 ) * $) % ) 7 & - $+ $ $ ) " 7 ( ) ) & ) )) 588--- * *8 7 D D2 EXPOSED PAD e E2 2 E b 2 1 1 K N N NOTE 1 TOP VIEW L BOTTOM VIEW A A1 A3 9 )$ * $ < * )$ :%*, ( " $ : " ) =# ; ) ) & (( ! / ) ) 7 $$ 0 =# @ &) 1 1' $ & " & @ &) 1 =# < ) 1' $ & " & < ) <<
PIC16(L)F1508/9 1RWH 6 ) * $) % ) 7 & - $+ $ $ ) " 7 ( ) ) & ) )) 588--- * *8 7 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 NOTES: DS40001609C-page 410 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 APPENDIX A: DATA SHEET REVISION HISTORY Revision A (10/2011) Original release. Revision B (6/2013) Updated Electrical Specifications Characterization Data. and added and added Revision C (8/2013) Updated Electrical Specifications Characterization Data. 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 NOTES: DS40001609C-page 412 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC16(L)F1508/9 NOTES: DS40001609C-page 414 2011-2013 Microchip Technology Inc.
PIC16(L)F1508/9 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. [X](1) PART NO.
PIC16(L)F1508/9 NOTES: DS40001609C-page 416 2011-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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