Datasheet

 2011 Microchip Technology Inc. Preliminary DS41586A-page 176
PIC16(L)F1507
TABLE 20-3: SUMMARY OF REGISTERS ASSOCIATED WITH CLCx
Name Bit7 Bit6 Bit5 Bit4 BIt3 Bit2 Bit1 Bit0
Register
on Page
ANSELB — —ANSB5ANSB4 — — — — 107
ANSELC
ANSC7 ANSC6 — — ANSC3 ANSC2 ANSC1 ANSC0 110
CLC1CON LC1EN LC1OE LC1OUT LC1INTP LC1INTN LC1MODE<2:0> 167
CLC2CON LC2EN LC2OE LC2OUT LC2INTP LC2INTN LC2MODE<2:0> 167
CLCDATA
— — — — — — MLC2OUT MLC1OUT 171
CLC1GLS0 LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N 171
CLC1GLS1 LC1G2D4T LC1G2D4N LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N LC1G2D1T LC1G2D1N 172
CLC1GLS2 LC1G3D4T LC1G3D4N LC1G3D3T LC1G3D3N LC1G3D2T LC1G3D2N LC1G3D1T LC1G3D1N 173
CLC1GLS3 LC1G4D4T LC1G4D4N LC1G4D3T LC1G4D3N LC1G4D2T LC1G4D2N LC1G4D1T LC1G4D1N 174
CLC1POL LC1POL
— — — LC1G4POL LC1G3POL LC1G2POL LC1G1POL 168
CLC1SEL0
— LC1D2S<2:0> — LC1D1S<2:0> 169
CLC1SEL1
— LC1D4S<2:0> — LC1D3S<2:0> 170
CLC2GLS0 LC2G1D4T LC2G1D4N LC2G1D3T LC2G1D3N LC2G1D2T LC2G1D2N LC2G1D1T LC2G1D1N 171
CLC2GLS1 LC2G2D4T LC2G2D4N LC2G2D3T LC2G2D3N LC2G2D2T LC2G2D2N LC2G2D1T LC2G2D1N 172
CLC2GLS2 LC2G3D4T LC2G3D4N LC2G3D3T LC2G3D3N LC2G3D2T LC2G3D2N LC2G3D1T LC2G3D1N 173
CLC2GLS3 LC2G4D4T LC2G4D4N LC2G4D3T LC2G4D3N LC2G4D2T LC2G4D2N LC2G4D1T LC2G4D1N 174
CLC2POL LC2POL
— — — LC2G4POL LC2G3POL LC2G2POL LC2G1POL 168
CLC2SEL0
— LC2D2S<2:0> — LC2D1S<2:0> 169
CLC2SEL1
— LC2D4S<2:0> — LC2D3S<2:0> 170
INTCON GIE PEIE
TMR0IE INTE IOCIE TMR0IF INTF IOCIF 66
PIE3
— — — — — — CLC2IE CLC1IE 69
PIR3
— — — — — — CLC2IF CLC1IF 72
TRISA
— — TRISA5 TRISA4 —
(1)
TRISA2 TRISA1 TRISA0 102
TRISB TRISB7
TRISB6 TRISB5 TRISB4 — — — — 106
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3
TRISC2 TRISC1 TRISC0 109
Legend: — = unimplemented read as ‘0’,. Shaded cells are not used for CLC module.
Note 1: Unimplemented, read as ‘1’.