Datasheet

PIC16(L)F1507
DS41586A-page 161 Preliminary  2011 Microchip Technology Inc.
20.0 CONFIGURABLE LOGIC CELL
(CLC)
The Configurable Logic Cell (CLCx) provides program-
mable logic that operates outside the speed limitations
of software execution. The logic cell takes up to 16
input signals and through the use of configurable gates
reduces the 16 inputs to four logic lines that drive one
of eight selectable single-output logic functions.
Input sources are a combination of the following:
• I/O pins
• Internal clocks
• Peripherals
•Register bits
The output can be directed internally to peripherals and
to an output pin.
Refer to Figure 20-1 for a simplified diagram showing
signal flow through the CLCx.
Possible configurations include:
• Combinatorial Logic
-AND
-NAND
- AND-OR
- AND-OR-INVERT
-OR-XOR
-OR-XNOR
• Latches
-S-R
- Clocked D with Set and Reset
- Transparent D with Set and Reset
- Clocked J-K with Reset
FIGURE 20-1: CLCx SIMPLIFIED BLOCK DIAGRAM
lcxg1
lcxg2
lcxg3
lcxg4
Interrupt
det
Logic
Function
Input Data Selection Gates
CLCx
LCxOE
lcxq
LCxPOL
LCxOUT
DQ
LE
Q1
LCxMODE<2:0>
lcx_out
CLCxIN[0]
CLCxIN[1]
CLCxIN[2]
CLCxIN[3]
CLCxIN[4]
CLCxIN[5]
CLCxIN[6]
CLCxIN[7]
CLCxIN[8]
CLCxIN[9]
CLCxIN[10]
CLCxIN[11]
CLCxIN[12]
CLCxIN[13]
CLCxIN[14]
CLCxIN[15]
TRIS Control
Interrupt
det
LCxINTP
LCxINTN
MLCxOUT
LCxEN
CLCxIF
sets
flag
See Figure 20-3
See Figure 20-2