Datasheet

PIC16(L)F1503
DS41607A-page 78 Preliminary  2011 Microchip Technology Inc.
TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE
REGISTER 8-1: VREGCON: VOLTAGE REGULATOR CONTROL REGISTER
(1)
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-1/1
— — — — — —VREGPMReserved
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-2 Unimplemented: Read as ‘0’
bit 1 VREGPM: Voltage Regulator Power Mode Selection bit
1 = Low-Power Sleep mode enabled in Sleep
Draws lowest current in Sleep, slower wake-up
0 = Normal Power mode enabled in Sleep
Draws higher current in Sleep, faster wake-up
bit 0 Reserved: Read as ‘1’. Maintain this bit set.
Note 1: PIC16F1503 only.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register on
Page
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 66
IOCAF
— —
IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0
111
IOCAN
— —
IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0
111
IOCAP
— —
IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0
111
PIE1 TMR1GIE ADIE
— —
SSP1IE
— TMR2IE TMR1IE 67
PIE2
—
C2IE C1IE
—
BCLIE
NCO1IE — — 68
PIE3
— — — — — — CLC2IE CLC1IE 69
PIR1 TMR1GIF ADIF
— —
SSP1IF
—
TMR2IF TMR1IF 70
PIR2
—
C2IF C1IF
—
BCL1IF NCO1IF
— — 71
PIR3
— — — — — — CLC2IF CLC1IF 72
STATUS
— — —TOPD Z DC C 18
WDTCON
— — WDTPS<4:0> SWDTEN 81
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used in Power-Down mode.