PIC16(L)F1503 Data Sheet 14-Pin Flash, 8-Bit Microcontrollers 2011 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC16(L)F1503 14-Pin Flash, 8-Bit Microcontrollers High-Performance RISC CPU: Low-Power Features (PIC16LF1503): • • • • • • Standby Current: - 20 nA @ 1.8V, typical • Watchdog Timer Current: - 300 nA @ 1.8V, typical • Operating Current: - 30 A/MHz @ 1.8V, typical C Compiler Optimized Architecture Only 49 Instructions 3.
PIC16(L)F1503 Peripheral Features (Continued): • Numerically Controlled Oscillator (NCO): - 20-bit accumulator - 16-bit increment - True linear frequency control - High-speed clock input - Selectable Output modes - Fixed Duty Cycle (FDC) - Pulse Frequency Mode (PFM) • Complementary Waveform Generator (CWG): - 8 selectable signal sources - Selectable falling and rising edge dead-band control - Polarity control - 4 auto-shutdown sources - Multiple input sources: PWM, CLC, NCO FIGURE 1: ICD 2 2 2 4 4 1 1 1
PIC16(L)F1503 FIGURE 2: 16-PIN QFN DIAGRAM FOR PIC16(L)F1503 VDD NC NC Vss QFN (3x3) RA5 RA4 MCLR/VPP/RA3 RC5 1 2 3 4 PIC16(L)F1503 16 15 14 13 12 11 10 9 - RA0/ICSPDAT RA1/ICSPCLK RA2 RC0 RC4 RC3 RC2 RC1 5 6 7 8 Note: See Table 1 for location of all peripheral functions.
PIC16(L)F1503 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 13 3.0 Memory Organization ................................................................................
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PIC16(L)F1503 NOTES: DS41607A-page 8 Preliminary 2011 Microchip Technology Inc.
PIC16(L)F1503 1.0 DEVICE OVERVIEW The PIC16(L)F1503 are described within this data sheet. They are available in 14 pin packages. Figure 1-1 shows a block diagram of the PIC16(L)F1503 devices. Tables 1-2 shows the pinout descriptions. Reference Table 1-1 for peripherals available per device.
PIC16(L)F1503 FIGURE 1-1: PIC16(L)F1503 BLOCK DIAGRAM Program Flash Memory RAM CLKOUT Timing Generation CLKIN INTRC Oscillator PORTA CPU (Figure 2-1) MCLR C1 Temp. Indicator C2 ADC 10-Bit Note DS41607A-page 10 1: 2: PORTC CLC1 FVR CLC2 Timer0 PWM1 Timer1 PWM2 Timer2 PWM3 CWG1 PWM4 NCO1 MSSP1 DAC See applicable chapters for more information on peripherals. See Table 1-1 for peripherals available on specific devices. Preliminary 2011 Microchip Technology Inc.
PIC16(L)F1503 TABLE 1-2: PIC16(L)F1503 PINOUT DESCRIPTION Name RA0/AN0/C1IN+/DACOUT1/ ICSPDAT RA1/AN1/VREF+/C1IN0-/C2IN0-/ ICSPCLK RA2/AN2/C1OUT/DACOUT2/ T0CKI/INT/PWM3/CLC1(1)/ CWG1FLT RA3/CLC1IN0/VPP/T1G(2)/SS(2)/ MCLR (2) (2) RA4/AN3/NCO1 /SDO / CLKOUT/T1G(1) RA5/CLKIN/T1CKI/NCO1CLK/ CLC1IN1 Function Input Type RA0 TTL AN0 AN Output Type Description CMOS General purpose I/O. — A/D Channel input. C1IN+ AN — Comparator C1 positive input.
PIC16(L)F1503 TABLE 1-2: PIC16(L)F1503 PINOUT DESCRIPTION (CONTINUED) Name RC0/AN4/C2IN+/CLC2/SCL/ SCK RC1/AN5/C1IN1-/C2IN1-/PWM4/ NCO1(1)/SDA/SDI RC2/AN6/C1IN2-/C2IN2-/SDO(1) RC3/AN7/C1IN3-/C2IN3-/PWM2/ CLC2IN0 RC4/C2OUT/CLC2IN1/CWG1B RC5/PWM1/CLC1(2)/ CWG1A Function Input Type RC0 TTL Output Type Description CMOS General purpose I/O. AN4 AN — A/D Channel input. C2IN+ AN — Comparator C2 positive input. CLC2 — SCL I2C CMOS Configurable Logic Cell source output. OD I2C™ clock.
PIC16(L)F1503 2.0 ENHANCED MID-RANGE CPU This family of devices contain an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, Indirect, and Relative addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory.
PIC16(L)F1503 FIGURE 2-1: CORE BLOCK DIAGRAM 15 Configuration 15 MUX Flash Program Memory Program Bus 16-Level 8 Level Stack Stack (13-bit) (15-bit) 14 Instruction Instruction Reg reg 8 Data Bus Program Counter RAM Program Memory Read (PMR) 12 RAM Addr Addr MUX Indirect Addr 12 12 Direct Addr 7 5 BSR FSR Reg reg 15 FSR0reg Reg FSR FSR1 Reg FSR reg 15 STATUS Reg reg STATUS 8 3 CLKIN CLKOUT Instruction Decodeand & Decode Control Timing Generation Internal Oscillator Block DS41607A-p
PIC16(L)F1503 3.0 MEMORY ORGANIZATION These devices contain the following types of memory: • Program Memory - Configuration Words - Device ID - User ID - Flash Program Memory • Data Memory - Core Registers - Special Function Registers - General Purpose RAM - Common RAM TABLE 3-1: The following features are associated with access and control of program memory and data memory: • PCL and PCLATH • Stack • Indirect Addressing 3.
PIC16(L)F1503 FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR PIC16(L)F1503 PC<14:0> CALL, CALLW RETURN, RETLW Interrupt, RETFIE On-chip Program Memory 15 READING PROGRAM MEMORY AS DATA There are two methods of accessing constants in program memory. The first method is to use tables of RETLW instructions. The second method is to set an FSR to point to the program memory. 3.1.1.1 RETLW Instruction Stack Level 0 Stack Level 1 The RETLW instruction can be used to provide access to tables of constants.
PIC16(L)F1503 3.1.1.2 Indirect Read with FSR 3.2.1 The program memory can be accessed as data by setting bit 7 of the FSRxH register and reading the matching INDFx register. The MOVIW instruction will place the lower 8 bits of the addressed word in the W register. Writes to the program memory cannot be performed via the INDF registers. Instructions that access the program memory via the FSR require one extra instruction cycle to complete. Example 3-2 demonstrates accessing the program memory via an FSR.
PIC16(L)F1503 3.2.1.1 STATUS Register The STATUS register, shown in Register 3-1, contains: • the arithmetic status of the ALU • the Reset status The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable.
PIC16(L)F1503 3.2.2 SPECIAL FUNCTION REGISTER FIGURE 3-2: The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). The registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet. 3.2.
DS41607A-page 20 Preliminary Legend: 07Fh 06Fh 070h 00Bh 00Ch 00Dh 00Eh 00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh 020h 000h 0FFh 0EFh 0F0h 0BFh 0C0h 09Dh 09Eh 09Fh 0A0h 08Bh 08Ch 08Dh 08Eh 08Fh 090h 091h 092h 093h 094h 095h 096h 097h 098h 099h 09Ah 09Bh 09Ch Common RAM (Accesses 70h – 7Fh) Unimplemented Read as ‘0’ ADCON0 ADCON1 ADCON2 General Purpose Register 32 Bytes TRISA — TRISC — — PIE1 PIE2 PIE3 — OPTION_REG PCON WDTCON — OSCCON OSCSTAT ADRESL
2011 Microchip Technology Inc.
DS41607A-page 22 Preliminary Legend: CFFh C6Fh C70h C0Bh C0Ch C0Dh C0Eh C0Fh C10h C11h C12h C13h C14h C15h C16h C17h C18h C19h C1Ah C1Bh C1Ch C1Dh C1Eh C1Fh C20h C00h CFFh CEFh CF0h C8Bh C8Ch C8Dh C8Eh C8Fh C90h C91h C92h C93h C94h C95h C96h C97h C98h C99h C9Ah C9Bh C9Ch C9Dh C9Eh C9Fh CA0h Common RAM (Accesses 70h – 7Fh) Unimplemented Read as ‘0’ — — — — — — — — — — — — — — — — — — — — Core Registers (Table 3-2) BANK 25 D7Fh D6Fh D70h D0Bh D0Ch D0Dh D0Eh D0Fh D10h D11h D12h D13h D14h D15h
PIC16(L)F1503 TABLE 3-3: PIC16(L)F1503 MEMORY MAP (CONTINUED) Bank 31 Bank 30 F0Ch F0Dh F0Eh F0Fh F10h F11h F12h F13h F14h F15h F16h F17h F18h F19h F1Ah F1Bh F1Ch F1Dh F1Eh F1Fh F20h F6Fh Legend: F8Ch — — — CLCDATA CLC1CON CLC1POL CLC1SEL0 CLC1SEL1 CLC1GLS0 CLC1GLS1 CLC1GLS2 CLC1GLS3 CLC2CON CLC2POL CLC2SEL0 CLC2SEL1 CLC2GLS0 CLC2GLS1 CLC2GLS2 CLC2GLS3 Unimplemented Read as ‘0’ FE3h FE4h FE5h FE6h FE7h FE8h FE9h FEAh FEBh FECh FEDh FEEh FEFh STATUS_SHAD WREG_SHAD BSR_SHAD PCLATH_SHAD FSR0L_SHAD FSR0H
PIC16(L)F1503 3.2.6 CORE FUNCTION REGISTERS SUMMARY The Core Function registers listed in Table 3-4 can be addressed from any Bank.
PIC16(L)F1503 TABLE 3-5: Address SPECIAL FUNCTION REGISTER SUMMARY Name Value on all other Resets Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --xx xxxx — RC5 RC4 RC3 RC2 RC1 RC0 --xx xxxx --xx xxxx Bank 0 00Ch PORTA 00Dh — 00Eh PORTC 00Fh — Unimplemented — — 010h — Unimplemented — — 011h PIR1 TMR1GIF ADIF — — SSP1IF — Unimplemented — — TMR2IF — TMR1IF 00-- 0-00 00-- 0-00 012h PIR2 — C2I
PIC16(L)F1503 TABLE 3-5: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Value on POR, BOR Value on all other Resets Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 — — LATA5 LATA4 — LATA2 LATA1 LATA0 --xx -xxx --uu -uuu — LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 --xx xxxx --uu uuuu Bank 2 10Ch LATA 10Dh — 10Eh LATC 10Fh — Unimplemented — — 110h — Unimplemented — — 111h CM1CON0 C1ON C1OUT 112h CM1CON1 C1INTP C1INTN 113h CM2CON0 C2ON C2OUT 114h
PIC16(L)F1503 TABLE 3-5: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Value on POR, BOR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 Value on all other Resets Bank 4 20Ch 20Dh to 210h WPUA --11 1111 --11 1111 — Unimplemented 211h SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 212h SSP1ADD ADD<7:0> 0000 0000 0000 0000 213h SSP1MSK MSK<7:0> 214h SSP1STAT SMP CKE D/A P 215h
PIC16(L)F1503 TABLE 3-5: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Value on POR, BOR Value on all other Resets Unimplemented — — Unimplemented — — Unimplemented — — Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bank 10 50Ch to 51Fh — Bank 11 58Ch to 59Fh — Bank 12 60Ch to 610h — 611h PWM1DCL 612h PWM1DCH 613h PWM1CON0 614h PWM2DCL 615h PWM2DCH 616h PWM2CON0 617h PWM3DCL 618h PWM3DCH 619h PWM3CON0 61Ah PWM4DCL 61Bh PWM4DCH 61Ch PWM4CON0 6
PIC16(L)F1503 TABLE 3-5: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on POR, BOR Value on all other Resets Unimplemented — — Unimplemented — — Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Banks 14-29 x0Ch/ x8Ch — x1Fh/ x9Fh — Bank 30 F0Ch to F0Eh — F0Fh CLCDATA — — — — — F10h CLC1CON LC1EN LC1OE LC1OUT LC1INTP LC1INTN F11h CLC1POL LC1POL — — — — MLC1OUT MLC2OUT LC1MODE<2:0> LC1G4POL LC1G3POL LC1G2POL ---- --00 ---- --00 0000 0000 0000 00
PIC16(L)F1503 TABLE 3-5: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets — — Bank 31 F8Ch — FE3h — FE4h STATUS_ Unimplemented — — — — — Z_SHAD DC_SHAD C_SHAD ---- -xxx ---- -uuu SHAD FE5h WREG_ Working Register Shadow xxxx xxxx uuuu uuuu SHAD FE6h BSR_ — — — Bank Select Register Shadow ---x xxxx ---u uuuu SHAD FE7h PCLATH_ — Program Counter Latch High Register Shad
PIC16(L)F1503 3.3 PCL and PCLATH 3.3.2 The Program Counter (PC) is 15 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<14:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 3-3 shows the five situations for the loading of the PC.
PIC16(L)F1503 3.4 Stack 3.4.1 The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack. Both registers are read/writable. TOS is split into TOSH and TOSL due to the 15-bit size of the PC. To access the stack, adjust the value of STKPTR, which will position TOSH:TOSL, then read/write to TOSH:TOSL. STKPTR is 5 bits to allow detection of overflow and underflow.
PIC16(L)F1503 FIGURE 3-5: ACCESSING THE STACK EXAMPLE 2 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 This figure shows the stack configuration after the first CALL or a single interrupt. If a RETURN instruction is executed, the return address will be placed in the Program Counter and the Stack Pointer decremented to the empty state (0x1F).
PIC16(L)F1503 FIGURE 3-7: ACCESSING THE STACK EXAMPLE 4 TOSH:TOSL 3.4.
PIC16(L)F1503 FIGURE 3-8: INDIRECT ADDRESSING 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory 0x29AF 0x29B0 FSR Address Range Reserved 0x7FFF 0x8000 0x0000 Program Flash Memory 0xFFFF Note: 0x7FFF Not all memory regions are completely implemented. Consult device memory tables for memory limits. 2011 Microchip Technology Inc.
PIC16(L)F1503 3.5.1 TRADITIONAL DATA MEMORY The traditional data memory is a region from FSR address 0x000 to FSR address 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers.
PIC16(L)F1503 3.5.2 3.5.3 LINEAR DATA MEMORY The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the banks. Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the FSR beyond one bank will go directly to the GPR memory of the next bank.
PIC16(L)F1503 NOTES: DS41607A-page 38 Preliminary 2011 Microchip Technology Inc.
PIC16(L)F1503 4.0 DEVICE CONFIGURATION Device Configuration consists of Configuration Words, Code Protection and Device ID. 4.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h. 2011 Microchip Technology Inc.
PIC16(L)F1503 REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1 U-1 U-1 R/P-1 — — CLKOUTEN R/P-1 R/P-1 U-1 BOREN<1:0> — bit 13 R/P-1 R/P-1 R/P-1 CP MCLRE PWRTE bit 8 R/P-1 R/P-1 U-1 WDTE<1:0> R/P-1 R/P-1 FOSC<1:0> — bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase bit 13-12 Unimplemented: Read as ‘1’ bit 11 CLKOUTEN: Clock Out Enable bit 1 = CLKOUT functi
PIC16(L)F1503 REGISTER 4-2: CONFIG2: CONFIGURATION WORD 2 R/P-1 U-1 R/P-1 R/P-1 R/P-1 U-1 LVP — LPBOR BORV STVREN — bit 13 bit 8 U-1 U-1 U-1 U-1 U-1 U-1 — — — — — — R/P-1 R/P-1 WRT<1:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase bit 13 LVP: Low-Voltage Programming Enable bit(1) 1 = Low-voltage programming enabled 0 = High-voltage on MCLR mus
PIC16(L)F1503 4.2 Code Protection Code protection allows the device to be protected from unauthorized access. Internal access to the program memory is unaffected by any code protection setting. 4.2.1 PROGRAM MEMORY PROTECTION The entire program memory space is protected from external reads and writes by the CP bit in Configuration Words. When CP = 0, external reads and writes of program memory are inhibited and a read will return all ‘0’s.
PIC16(L)F1503 4.5 Device ID and Revision ID The memory location 8006h is where the Device ID and Revision ID are stored. The upper nine bits hold the Device ID. The lower five bits hold the Revision ID. See Section 10.4 “User ID, Device ID and Configuration Word Access” for more information on accessing these memory locations. Development tools, such as device programmers and debuggers, may be used to read the Device ID and Revision ID.
PIC16(L)F1503 NOTES: DS41607A-page 44 Preliminary 2011 Microchip Technology Inc.
PIC16(L)F1503 5.0 OSCILLATOR MODULE The oscillator module can be configured in one of the following clock modes. 5.1 Overview 1. The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 5-1 illustrates a block diagram of the oscillator module. 2. 3. 4. ECL – External Clock Low-Power mode (0 MHz to 0.5 MHz) ECM – External Clock Medium-Power mode (0.
PIC16(L)F1503 5.2 Clock Source Types 5.2.1.1 Clock sources can be classified as external or internal. External clock sources rely on external circuitry for the clock source to function. Examples are: oscillator modules (EC mode). Internal clock sources are contained within the oscillator module.
PIC16(L)F1503 5.2.2 INTERNAL CLOCK SOURCES 5.2.2.2 The device may be configured to use the internal oscillator block as the system clock by performing one of the following actions: • Program the FOSC<1:0> bits in Configuration Words to select the INTOSC clock source, which will be used as the default system clock upon a device Reset. • Write the SCS<1:0> bits in the OSCCON register to switch the system clock source to the internal oscillator during run-time. See Section 5.
PIC16(L)F1503 5.2.2.3 Internal Oscillator Frequency Selection 5.2.2.4 The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register. The outputs of the 16 MHz HFINTOSC postscaler and the LFINTOSC connect to a multiplexer (see Figure 5-1). The Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register select the frequency output of the internal oscillators.
PIC16(L)F1503 FIGURE 5-3: HFINTOSC INTERNAL OSCILLATOR SWITCH TIMING LFINTOSC (WDT disabled) HFINTOSC Start-up Time 2-cycle Sync Running 2-cycle Sync Running LFINTOSC IRCF <3:0> 0 0 System Clock HFINTOSC LFINTOSC (WDT enabled) HFINTOSC LFINTOSC 0 IRCF <3:0> 0 System Clock LFINTOSC HFINTOSC LFINTOSC turns off unless WDT is enabled LFINTOSC Start-up Time 2-cycle Sync Running HFINTOSC IRCF <3:0> =0 0 System Clock 2011 Microchip Technology Inc.
PIC16(L)F1503 5.3 Clock Switching 5.3.1 The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bits of the OSCCON register.
PIC16(L)F1503 5.
PIC16(L)F1503 REGISTER 5-2: OSCSTAT: OSCILLATOR STATUS REGISTER U-0 U-0 U-0 R-0/q U-0 U-0 R-0/q R-0/q — — — HFIOFR — — LFIOFR HFIOFS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Conditional bit 7-5 Unimplemented: Read as ‘0’ bit 4 HFIOFR: High-Frequency Internal Oscillator Ready bit 1 = 16 MHz Inter
PIC16(L)F1503 6.0 RESETS There are multiple ways to reset this device: • • • • • • • • • Power-on Reset (POR) Brown-out Reset (BOR) Low-Power Brown-out Reset (LPBOR) MCLR Reset WDT Reset RESET instruction Stack Overflow Stack Underflow Programming mode exit To allow VDD to stabilize, an optional Power-up Timer can be enabled to extend the Reset time after a BOR or POR event. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 6-1.
PIC16(L)F1503 6.1 Power-on Reset (POR) 6.2 Brown-Out Reset (BOR) The POR circuit holds the device in Reset until VDD has reached an acceptable level for minimum operation. Slow rising VDD, fast operating speeds or analog performance may require greater than minimum VDD. The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met. The BOR circuit holds the device in Reset when VDD reaches a selectable minimum level.
PIC16(L)F1503 FIGURE 6-2: BROWN-OUT SITUATIONS VDD VBOR Internal Reset TPWRT(1) VDD VBOR Internal Reset < TPWRT TPWRT(1) VDD VBOR Internal Reset Note 1: TPWRT(1) TPWRT delay only if PWRTE bit is programmed to ‘0’.
PIC16(L)F1503 6.3 Low-Power Brown-out Reset (LPBOR) 6.5 The Low-Power Brown-Out Reset (LPBOR) is an essential part of the Reset subsystem. Refer to Figure 6-1 to see how the BOR interacts with other modules. The LPBOR is used to monitor the external VDD pin. When too low of a voltage is detected, the device is held in Reset. When this occurs, a register bit (BOR) is changed to indicate that a BOR Reset has occurred. The same bit is set for both the BOR and the LPBOR. Refer to Register 6-2. 6.3.
PIC16(L)F1503 FIGURE 6-3: RESET START-UP SEQUENCE VDD Internal POR TPWRT Power-Up Timer MCLR TMCLR Internal RESET Internal Oscillator Oscillator FOSC External Clock (EC) CLKIN FOSC 2011 Microchip Technology Inc.
PIC16(L)F1503 6.11 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON register are updated to indicate the cause of the Reset. Table 6-3 and Table 6-4 show the Reset conditions of these registers.
PIC16(L)F1503 6.12 Power Control (PCON) Register The Power Control (PCON) register contains flag bits to differentiate between a: • • • • • • • Power-on Reset (POR) Brown-out Reset (BOR) Reset Instruction Reset (RI) MCLR Reset (RMCLR) Watchdog Timer Reset (RWDT) Stack Underflow Reset (STKUNF) Stack Overflow Reset (STKOVF) The PCON register bits are shown in Register 6-2.
PIC16(L)F1503 TABLE 6-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BORCON SBOREN BORFS — — — — — BORRDY 55 PCON STKOVF STKUNF — RWDT RMCLR RI POR BOR 59 STATUS — — — TO PD Z DC C 18 WDTCON — — SWDTEN 81 WDTPS<4:0> Legend: — = unimplemented bit, reads as ‘0’. Shaded cells are not used by Resets.
PIC16(L)F1503 7.0 INTERRUPTS The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode. This chapter contains the following information for Interrupts: • • • • • Operation Interrupt Latency Interrupts During Sleep INT Pin Automatic Context Saving Many peripherals produce interrupts. Refer to the corresponding chapters for details.
PIC16(L)F1503 7.1 Operation 7.2 Interrupts are disabled upon any device Reset.
PIC16(L)F1503 FIGURE 7-2: INTERRUPT LATENCY Fosc Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKR Interrupt Sampled during Q1 Interrupt GIE PC Execute PC-1 PC 1 Cycle Instruction at PC PC+1 0004h 0005h Inst(PC) NOP NOP Inst(0004h) PC+1/FSR ADDR New PC/ PC+1 0004h 0005h Inst(PC) NOP NOP Inst(0004h) FSR ADDR PC+1 PC+2 0004h 0005h INST(PC) NOP NOP NOP Inst(0004h) Inst(0005h) FSR ADDR PC+1 0004h 0005h INST(PC) NOP NOP
PIC16(L)F1503 FIGURE 7-3: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 FOSC CLKOUT (3) INT pin (1) (1) INTF Interrupt Latency (2) (4) GIE INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: PC Inst (PC) Inst (PC – 1) PC + 1 Inst (PC + 1) Inst (PC) PC + 1 — Forced NOP 0004h 0005h Inst (0004h) Inst (0005h) Forced NOP Inst (0004h) INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3-5 TCY.
PIC16(L)F1503 7.3 Interrupts During Sleep Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction.
PIC16(L)F1503 7.6 Interrupt Control Registers 7.6.1 Note: INTCON REGISTER The INTCON register is a readable and writable register, that contains the various enable and flag bits for TMR0 register overflow, interrupt-on-change and external INT pin interrupts. REGISTER 7-1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE, of the INTCON register.
PIC16(L)F1503 7.6.2 PIE1 REGISTER The PIE1 register contains the interrupt enable bits, as shown in Register 7-2. REGISTER 7-2: Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
PIC16(L)F1503 7.6.3 PIE2 REGISTER The PIE2 register contains the interrupt enable bits, as shown in Register 7-3. REGISTER 7-3: Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
PIC16(L)F1503 7.6.4 PIE3 REGISTER The PIE3 register contains the interrupt enable bits, as shown in Register 7-4. REGISTER 7-4: Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
PIC16(L)F1503 7.6.5 PIR1 REGISTER The PIR1 register contains the interrupt flag bits, as shown in Register 7-5. REGISTER 7-5: Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16(L)F1503 7.6.6 PIR2 REGISTER The PIR2 register contains the interrupt flag bits, as shown in Register 7-6. REGISTER 7-6: Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16(L)F1503 7.6.7 PIR3 REGISTER The PIR3 register contains the interrupt flag bits, as shown in Register 7-7. REGISTER 7-7: Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16(L)F1503 TABLE 7-1: Name INTCON SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 66 OPTION_REG WPUEN PIE1 INTEDG TMR0CS TMR0SE PSA PS<2:0> TMR1GIE ADIE — — SSP1IE — C1IE TMR2IE 146 TMR1IE 67 PIE2 — C2IE — BCLIE NCO1IE — — 68 PIE3 — — — — — — CLC2IE CLC1IE 69 PIR1 TMR1GIF ADIF — — SSP1IF — TMR2IF TMR1IF 70 PIR2 — C2IF C1IF — BCL1I
PIC16(L)F1503 NOTES: DS41607A-page 74 Preliminary 2011 Microchip Technology Inc.
PIC16(L)F1503 8.0 POWER-DOWN MODE (SLEEP) The Power-Down mode is entered by executing a SLEEP instruction. Upon entering Sleep mode, the following conditions exist: 1. 2. 3. 4. 5. 6. 7. 8. WDT will be cleared but keeps running, if enabled for operation during Sleep. PD bit of the STATUS register is cleared. TO bit of the STATUS register is set. CPU clock is disabled. 31 kHz LFINTOSC is unaffected and peripherals that operate from it may continue operation in Sleep.
PIC16(L)F1503 Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP.
PIC16(L)F1503 8.2 Low-Power Sleep Mode 8.2.2 The PIC16F1503 device contains an internal Low Dropout (LDO) voltage regulator, which allows the device I/O pins to operate at voltages up to 5.5V while the internal device logic operates at a lower voltage. The LDO and its associated reference circuitry must remain active when the device is in Sleep mode. The PIC16F1503 allows the user to optimize the operating current in Sleep, depending on the application requirements.
PIC16(L)F1503 VREGCON: VOLTAGE REGULATOR CONTROL REGISTER(1) REGISTER 8-1: U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-1/1 — — — — — — VREGPM Reserved bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1 VREGPM: Voltage Regulator Power Mode Selection bit 1 = Low-Power Sleep mode e
PIC16(L)F1503 9.0 WATCHDOG TIMER The Watchdog Timer is a system timer that generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The Watchdog Timer is typically used to recover the system from unexpected events.
PIC16(L)F1503 9.1 Independent Clock Source 9.3 Time-Out Period The WDT derives its time base from the 31 kHz LFINTOSC internal oscillator. Time intervals in this chapter are based on a nominal interval of 1 ms. See Section 28.0 “Electrical Specifications” for the LFINTOSC tolerances. The WDTPS bits of the WDTCON register set the time-out period from 1 ms to 256 seconds (nominal). After a Reset, the default time-out period is 2 seconds. 9.
PIC16(L)F1503 9.
PIC16(L)F1503 TABLE 9-3: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER Name Bit 7 OSCCON Bit 6 — PCON Bit 5 Bit 4 Bit 3 IRCF<3:0> STKUNF — RWDT STATUS — — — TO WDTCON — — CONFIG1 Legend: Bit 0 SCS<1:0> RMCLR RI POR PD Z DC WDTPS<4:0> Register on Page 51 BOR 59 C 18 SWDTEN 81 x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Watchdog Timer.
PIC16(L)F1503 10.0 FLASH PROGRAM MEMORY CONTROL The Flash program memory is readable and writable during normal operation over the VDD range specified in the Electrical Specification. See Section 28.0 “Electrical Specifications”. Program memory is indirectly addressed using Special Function Registers (SFRs). The SFRs used to access program memory are: • • • • • • PMCON1 PMCON2 PMDATL PMDATH PMADRL PMADRH Control bits RD and WR initiate read and write, respectively.
PIC16(L)F1503 10.2.1 READING THE FLASH PROGRAM MEMORY FIGURE 10-1: To read a program memory location, the user must: 1. 2. 3. Write the desired address to the PMADRH:PMADRL register pair. Clear the CFGS bit of the PMCON1 register. Then, set control bit RD of the PMCON1 register. Once the read control bit is set, the program memory Flash controller will use the second instruction cycle to read the data.
PIC16(L)F1503 FIGURE 10-2: FLASH PROGRAM MEMORY READ CYCLE EXECUTION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC Flash ADDR Flash Data PC + 1 INSTR (PC) INSTR(PC - 1) executed here PC +3 PC+3 PMADRH,PMADRL INSTR (PC + 1) BSF PMCON1,RD executed here PMDATH,PMDATL INSTR(PC + 1) instruction ignored Forced NOP executed here PC + 4 INSTR (PC + 3) INSTR(PC + 2) instruction ignored Forced NOP executed here PC + 5 INSTR (PC + 4) INSTR(PC + 3) executed here INSTR(P
PIC16(L)F1503 10.2.2 FLASH MEMORY UNLOCK SEQUENCE FIGURE 10-3: The unlock sequence is a mechanism that protects the Flash program memory from unintended self-write programming or erasing.
PIC16(L)F1503 10.2.3 ERASING FLASH PROGRAM MEMORY FIGURE 10-4: While executing code, program memory can only be erased by rows. To erase a row: 1. 2. 3. 4. 5. Load the PMADRH:PMADRL register pair with any address within the row to be erased. Clear the CFGS bit of the PMCON1 register. Set the FREE and WREN bits of the PMCON1 register. Write 55h, then AAh, to PMCON2 (Flash programming unlock sequence). Set control bit WR of the PMCON1 register to begin the erase operation. See Example 10-2.
PIC16(L)F1503 EXAMPLE 10-2: ERASING ONE ROW OF PROGRAM MEMORY Required Sequence ; This row erase routine assumes the following: ; 1. A valid address within the erase row is loaded in ADDRH:ADDRL ; 2.
PIC16(L)F1503 10.2.4 WRITING TO FLASH PROGRAM MEMORY Program memory is programmed using the following steps: 1. 2. 3. 4. Load the address in PMADRH:PMADRL of the row to be programmed. Load each write latch with data. Initiate a programming operation. Repeat steps 1 through 3 until all data is written. The following steps should be completed to load the write latches and program a row of program memory. These steps are divided into two parts.
6 r10 7 - r9 FIGURE 10-5: r8 r7 r6 PMADRH DS41607A-page 90 11 r4 r3 r2 PMADRH<6:0> :PMADRL<7:4> r5 0 7 r1 c3 Preliminary c0 CFGS = 0 PMADRL<4:0> 4 c1 0 CFGS = 1 c2 PMADRL Row Address Decode r0 5 4 0000h 0010h 0020h 7FE0h 000h 001h 002h 7FEh 800h PMDATH 6 8004h - 8005h reserved USER ID 0 - 3 7FF1h 7FE1h 0021h 0011h 0001h Addr 14 Write Latch #1 01h 14 8000h - 8003h 7FF0h Addr 14 Write Latch #0 00h 14 Row 7FFh - 5 0 14 7 14 0 Configuration Words
PIC16(L)F1503 FIGURE 10-6: FLASH PROGRAM MEMORY WRITE FLOWCHART Start Write Operation Determine number of words to be written into Program or Configuration Memory. The number of words cannot exceed the number of words per row. (word_cnt) Disable Interrupts (GIE = 0) Select Program or Config.
PIC16(L)F1503 EXAMPLE 10-3: ; ; ; ; ; ; ; WRITING TO FLASH PROGRAM MEMORY This write routine assumes the following: 1. 32 bytes of data are loaded, starting at the address in DATA_ADDR 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR, stored in little endian format 3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL 4.
PIC16(L)F1503 10.3 Modifying Flash Program Memory FIGURE 10-7: When modifying existing data in a program memory row, and data within that row must be preserved, it must first be read and saved in a RAM image. Program memory is modified using the following steps: 1. 2. 3. 4. 5. 6. 7. Load the starting address of the row to be modified. Read the existing data from the row into a RAM image. Modify the RAM image to contain the new data to be written into program memory.
PIC16(L)F1503 10.4 User ID, Device ID and Configuration Word Access Instead of accessing program memory, the User ID’s, Device ID/Revision ID and Configuration Words can be accessed when CFGS = 1 in the PMCON1 register. This is the region that would be pointed to by PC<15> = 1, but not all addresses are accessible. Different access may exist for reads and writes. Refer to Table 10-2.
PIC16(L)F1503 10.5 Write Verify It is considered good programming practice to verify that program memory writes agree with the intended value. Since program memory is stored as a full page then the stored program memory contents are compared with the intended data stored in RAM after the last write is complete. FIGURE 10-8: FLASH PROGRAM MEMORY VERIFY FLOWCHART Start Verify Operation This routine assumes that the last row of data written was from an image saved in RAM.
PIC16(L)F1503 10.
PIC16(L)F1503 REGISTER 10-5: PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER U-1(1) R/W-0/0 R/W-0/0 R/W/HC-0/0 R/W/HC-x/q R/W-0/0 R/S/HC-0/0 R/S/HC-0/0 — CFGS LWLO FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 Unimplemented: Read as ‘1’ bit 6 CFGS
PIC16(L)F1503 REGISTER 10-6: W-0/0 PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 Program Memory Control Register 2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Flash Memory Unlock Pattern bits To unlock writes, a 55h must be written first, followed by an AAh, before s
PIC16(L)F1503 11.0 I/O PORTS FIGURE 11-1: GENERIC I/O PORT OPERATION Each port has three standard registers for its operation. These registers are: • TRISx registers (data direction) • PORTx registers (reads the levels on the pins of the device) • LATx registers (output latch) Read LATx D Some ports may have one or more of the following additional registers.
PIC16(L)F1503 11.1 Alternate Pin Function The Alternate Pin Function Control register is used to steer specific peripheral input and output functions between different pins. The APFCON register is shown in Register 11-1. For this device family, the following functions can be moved between different pins. • • • • • SDO SS T1G CLC1 NCO1 These bits have no effect on the values of any TRIS register. PORT and TRIS overrides will be routed to the correct pin. The unselected pin will be unaffected.
PIC16(L)F1503 11.2 PORTA Registers 11.2.2 PORTA is a 6-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 11-3). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin).
PIC16(L)F1503 REGISTER 11-2: PORTA: PORTA REGISTER U-0 U-0 R/W-x/x R/W-x/x R-x/x R/W-x/x R/W-x/x R/W-x/x — — RA5 RA4 RA3 RA2 RA1 RA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RA<5:0>: PORTA I/O Value bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL Note 1
PIC16(L)F1503 REGISTER 11-4: LATA: PORTA DATA LATCH REGISTER U-0 U-0 R/W-x/u R/W-x/u U-0 R/W-x/u R/W-x/u R/W-x/u — — LATA5 LATA4 — LATA2 LATA1 LATA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 LATA<5:4>: RA<5:4> Output Latch Value bits(1) bit 3 Unimplemented:
PIC16(L)F1503 REGISTER 11-6: WPUA: WEAK PULL-UP PORTA REGISTER U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 WPUA<5:0>: Weak Pull-up Register bits(3) 1 = Pull-up enabl
PIC16(L)F1503 11.3 PORTC Registers 11.3.2 PORTC is a 6-bit wide, bidirectional port. The corresponding data direction register is TRISC (Register 11-8). Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin).
PIC16(L)F1503 REGISTER 11-7: PORTC: PORTC REGISTER U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — RC5 RC4 RC3 RC2 RC1 RC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RC<5:0>: PORTC General Purpose I/O Pin bits 1 = Port pin is > VIH 0 = Port pin is
PIC16(L)F1503 REGISTER 11-10: ANSELC: PORTC ANALOG SELECT REGISTER U-0 U-0 U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — — — ANSC3 ANSC2 ANSC1 ANSC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 ANSC<3:0>: Analog Select between Analog or Digital Function on pins RC<3
PIC16(L)F1503 NOTES: DS41607A-page 108 Preliminary 2011 Microchip Technology Inc.
PIC16(L)F1503 12.0 INTERRUPT-ON-CHANGE 12.3 The PORTA and PORTB pins can be configured to operate as Interrupt-On-Change (IOC) pins. An interrupt can be generated by detecting a signal that has either a rising edge or a falling edge. Any individual port pin, or combination of port pins, can be configured to generate an interrupt.
PIC16(L)F1503 FIGURE 12-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM (PORTA EXAMPLE) IOCANx D Q4Q1 Q CK Edge Detect R RAx IOCAPx D Data Bus = 0 or 1 Q Write IOCAFx CK D S Q To Data Bus IOCAFx CK IOCIE R Q2 From all other IOCAFx individual Pin Detectors Q1 Q2 Q3 Q4 Q4Q1 DS41607A-page 110 Q1 Q1 Q2 Q2 Q3 Q4 Q4Q1 IOC interrupt to CPU core Q3 Q4 Q4 Q4Q1 Preliminary Q4Q1 2011 Microchip Technology Inc.
PIC16(L)F1503 12.
PIC16(L)F1503 TABLE 12-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 103 INTCON Name GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 66 IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 111 IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 111 IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 111 TRISA4 —(1) TRISA2 TRISA1 TR
PIC16(L)F1503 13.0 FIXED VOLTAGE REFERENCE (FVR) The Fixed Voltage Reference, or FVR, is a stable voltage reference, independent of VDD, with 1.024V, 2.048V or 4.096V selectable output levels. The output of the FVR can be configured to supply a reference voltage to the following: • ADC input channel • Comparator positive input • Comparator negative input The FVR can be enabled by setting the FVREN bit of the FVRCON register. 13.
PIC16(L)F1503 13.
PIC16(L)F1503 14.0 TEMPERATURE INDICATOR MODULE FIGURE 14-1: This family of devices is equipped with a temperature circuit designed to measure the operating temperature of the silicon die. The circuit’s range of operating temperature falls between -40°C and +85°C. The output is a voltage that is proportional to the device temperature. The output of the temperature indicator is internally connected to the device ADC.
PIC16(L)F1503 TABLE 14-2: Name FVRCON Legend: SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR Bit 7 Bit 6 Bit 5 Bit 4 FVREN FVRRDY TSEN TSRNG Bit 3 Bit 2 CDAFVR<1:0> Bit 1 Bit 0 ADFVR<1:0> Register on page 118 Shaded cells are unused by the temperature indicator module. DS41607A-page 116 Preliminary 2011 Microchip Technology Inc.
PIC16(L)F1503 15.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter.
PIC16(L)F1503 15.1 ADC Configuration 15.1.4 When configuring and using the ADC the following functions must be considered: • • • • • • Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Result formatting 15.1.1 The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits. Refer to Section 11.
PIC16(L)F1503 TABLE 15-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES ADC Clock Period (TAD) Device Frequency (FOSC) ADC Clock Source ADCS<2:0> 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz Fosc/2 000 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s Fosc/4 100 (2) 200 ns (2) 250 ns (2) Fosc/8 001 400 ns(2) 0.5 s(2) Fosc/16 101 800 ns 1.0 s Fosc/32 1.6 s 010 2.0 s Fosc/64 110 3.2 s 4.0 s FRC x11 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) Legend: Note 1: 2: 3: 4: 1.
PIC16(L)F1503 15.1.5 INTERRUPTS 15.1.6 The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. RESULT FORMATTING The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON1 register controls the output format.
PIC16(L)F1503 15.2 15.2.1 ADC Operation 15.2.4 STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a ‘1’. Setting the GO/ DONE bit of the ADCON0 register to a ‘1’ will start the Analog-to-Digital conversion. Note: 15.2.2 The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 15.2.6 “A/D Conversion Procedure”.
PIC16(L)F1503 15.2.6 A/D CONVERSION PROCEDURE EXAMPLE 15-1: This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. 2. 3. 4. 5. 6. 7. 8.
PIC16(L)F1503 15.2.7 ADC REGISTER DEFINITIONS The following registers are used to control the operation of the ADC.
PIC16(L)F1503 REGISTER 15-2: R/W-0/0 ADCON1: A/D CONTROL REGISTER 1 R/W-0/0 ADFM R/W-0/0 R/W-0/0 ADCS<2:0> U-0 U-0 — — R/W-0/0 R/W-0/0 ADPREF<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: A/D Result Format Select bit 1 = Right justified.
PIC16(L)F1503 REGISTER 15-3: R/W-0/0 ADCON2: A/D CONTROL REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 TRIGSEL<3:0> U-0 U-0 U-0 U-0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 TRIGSEL<3:0>: Auto-Conversion Trigger Selection bits(1) 0000 = No auto-conversion trigger selected 0001 = Reserved 0010 = Reserv
PIC16(L)F1503 REGISTER 15-4: R/W-x/u ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ADRES<9:2>: ADC Result Register bits Upper 8 bits of 10-bit conversion result REGISTER 15-5: R/W-x/u ADRE
PIC16(L)F1503 REGISTER 15-6: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — — — — — R/W-x/u R/W-x/u ADRES<9:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Reserved: Do not use.
PIC16(L)F1503 15.3 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 15-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), refer to Figure 15-4.
PIC16(L)F1503 FIGURE 15-4: ANALOG INPUT MODEL VDD Analog Input pin Rs VT 0.6V CPIN 5 pF VA RIC 1k Sampling Switch SS Rss I LEAKAGE(1) VT 0.
PIC16(L)F1503 TABLE 15-2: Name SUMMARY OF REGISTERS ASSOCIATED WITH ADC Bit 7 ADCON0 — ADCON1 ADFM ADCON2 Bit 6 Bit 5 Bit 4 Bit 2 — — ADPREF<1:0> 124 — — — 125 CHS<4:0> ADCS<2:0> TRIGSEL<3:0> Bit 1 Bit 0 GO/DONE ADON Register on Page Bit 3 — 123 ADRESH A/D Result Register High 126, 127 ADRESL A/D Result Register Low 126, 127 ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 103 ANSELC — — — — ANSC3 ANSC2 ANSC1 ANSC0 107 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0I
PIC16(L)F1503 16.0 DIGITAL-TO-ANALOG CONVERTER (DAC) MODULE The Digital-to-Analog Converter supplies a variable voltage reference, ratiometric with the input source, with 32 selectable output levels. The input of the DAC can be connected to: 16.1 Output Voltage Selection The DAC has 32 voltage level ranges. The 32 levels are set with the DACR<4:0> bits of the DACCON1 register.
PIC16(L)F1503 FIGURE 16-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM Digital-to-Analog Converter (DAC) VSOURCE+ VDD DACR<4:0> 5 VREF+ R R DACPSS R DACEN R 32 Steps R 32-to-1 MUX R DAC (To Comparator and ADC Module) R DACOUT1 R DACOE1 VSOURCE- DACOUT2 DACOE2 FIGURE 16-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC® MCU DAC Module R Voltage Reference Output Impedance DS41607A-page 132 DACOUTX Preliminary + – Buffered DAC Output 2011 Microchip Technology Inc.
PIC16(L)F1503 16.4 Operation During Sleep When the device wakes up from Sleep through an interrupt or a Watchdog Timer time-out, the contents of the DACCON0 register are not affected. To minimize current consumption in Sleep mode, the voltage reference should be disabled. 16.5 Effects of a Reset A device Reset affects the following: • DAC is disabled. • DAC output voltage is removed from the DACOUT pin. • The DACR<4:0> range select bits are cleared. 2011 Microchip Technology Inc.
PIC16(L)F1503 16.
PIC16(L)F1503 17.0 COMPARATOR MODULE FIGURE 17-1: Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. Comparators are very useful mixed signal building blocks because they provide analog functionality independent of program execution.
PIC16(L)F1503 FIGURE 17-2: COMPARATOR MODULES SIMPLIFIED BLOCK DIAGRAM CxNCH<2:0> CxON(1) 3 C12IN0- 0 C12IN1C12IN2- 1 MUX 2 (2) C12IN3- 3 FVR Buffer 4 det Set CxIF 0 MUX 1 (2) DAC FVR Buffer2 CxINTN Interrupt det CXPOL CxVN D Cx CxVP CXIN+ CxINTP Interrupt CXOUT MCXOUT Q To Data Bus + EN Q1 CxHYS CxSP async_CxOUT To CWG 2 3 CXSYNC CxON CXPCH<1:0> CXOE TRIS bit CXOUT 0 2 D (from Timer1) T1CLK Q 1 To Timer1 CLCX, ADC SYNC_CXOUT Note 1: 2: When CxON = 0, the comparator
PIC16(L)F1503 17.2 Comparator Control 17.2.3 Each comparator has 2 control registers: CMxCON0 and CMxCON1. The CMxCON0 registers (see Register 17-1) contain Control and Status bits for the following: • • • • • • Enable Output selection Output polarity Speed/Power selection Hysteresis enable Output synchronization Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs.
PIC16(L)F1503 17.3 Comparator Hysteresis 17.5 A selectable amount of separation voltage can be added to the input pins of each comparator to provide a hysteresis function to the overall operation. Hysteresis is enabled by setting the CxHYS bit of the CMxCON0 register. Comparator Interrupt An interrupt can be generated upon a change in the output value of the comparator for each comparator, a rising edge detector and a falling edge detector are present. See Section 28.
PIC16(L)F1503 17.7 Comparator Negative Input Selection 17.10 Analog Input Connection Considerations The CxNCH<1:0> bits of the CMxCON0 register direct one of the input sources to the comparator inverting input. Note: 17.8 To use CxIN+ and CxINx- pins as analog input, the appropriate bits must be set in the ANSEL register and the corresponding TRIS bits must also be set to disable the output drivers.
PIC16(L)F1503 FIGURE 17-3: ANALOG INPUT MODEL VDD Rs < 10K Analog Input pin VT 0.6V RIC To Comparator VA CPIN 5 pF VT 0.6V ILEAKAGE(1) Vss Legend: CPIN = Input Capacitance ILEAKAGE = Leakage Current at the pin due to various junctions = Interconnect Resistance RIC = Source Impedance RS = Analog Voltage VA = Threshold Voltage VT Note 1: DS41607A-page 140 See Section 28.0 “Electrical Specifications”. Preliminary 2011 Microchip Technology Inc.
PIC16(L)F1503 REGISTER 17-1: CMxCON0: COMPARATOR Cx CONTROL REGISTER 0 R/W-0/0 R-0/0 R/W-0/0 R/W-0/0 U-0 R/W-1/1 R/W-0/0 R/W-0/0 CxON CxOUT CxOE CxPOL — CxSP CxHYS CxSYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CxON: Comparator Enable bit 1 = Comparator is enabled and consumes no active power 0
PIC16(L)F1503 REGISTER 17-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1 R/W-0/0 R/W-0/0 CxINTP CxINTN R/W-0/0 R/W-0/0 CxPCH<1:0> U-0 R/W-0/0 R/W-0/0 R/W-0/0 CxNCH<2:0> — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CxINTP: Comparator Interrupt on Positive Going Edge Enable bits 1 = The CxIF interrupt fl
PIC16(L)F1503 TABLE 17-2: Name ANSELA ANSELC CM1CON0 SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — — ANSA4 — ANSA2 ANSA1 ANSA0 103 — — — — ANSC3 ANSC2 ANSC1 ANSC0 107 C1ON C1OUT C1OE C1POL — C1SP C1HYS C1SYNC 141 C2OE C2POL — C2SP C2HYS C2SYNC 141 CM2CON0 C2ON C2OUT CM1CON1 C1NTP C1INTN CM2CON1 C2NTP C2INTN — — — — — — MC2OUT MC1OUT 142 DACCON0 DACEN — DACOE1 DACOE
PIC16(L)F1503 18.0 TIMER0 MODULE 18.1.2 8-BIT COUNTER MODE The Timer0 module is an 8-bit timer/counter with the following features: In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin. • • • • • • 8-Bit Counter mode using the T0CKI pin is selected by setting the TMR0CS bit in the OPTION_REG register to ‘1’.
PIC16(L)F1503 18.1.3 SOFTWARE PROGRAMMABLE PRESCALER A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION_REG register. Note: The Watchdog Timer (WDT) uses its own independent prescaler. There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION_REG register.
PIC16(L)F1503 18.
PIC16(L)F1503 NOTES: 2011 Microchip Technology Inc.
PIC16(L)F1503 19.0 TIMER1 MODULE WITH GATE CONTROL • Gate Single-Pulse mode • Gate Value Status • Gate Event Interrupt The Timer1 module is a 16-bit timer/counter with the following features: Figure 19-1 is a block diagram of the Timer1 module.
PIC16(L)F1503 19.1 Timer1 Operation 19.2 The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and increments on every selected edge of the external source.
PIC16(L)F1503 19.3 Timer1 Prescaler Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L. 19.4 Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC of the T1CON register is set, the external clock input is not synchronized.
PIC16(L)F1503 19.5.2.1 T1G Pin Gate Operation 19.5.5 The T1G pin is one source for Timer1 Gate Control. It can be used to supply an external source to the Timer1 gate circuitry. 19.5.2.2 Timer0 Overflow Gate Operation When Timer0 increments from FFh to 00h, a low-to-high pulse will automatically be generated and internally supplied to the Timer1 gate circuitry. 19.5.
PIC16(L)F1503 19.6 Timer1 Interrupt 19.7.1 The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set.
PIC16(L)F1503 FIGURE 19-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL t1g_in T1CKI T1GVAL Timer1 N FIGURE 19-4: N+1 N+2 N+3 N+4 TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM t1g_in T1CKI T1GVAL Timer1 N 2011 Microchip Technology Inc.
PIC16(L)F1503 FIGURE 19-5: TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G t1g_in T1CKI T1GVAL Timer1 TMR1GIF DS41607A-page 154 N N+1 N+2 Set by hardware on falling edge of T1GVAL Cleared by software Preliminary Cleared by software 2011 Microchip Technology Inc.
PIC16(L)F1503 FIGURE 19-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G t1g_in T1CKI T1GVAL Timer1 TMR1GIF N Cleared by software 2011 Microchip Technology Inc.
PIC16(L)F1503 19.
PIC16(L)F1503 REGISTER 19-2: T1GCON: TIMER1 GATE CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ DONE T1GVAL R/W-0/u R/W-0/u T1GSS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 TMR1GE: Timer1 Gate Enable bit If T
PIC16(L)F1503 TABLE 19-5: Name SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Bit 7 Bit 6 ANSELA — APFCON — INTCON PIE1 PIR1 Bit 5 Bit 4 — — — SDOSEL Bit 2 ANSA4 — ANSA2 ANSA1 ANSA0 103 SSSEL T1GSEL — CLC1SEL NCO1SEL 100 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 66 ADIE — — SSP1IE — TMR2IE TMR1IE 67 TMR1GIF ADIF — — SSP1IF — TMR2IF TMR1IF Holding Register for the Most Significant Byte of the 16-bit TMR1 Count TMR1L Holding Register for the Least Signific
PIC16(L)F1503 NOTES: 2011 Microchip Technology Inc.
PIC16(L)F1503 20.0 TIMER2 MODULE The Timer2 module incorporates the following features: • 8-bit Timer and Period registers (TMR2 and PR2, respectively) • Readable and writable (both registers) • Software programmable prescaler (1:1, 1:4, 1:16, and 1:64) • Software programmable postscaler (1:1 to 1:16) • Interrupt on TMR2 match with PR2, respectively See Figure 20-1 for a block diagram of Timer2.
PIC16(L)F1503 20.1 Timer2 Operation 20.3 The clock input to the Timer2 module is the system instruction clock (FOSC/4). TMR2 increments from 00h on each clock edge. A 4-bit counter/prescaler on the clock input allows direct input, divide-by-4 and divide-by-16 prescale options. These options are selected by the prescaler control bits, T2CKPS<1:0> of the T2CON register. The value of TMR2 is compared to that of the Period register, PR2, on each clock cycle.
PIC16(L)F1503 REGISTER 20-1: U-0 T2CON: TIMER2 CONTROL REGISTER R/W-0/0 — R/W-0/0 R/W-0/0 R/W-0/0 T2OUTPS<3:0> R/W-0/0 R/W-0/0 TMR2ON R/W-0/0 T2CKPS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-3 T2OUTPS<3:0>: Timer2 Output Postscaler Select bits 0000 = 1:1 Postsca
PIC16(L)F1503 TABLE 20-1: Name INTCON SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 66 PIE1 TMR1GIE ADIE — — SSP1IE — TMR2IE TMR1IE 67 PIR1 TMR1GIF ADIF — — SSP1IF — TMR2IF TMR1IF PR2 Timer2 Module Period Register 70 160* PWM1CON PWM1EN PWM1OE PWM1OUT PWM1POL — — — — 222 PWM2CON PWM2EN PWM2OE PWM2OUT PWM2POL — — — — 222 PWM3CON PWM3EN PWM3O
PIC16(L)F1503 21.0 MASTER SYNCHRONOUS SERIAL PORT MODULE 21.1 Master SSP (MSSP) Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc.
PIC16(L)F1503 The I2C interface supports the following modes and features: Master mode Slave mode Byte NACKing (Slave mode) Limited Multi-master support 7-bit and 10-bit addressing Start and Stop interrupts Interrupt masking Clock stretching Bus collision detection General call address matching Address masking Address Hold and Data Hold modes Selectable SDAx hold times Note 1: In devices with more than one MSSP module, it is very important to pay close attention to SSPxCONx register names.
PIC16(L)F1503 FIGURE 21-3: MSSPX BLOCK DIAGRAM (I2C™ SLAVE MODE) Internal Data Bus Read Write SSPxBUF Reg SCLx Shift Clock SSPxSR Reg SDAx MSb LSb SSPxMSK Reg Match Detect Addr Match SSPxADD Reg Start and Stop bit Detect DS41607A-page 166 Preliminary Set, Reset S, P bits (SSPxSTAT Reg) 2011 Microchip Technology Inc.
PIC16(L)F1503 21.2 SPI Mode Overview The Serial Peripheral Interface (SPI) bus is a synchronous serial data communication bus that operates in Full Duplex mode. Devices communicate in a master/slave environment where the master device initiates the communication. A slave device is controlled through a Chip Select known as Slave Select. The SPI bus specifies four signal connections: • • • • During each SPI clock cycle, a full duplex data transmission occurs.
PIC16(L)F1503 FIGURE 21-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION SPI Master SCKx SCKx SDOx SDIx SDIx SDOx General I/O General I/O SSx General I/O SCKx SDIx SDOx SPI Slave #1 SPI Slave #2 SSx SCKx SDIx SDOx SPI Slave #3 SSx 21.2.1 SPI MODE REGISTERS The MSSPx module has five registers for SPI mode operation.
PIC16(L)F1503 21.2.2 SPI MODE OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>).
PIC16(L)F1503 21.2.3 SPI MASTER MODE The master can initiate the data transfer at any time because it controls the SCKx line. The master determines when the slave (Processor 2, Figure 21-5) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPxBUF register is written to. If the SPI is only going to receive, the SDOx output could be disabled (programmed as an input).
PIC16(L)F1503 21.2.4 21.2.5 SPI SLAVE MODE In Slave mode, the data is transmitted and received as external clock pulses appear on SCKx. When the last bit is latched, the SSPxIF interrupt flag bit is set. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCKx pin. The Idle state is determined by the CKP bit of the SSPxCON1 register.
PIC16(L)F1503 FIGURE 21-7: SPI DAISY-CHAIN CONNECTION SPI Master SCK SCK SDOx SDIx SDIx SDOx General I/O SPI Slave #1 SSx SCK SDIx SDOx SPI Slave #2 SSx SCK SDIx SDOx SPI Slave #3 SSx FIGURE 21-8: SLAVE SELECT SYNCHRONOUS WAVEFORM SSx SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF Shift register SSPxSR and bit count are reset SSPxBUF to SSPxSR SDOx bit 7 bit 6 bit 7 SDIx bit 6 bit 0 bit 0 bit 7 bit 7 Input Sample SSPxIF Interrupt Flag SSPxSR to SSPxBUF DS41607A-p
PIC16(L)F1503 FIGURE 21-9: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SSx Optional SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF Valid SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDIx bit 0 bit 7 Input Sample SSPxIF Interrupt Flag SSPxSR to SSPxBUF Write Collision detection active FIGURE 21-10: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SSx Not Optional SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) Write to SSPxBUF Valid SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit
PIC16(L)F1503 21.2.6 SPI OPERATION IN SLEEP MODE In SPI Master mode, module clocks may be operating at a different speed than when in Full-Power mode; in the case of the Sleep mode, all clocks are halted. Special care must be taken by the user when the MSSPx clock is much faster than the system clock. In Slave mode, when MSSPx interrupts are enabled, after the master completes sending data, an MSSPx interrupt will wake the controller from Sleep.
PIC16(L)F1503 21.3 I2C MODE OVERVIEW FIGURE 21-11: The Inter-Integrated Circuit Bus (I2C) is a multi-master serial data communication bus. Devices communicate in a master/slave environment where the master devices initiate the communication. A slave device is controlled through addressing. VDD SCLx The I2C bus specifies two signal connections: • Serial Clock (SCLx) • Serial Data (SDAx) Figure 21-11 shows a typical connection between two processors configured as master and slave devices.
PIC16(L)F1503 When one device is transmitting a logical one, or letting the line float, and a second device is transmitting a logical zero, or holding the line low, the first device can detect that the line is not a logical one. This detection, when used on the SCLx line, is called clock stretching. Clock stretching give slave devices a mechanism to control the flow of data. When this detection is used on the SDAx line, it is called arbitration.
PIC16(L)F1503 21.4 I2C MODE OPERATION TABLE 21-2: All MSSPx I2C communication is byte oriented and shifted out MSb first. Six SFR registers and two interrupt flags interface the module with the PIC® microcontroller and user software. Two pins, SDAx and SCLx, are exercised by the module to communicate with other external I2C devices. 21.4.1 BYTE FORMAT All communication in I2C is done in 9-bit segments. A byte is sent from a master to a slave or vice-versa, followed by an Acknowledge bit sent back.
PIC16(L)F1503 21.4.5 START CONDITION 21.4.7 The I2C specification defines a Start condition as a transition of SDAx from a high to a low state while SCLx line is high. A Start condition is always generated by the master and signifies the transition of the bus from an Idle to an Active state. Figure 21-10 shows wave forms for Start and Stop conditions. A Restart is valid any time that a Stop would be valid. A master can issue a Restart if it wishes to hold the bus after terminating the current transfer.
PIC16(L)F1503 21.4.9 21.5 ACKNOWLEDGE SEQUENCE The 9th SCLx pulse for any transferred byte in I2C is dedicated as an Acknowledge. It allows receiving devices to respond back to the transmitter by pulling the SDAx line low. The transmitter must release control of the line during this time to shift in the response. The Acknowledge (ACK) is an active-low signal, pulling the SDAx line low indicated to the transmitter that the device has received the transmitted data and is ready to receive more.
PIC16(L)F1503 21.5.2 21.5.2.2 SLAVE RECEPTION When the R/W bit of a matching received address byte is clear, the R/W bit of the SSPxSTAT register is cleared. The received address is loaded into the SSPxBUF register and acknowledged. When the overflow condition exists for a received address, then not Acknowledge is given. An overflow condition is defined as either bit BF of the SSPxSTAT register is set, or bit SSPOV of the SSPxCON1 register is set.
2011 Microchip Technology Inc. Preliminary SSPOV BF SSPxIF S 1 A7 2 A6 3 A5 4 A4 5 A3 Receiving Address 6 A2 7 A1 8 9 ACK 1 D7 2 D6 4 5 D3 6 D2 7 D1 SSPxBUF is read Cleared by software 3 D4 Receiving Data D5 8 9 2 D6 First byte of data is available in SSPxBUF 1 D0 ACK D7 4 5 D3 6 D2 7 D1 SSPOV set because SSPxBUF is still full. ACK is not sent.
DS41607A-page 182 Preliminary CKP SSPOV BF SSPxIF 1 SCLx S A7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 9 R/W=0 ACK SEN 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 CKP is written to ‘1’ in software, releasing SCLx SSPxBUF is read Cleared by software Clock is held low until CKP is set to ‘1’ 1 D7 Receive Data 9 ACK SEN 3 D5 4 D4 5 D3 First byte of data is available in SSPxBUF 6 D2 7 D1 SSPOV set because SSPxBUF is still full. ACK is not sent.
2011 Microchip Technology Inc.
DS41607A-page 184 Preliminary P S ACKTIM CKP ACKDT BF SSPxIF S Receiving Address 4 5 6 7 8 When AHEN = 1; on the 8th falling edge of SCLx of an address byte, CKP is cleared Slave software clears ACKDT to ACK the received byte Received address is loaded into SSPxBUF 2 3 ACKTIM is set by hardware on 8th falling edge of SCLx 1 A7 A6 A5 A4 A3 A2 A1 9 ACK Receive Data 2 3 4 5 6 7 8 ACKTIM is cleared by hardware on 9th rising edge of SCLx When DHEN = 1; on the 8th falling edge of SCL
PIC16(L)F1503 21.5.3 SLAVE TRANSMISSION 21.5.3.2 7-bit Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPxSTAT register is set. The received address is loaded into the SSPxBUF register, and an ACK pulse is sent by the slave on the ninth bit. A master device can transmit a read request to a slave, and then clock data out of the slave. The list below outlines what software for a slave will need to do to accomplish a standard transmission.
DS41607A-page 186 Preliminary P S D/A R/W ACKSTAT CKP BF SSPxIF S 1 2 5 6 7 8 Received address is read from SSPxBUF 4 Indicates an address has been received R/W is copied from the matching address byte When R/W is set SCLx is always held low after 9th SCLx falling edge 3 9 Automatic 2 3 4 5 Set by software Data to transmit is loaded into SSPxBUF Cleared by software 1 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK Transmitting Data 2 3 4 5 7 8 CKP is not held for not ACK 6
PIC16(L)F1503 21.5.3.3 7-bit Transmission with Address Hold Enabled Setting the AHEN bit of the SSPxCON3 register enables additional clock stretching and interrupt generation after the 8th falling edge of a received matching address. Once a matching address has been clocked in, CKP is cleared and the SSPxIF interrupt is set. Figure 21-18 displays a standard waveform of a 7-bit Address Slave Transmission with AHEN enabled. 1. 2. Bus starts Idle.
DS41607A-page 188 Preliminary D/A R/W ACKTIM CKP ACKSTAT ACKDT BF SSPxIF S Receiving Address 2 4 5 6 7 8 Slave clears ACKDT to ACK address ACKTIM is set on 8th falling edge of SCLx 9 ACK When R/W = 1; CKP is always cleared after ACK R/W = 1 Received address is read from SSPxBUF 3 When AHEN = 1; CKP is cleared by hardware after receiving matching address.
PIC16(L)F1503 21.5.4 SLAVE MODE 10-BIT ADDRESS RECEPTION 21.5.5 This section describes a standard sequence of events for the MSSPx module configured as an I2C Slave in 10-bit Addressing mode. Figure 21-19 is used as a visual reference for this description. This is a step by step process of what must be done by slave software to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. Bus starts Idle.
DS41607A-page 190 Preliminary CKP UA BF SSPxIF S 1 1 2 1 5 6 7 0 A9 A8 8 Set by hardware on 9th falling edge 4 1 When UA = 1; SCLx is held low 9 ACK If address matches SSPxADD it is loaded into SSPxBUF 3 1 Receive First Address Byte 1 3 4 5 6 7 8 Software updates SSPxADD and releases SCLx 2 9 A7 A6 A5 A4 A3 A2 A1 A0 ACK Receive Second Address Byte 1 3 4 5 6 7 8 9 1 3 4 5 6 7 Data is read from SSPxBUF SCLx is held low while CKP = 0 2 8 9 D7 D6 D5 D4 D3 D
2011 Microchip Technology Inc.
DS41607A-page 192 Preliminary D/A R/W ACKSTAT CKP UA BF SSPxIF 4 5 6 7 Set by hardware 3 Indicates an address has been received UA indicates SSPxADD must be updated SSPxBUF loaded with received address 2 8 9 1 SCLx S Receiving Address R/W = 0 1 1 1 1 0 A9 A8 ACK 1 3 4 5 6 7 8 After SSPxADD is updated, UA is cleared and SCLx is released Cleared by software 2 9 A7 A6 A5 A4 A3 A2 A1 A0 ACK Receiving Second Address Byte 1 4 5 6 7 8 Set by hardware 2 3 R/W is copied from
PIC16(L)F1503 21.5.6 21.5.6.2 CLOCK STRETCHING Clock stretching occurs when a device on the bus holds the SCLx line low, effectively pausing communication. The slave may stretch the clock to allow more time to handle data or prepare a response for the master device. A master device is not concerned with stretching as anytime it is active on the bus and not transferring data it is stretching.
PIC16(L)F1503 21.5.8 In 10-bit Address mode, the UA bit will not be set on the reception of the general call address. The slave will prepare to receive the second byte as data, just as it would in 7-bit mode. GENERAL CALL ADDRESS SUPPORT The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master device. The exception is the general call address which can address all devices.
PIC16(L)F1503 21.6 I2C MASTER MODE 21.6.1 Master mode is enabled by setting and clearing the appropriate SSPM bits in the SSPxCON1 register and by setting the SSPEN bit. In Master mode, the SDAx and SCKx pins must be configured as inputs. The MSSP peripheral hardware will override the output driver TRIS controls when necessary to drive the pins low. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions.
PIC16(L)F1503 21.6.2 CLOCK ARBITRATION Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, releases the SCLx pin (SCLx allowed to float high). When the SCLx pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCLx pin is actually sampled high. When the SCLx pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and begins counting.
PIC16(L)F1503 21.6.4 I2C MASTER MODE START by hardware; the Baud Rate Generator is suspended, leaving the SDAx line held low and the Start condition is complete. CONDITION TIMING To initiate a Start condition, the user sets the Start Enable bit, SEN bit of the SSPxCON2 register. If the SDAx and SCLx pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and starts its count.
PIC16(L)F1503 21.6.5 I2C MASTER MODE REPEATED SSPxCON2 register will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDAx pin held low. As soon as a Start condition is detected on the SDAx and SCLx pins, the S bit of the SSPxSTAT register will be set. The SSPxIF bit will not be set until the Baud Rate Generator has timed out.
PIC16(L)F1503 21.6.6 I2C MASTER MODE TRANSMISSION 21.6.6.3 Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPxBUF register. This action will set the Buffer Full flag bit, BF and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDAx pin after the falling edge of SCLx is asserted.
DS41607A-page 200 S Preliminary R/W PEN SEN BF (SSPxSTAT<0>) SSPxIF SCLx SDAx A6 A5 A4 A3 A2 A1 3 4 5 Cleared by software 2 6 7 8 9 After Start condition, SEN cleared by hardware SSPxBUF written 1 D7 1 SCLx held low while CPU responds to SSPxIF ACK = 0 R/W = 0 SSPxBUF written with 7-bit address and R/W start transmit A7 Transmit Address to Slave 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 SSPxBUF is written by software Cleared by software service routine from SSPx interrupt 2
PIC16(L)F1503 21.6.7 I2C MASTER MODE RECEPTION 21.6.7.4 Master mode reception is enabled by programming the Receive Enable bit, RCEN bit of the SSPxCON2 register. Note: The MSSPx module must be in an Idle state before the RCEN bit is set or the RCEN bit will be disregarded. The Baud Rate Generator begins counting and on each rollover, the state of the SCLx pin changes (high-to-low/low-to-high) and data is shifted into the SSPxSR.
DS41607A-page 202 Preliminary RCEN ACKEN SSPOV BF (SSPxSTAT<0>) SDAx = 0, SCLx = 1 while CPU responds to SSPxIF SSPxIF S 1 A7 2 4 5 6 Cleared by software 3 A6 A5 A4 A3 A2 Transmit Address to Slave 7 8 9 ACK Receiving Data from Slave 2 3 5 6 7 8 D0 9 ACK Receiving Data from Slave 2 3 4 RCEN cleared automatically 5 6 7 Cleared by software Set SSPxIF interrupt at end of Acknowledge sequence Data shifted in on falling edge of CLK 1 ACK from Master SDAx = ACKDT = 0 Clea
PIC16(L)F1503 21.6.8 ACKNOWLEDGE SEQUENCE TIMING 21.6.9 A Stop bit is asserted on the SDAx pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN bit of the SSPxCON2 register. At the end of a receive/transmit, the SCLx line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDAx line low. When the SDAx line is sampled low, the Baud Rate Generator is reloaded and counts down to ‘0’.
PIC16(L)F1503 FIGURE 21-31: STOP CONDITION RECEIVE OR TRANSMIT MODE SCLx = 1 for TBRG, followed by SDAx = 1 for TBRG after SDAx sampled high. P bit (SSPxSTAT<4>) is set. Write to SSPxCON2, set PEN PEN bit (SSPxCON2<2>) is cleared by hardware and the SSPxIF bit is set Falling edge of 9th clock TBRG SCLx SDAx ACK P TBRG TBRG TBRG SCLx brought high after TBRG SDAx asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period. 21.6.
PIC16(L)F1503 FIGURE 21-32: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCLx = 0 SDAx line pulled low by another source SDAx released by master Sample SDAx. While SCLx is high, data does not match what is driven by the master. Bus collision has occurred. SDAx SCLx Set bus collision interrupt (BCLxIF) BCLxIF 2011 Microchip Technology Inc.
PIC16(L)F1503 21.6.13.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDAx or SCLx are sampled low at the beginning of the Start condition (Figure 21-32). SCLx is sampled low before SDAx is asserted low (Figure 21-33). During a Start condition, both the SDAx and the SCLx pins are monitored. If the SDAx pin is sampled low during this count, the BRG is reset and the SDAx line is asserted early (Figure 21-34).
PIC16(L)F1503 FIGURE 21-34: BUS COLLISION DURING START CONDITION (SCLX = 0) SDAx = 0, SCLx = 1 TBRG TBRG SDAx Set SEN, enable Start sequence if SDAx = 1, SCLx = 1 SCLx SCLx = 0 before SDAx = 0, bus collision occurs. Set BCLxIF. SEN SCLx = 0 before BRG time-out, bus collision occurs. Set BCLxIF.
PIC16(L)F1503 21.6.13.2 Bus Collision During a Repeated Start Condition If SDAx is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, Figure 21-35). If SDAx is sampled high, the BRG is reloaded and begins counting. If SDAx goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDAx at exactly the same time.
PIC16(L)F1503 21.6.13.3 Bus Collision During a Stop Condition The Stop condition begins with SDAx asserted low. When SDAx is sampled low, the SCLx pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPxADD and counts down to 0. After the BRG times out, SDAx is sampled. If SDAx is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 21-37).
PIC16(L)F1503 TABLE 21-3: Name INTCON SUMMARY OF REGISTERS ASSOCIATED WITH I2C™ OPERATION Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: INTE IOCIE TMR0IF INTF IOCIF 66 Bit 7 Bit 6 Bit 5 Bit 4 GIE PEIE TMR0IE PIE1 TMR1GIE ADIE — — SSP1IE — TMR2IE TMR1IE 67 PIE2 — C2IE C1IE — BCLIE NCO1IE — — 68 — PIR1 TMR1GIF ADIF — — SSP1IF TMR2IF TMR1IF 70 PIR2 — C2IF C1IF — BCL1IF NCO1IF — — 71 TRISA — — TRISA5 TRISA4 —(1) TRISA2 TRISA1 TRISA0 102 SSPAD
PIC16(L)F1503 21.7 BAUD RATE GENERATOR The MSSPx module has a Baud Rate Generator available for clock generation in both I2C and SPI Master modes. The Baud Rate Generator (BRG) reload value is placed in the SSPxADD register (Register 21-6). When a write occurs to SSPxBUF, the Baud Rate Generator will automatically begin counting down. Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state. module clock line.
PIC16(L)F1503 REGISTER 21-1: SSPXSTAT: SSPX STATUS REGISTER R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SMP: SPI Data Input Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sam
PIC16(L)F1503 REGISTER 21-2: SSPXCON1: SSPX CONTROL REGISTER 1 R/C/HS-0/0 R/C/HS-0/0 R/W-0/0 R/W-0/0 WCOL SSPOV SSPEN CKP R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SSPM<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared bit 7 WCOL: Write Collision Detect bit Master mode: 1
PIC16(L)F1503 REGISTER 21-3: SSPXCON2: SSPX CONTROL REGISTER 2 R/W-0/0 R-0/0 R/W-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/W/HS-0/0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware S = User set bit 7 GCEN: General Call Enable bit (i
PIC16(L)F1503 REGISTER 21-4: SSPXCON3: SSPX CONTROL REGISTER 3 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only)(3) 1 = Indicates the I2C bus is in
PIC16(L)F1503 REGISTER 21-5: R/W-1/1 SSPXMSK: SSPX MASK REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 MSK<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 MSK<7:1>: Mask bits 1 = The received address bit n is compared to SSPxADD to detect I2C address match 0 = The received address bi
PIC16(L)F1503 NOTES: 2011 Microchip Technology Inc.
PIC16(L)F1503 22.0 PULSE WIDTH MODULATION (PWM) MODULE For a step-by-step procedure on how to set up this module for PWM operation, refer to Section 22.1.9 “Setup for PWM Operation using PWMx Pins”.
PIC16(L)F1503 22.1 PWMx Pin Configuration All PWM outputs are multiplexed with the PORT data latch. The user must configure the pins as outputs by clearing the associated TRIS bits. Note: 22.1.1 Clearing the PWMxOE bit will relinquish control of the PWMx pin. FUNDAMENTAL OPERATION The PWM module produces a 10-bit resolution output. Timer2 and PR2 set the period of the PWM. The PWMxDCL and PWMxDCH registers configure the duty cycle.
PIC16(L)F1503 22.1.5 PWM RESOLUTION The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is 10 bits when PR2 is 255. The resolution is a function of the PR2 register value as shown by Equation 22-4.
PIC16(L)F1503 22.1.9 SETUP FOR PWM OPERATION USING PWMx PINS The following steps should be taken when configuring the module for PWM operation using the PWMx pins: 1. Disable the PWMx pin output driver(s) by setting the associated TRIS bit(s). 2. Clear the PWMxCON register. 3. Load the PR2 register with the PWM period value. 4. Clear the PWMxDCH register and bits <7:6> of the PWMxDCL register. 5. Configure and start Timer2: • Clear the TMR2IF interrupt flag bit of the PIR1 register. See Note below.
PIC16(L)F1503 22.
PIC16(L)F1503 REGISTER 22-2: R/W-x/u PWMxDCH: PWM DUTY CYCLE HIGH BITS R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u PWMxDCH<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PWMxDCH<7:0>: PWM Duty Cycle Most Significant bits These bits are the MSbs of the PWM duty cycle.
PIC16(L)F1503 23.0 CONFIGURABLE LOGIC CELL (CLC) The Configurable Logic Cell (CLCx) provides programmable logic that operates outside the speed limitations of software execution. The logic cell takes up to 16 input signals and through the use of configurable gates reduces the 16 inputs to four logic lines that drive one of eight selectable single-output logic functions.
PIC16(L)F1503 23.1 CLCx Setup 23.1.1 Programming the CLCx module is performed by configuring the 4 stages in the logic signal flow. The 4 stages are: • • • • Data selection Data gating Logic function selection Output polarity Each stage is setup at run time by writing to the corresponding CLCx Special Function Registers. This has the added advantage of permitting logic reconfiguration on-the-fly during program execution.
PIC16(L)F1503 23.1.2 DATA GATING Outputs from the input multiplexers are directed to the desired logic function input through the data gating stage. Each data gate can direct any combination of the four selected inputs. Note: 23.1.3 Data gating is undefined at power-up. The gate stage is more than just signal direction. The gate can be configured to direct each input signal as inverted or non-inverted data. Directed signals are ANDed together in each gate.
PIC16(L)F1503 23.1.5 23.2 CLCx SETUP STEPS The following steps should be followed when setting up the CLCx: • Disable CLCx by clearing the LCxEN bit. • Select desired inputs using CLCxSEL0 and CLCxSEL1 registers (See Table 23-1). • Clear any associated ANSEL bits. • Set all TRIS bits associated with inputs. • Clear all TRIS bits associated with outputs. • Enable the chosen inputs through the four gates using CLCxGLS0, CLCxGLS1, CLCxGLS2, and CLCxGLS3 registers.
PIC16(L)F1503 FIGURE 23-2: CLCxIN[0] CLCxIN[1] CLCxIN[2] CLCxIN[3] CLCxIN[4] CLCxIN[5] CLCxIN[6] CLCxIN[7] INPUT DATA SELECTION AND GATING 000 Data Selection Data GATE 1 lcxd1T LCxD1G1T lcxd1N LCxD1G1N 111 LCxD2G1T LCxD1S<2:0> LCxD2G1N CLCxIN[4] CLCxIN[5] CLCxIN[6] CLCxIN[7] CLCxIN[8] CLCxIN[9] CLCxIN[10] CLCxIN[11] lcxg1 000 LCxD3G1T lcxd2T LCxG1POL LCxD3G1N lcxd2N LCxD4G1T 111 LCxD2S<2:0> CLCxIN[8] CLCxIN[9] CLCxIN[10] CLCxIN[11] CLCxIN[12] CLCxIN[13] CLCxIN[14] CLCxIN[15] LCxD4G1N 00
PIC16(L)F1503 FIGURE 23-3: PROGRAMMABLE LOGIC FUNCTIONS AND - OR OR - XOR lcxg1 lcxg1 lcxg2 lcxg2 lcxq lcxg3 lcxq lcxg3 lcxg4 lcxg4 LCxMODE<2:0>= 000 LCxMODE<2:0>= 001 4-Input AND S-R Latch lcxg1 lcxg1 lcxg2 lcxg2 lcxq lcxg3 S lcxg3 lcxg4 R lcxg4 LCxMODE<2:0>= 010 lcxq Q LCxMODE<2:0>= 011 1-Input D Flip-Flop with S and R 2-Input D Flip-Flop with R lcxg4 lcxg2 D S lcxg4 Q lcxq D lcxg2 lcxg1 lcxg1 Q lcxq R R lcxg3 lcxg3 LCxMODE<2:0>= 100 LCxMODE<2:0>= 101 J-K Fli
PIC16(L)F1503 23.
PIC16(L)F1503 REGISTER 23-2: CLCxPOL: SIGNAL POLARITY CONTROL REGISTER R/W-0/0 U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxPOL — — — LCxG4POL LCxG3POL LCxG2POL LCxG1POL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxPOL: LCOUT Polarity Control bit 1 = The output of the logic cell is inverted 0 =
PIC16(L)F1503 REGISTER 23-3: U-0 CLCxSEL0: MULTIPLEXER DATA 1 AND 2 SELECT REGISTER R/W-x/u — R/W-x/u R/W-x/u LCxD2S<2:0> U-0 — R/W-x/u R/W-x/u R/W-x/u LCxD1S<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-4 LCxD2S<2:0>: Input Data 2 Selection Control bits(1) 111 = CL
PIC16(L)F1503 REGISTER 23-4: U-0 CLCxSEL1: MULTIPLEXER DATA 3 AND 4 SELECT REGISTER R/W-x/u — R/W-x/u R/W-x/u LCxD4S<2:0> U-0 — R/W-x/u R/W-x/u R/W-x/u LCxD3S<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-4 LCxD4S<2:0>: Input Data 4 Selection Control bits(1) 111 = CL
PIC16(L)F1503 REGISTER 23-5: CLCxGLS0: GATE 1 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG1D4T LCxG1D4N LCxG1D3T LCxG1D3N LCxG1D2T LCxG1D2N LCxG1D1T LCxG1D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxG1D4T: Gate 1 Data 4 True (non-inverted) bit 1 =
PIC16(L)F1503 REGISTER 23-6: CLCxGLS1: GATE 2 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG2D4T LCxG2D4N LCxG2D3T LCxG2D3N LCxG2D2T LCxG2D2N LCxG2D1T LCxG2D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxG2D4T: Gate 2 Data 4 True (non-inverted) bit 1 =
PIC16(L)F1503 REGISTER 23-7: CLCxGLS2: GATE 3 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG3D4T LCxG3D4N LCxG3D3T LCxG3D3N LCxG3D2T LCxG3D2N LCxG3D1T LCxG3D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxG3D4T: Gate 3 Data 4 True (non-inverted) bit 1 =
PIC16(L)F1503 REGISTER 23-8: CLCxGLS3: GATE 4 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG4D4T LCxG4D4N LCxG4D3T LCxG4D3N LCxG4D2T LCxG4D2N LCxG4D1T LCxG4D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxG4D4T: Gate 4 Data 4 True (non-inverted) bit 1 =
PIC16(L)F1503 REGISTER 23-9: CLCDATA: CLC DATA OUTPUT U-0 U-0 U-0 U-0 U-0 U-0 R-0 R-0 — — — — — — MLC2OUT MLC1OUT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1 MLC2OUT: Mirror copy of LC2OUT bit bit 0 MLC1OUT: Mirror copy of LC1OUT bit DS41607A-page 238 Prelim
PIC16(L)F1503 TABLE 23-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH CLCx Bit5 Bit4 Bit1 Bit0 Register on Page Bit7 Bit6 BIt3 Bit2 ANSELC — — — APFCON — — SDOSEL — ANSC3 ANSC2 ANSC1 ANSC0 107 SSSEL T1GSEL — CLC1SEL NCO1SEL 100 CLC1CON LC1EN LC1OE LC1OUT LC1INTP LC1INTN LC1MODE<2:0> 230 CLC2CON LC2EN LC2OE LC2OUT LC2INTP LC2INTN LC2MODE<2:0> 230 CLCDATA — — — — — — MLC2OUT MLC1OUT 234 CLC1GLS0 LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N
PIC16(L)F1503 24.0 NUMERICALLY CONTROLLED OSCILLATOR (NCO) MODULE The Numerically Controlled Oscillator (NCOx) module is a timer that uses the overflow from the addition of an increment value to divide the input frequency. The advantage of the addition method over simple counter driven timer is that the resolution of division does not vary with the divider value. The NCOx is most useful for applications that require frequency accuracy and fine resolution at a fixed duty cycle.
DS41607A-page 241 Preliminary Note 1: 2 NxEN NxCKS<2:0> 00 01 10 11 20 (1) NCOx Clock 20 Accumulator 16 Buffer 16 Increment Ripple Counter NCOx Clock Overflow Q Q R Q Q S NxPWS<2:0> Reset 3 Overflow D Interrupt event NxPOL NxPFM 1 0 NUMERICALLY CONTROLLED OSCILLATOR (NCOx) MODULE SIMPLIFIED BLOCK DIAGRAM The increment registers are double-buffered to allow for value changes to be made without first disabling the NCOx module. They are shown here for reference.
PIC16(L)F1503 24.1 NCOx OPERATION 24.1.3 ADDER The NCOx operates by repeatedly adding a fixed value to an accumulator. Additions occur at the input clock rate. The accumulator will overflow with a carry periodically, which is the raw NCOx output. This effectively reduces the input clock by the ratio of the addition value to the maximum accumulator value. See Equation 24-1. The NCOx Adder is a full adder, which operates independently from the system clock.
PIC16(L)F1503 24.2 FIXED DUTY CYCLE (FDC) MODE In Fixed Duty Cycle (FDC) mode, every time the accumulator overflows, the output is toggled. This provides a 50% duty cycle, provided that the increment value remains constant. For more information, see Figure 24-2. The FDC mode is selected by clearing the NxPFM bit in the NCOxCON register. 24.3 PULSE FREQUENCY (PF) MODE In Pulse Frequency (PF) mode, every time the accumulator overflows, the output becomes active for one or more clock periods.
DS41607A-page 244 Preliminary NCOx Output PF mode NCOx PWS = 010 NCOx Output PF mode NCOX PWS = 000 NCOx Output FDC mode Interrupt Event Overflow PWS = 000 NCOx Accumulator Value Accumulator Input Overflow NCOx Accumulator Input NCOx Increment Value 0000h 02000h 2000h 04000h 4000h 06000h 6000h 08000h 0C000h Tadder 0E000h 8000h A000h C000h Overflow is the MSB of the accumulator 0A000h FDC OUTPUT MODE OPERATION DIAGRAM Clock Source FIGURE 24-2: E000h 10000h Tadder 0000h Tadder
PIC16(L)F1503 24.5 Interrupts When the accumulator overflows, the NCOx Interrupt Flag bit, NCOxIF, of the PIRx register is set. To enable the interrupt event, the following bits must be set: • • • • NxEN bit of the NCOxCON register NCOxIE bit of the PIEx register PEIE bit of the INTCON register GIE bit of the INTCON register The interrupt must be cleared by software by clearing the NCOxIF bit in the Interrupt Service Routine. 24.
PIC16(L)F1503 24.
PIC16(L)F1503 REGISTER 24-3: R/W-0/0 NCOxACCL: NCOx ACCUMULATOR REGISTER – LOW BYTE R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 NCOxACC<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 NCOxACC<7:0>: NCOx Accumulator, low byte REGISTER 24-4: R/W-0/0 NCOxACCH: NCOx ACCUMULATOR REGISTER – HIGH
PIC16(L)F1503 REGISTER 24-6: R/W-0/0 NCOxINCL: NCOx INCREMENT REGISTER – LOW BYTE R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-1/1 NCOxINC<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 NCOxINC<7:0>: NCOx Increment, low byte REGISTER 24-7: R/W-0/0 NCOxINCH: NCOx INCREMENT REGISTER – HIGH BYTE
PIC16(L)F1503 TABLE 24-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH NCOx Bit 2 Bit 1 Bit 0 Register on Page T1GSEL — CLC1SEL NCO1SEL 100 IOCIE TMR0IF INTF IOCIF 66 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 APFCON — — SDOSEL SSSEL INTCON GIE PEIE TMR0IE INTE NCO1ACCH NCO1ACC<15:8> 247 NCO1ACCL NCO1ACC<7:0> 247 — NCO1ACCU NCO1CLK NCO1CON NCO1ACC<19:16> N1PWS<2:0> N1EN N1OE N1OUT NCO1INCH — — — N1POL — — 247 N1CKS<1:0> — N1PFM NCO1INC<15:8> NCO1INCL 246 246 248 NCO1IN
PIC16(L)F1503 25.0 COMPLEMENTARY WAVEFORM GENERATOR (CWG) MODULE The Complementary Waveform Generator (CWG) produces a complementary waveform with dead-band delay from a selection of input sources.
2011 Microchip Technology Inc.
PIC16(L)F1503 FIGURE 25-2: TYPICAL CWG OPERATION WITH PWM1 (NO AUTO-SHUTDOWN) cwg_clock PWM1 CWGxA Rising Edge Dead Band Falling Edge Dead Band Rising Edge Dead Band Rising Edge D Falling Edge Dead Band CWGxB DS41607A-page 252 Preliminary 2011 Microchip Technology Inc.
PIC16(L)F1503 25.1 Fundamental Operation The CWG generates a two output complementary waveform from one of four selectable input sources. The off-to-on transition of each output can be delayed from the on-to-off transition of the other output, thereby, creating a time delay immediately where neither output is driven. This is referred to as dead time and is covered in Section 25.5 “Dead-Band Control”.
PIC16(L)F1503 25.7 Falling Edge Dead Band The falling edge dead band delays the turn-on of the CWGxB output from when the CWGxA output is turned off. The falling edge dead-band time starts when the falling edge of the input source goes true. When this happens, the CWGxA output is immediately turned off and the falling edge dead-band delay time starts. When the falling edge dead-band delay time is reached, the CWGxB output is turned on.
2011 Microchip Technology Inc.
PIC16(L)F1503 EQUATION 25-1: DEAD-BAND UNCERTAINTY 1 TDEADBAND_UNCERTAINTY = ----------------------------Fcwg_clock Example: Fcwg_clock = 16 MHz Therefore: 1 TDEADBAND_UNCERTAINTY = ----------------------------Fcwg_clock 1 = ------------------16 MHz = 625ns DS41607A-page 256 Preliminary 2011 Microchip Technology Inc.
PIC16(L)F1503 25.9 Auto-shutdown Control 25.10 Operation During Sleep Auto-shutdown is a method to immediately override the CWG output levels with specific overrides that allow for safe shutdown of the circuit. The shutdown state can be either cleared automatically or held until cleared by software. 25.9.1 SHUTDOWN The shutdown state can be entered by either of the following two methods: • Software generated • External Input 25.9.1.
PIC16(L)F1503 25.11 Configuring the CWG 25.11.1 The following steps illustrate how to properly configure the CWG to ensure a synchronous start: The levels driven to the output pins, while the shutdown input is true, are controlled by the GxASDLA and GxASDLB bits of the CWGxCON2 register (Register 25-3). GxASDLA controls the CWG1A override level and GxASDLB controls the CWG1B override level. The control bit logic level corresponds to the output logic drive level while in the shutdown state.
2011 Microchip Technology Inc.
PIC16(L)F1503 25.
PIC16(L)F1503 REGISTER 25-2: R/W-x/u CWGxCON1: CWG CONTROL REGISTER 1 R/W-x/u GxASDLB<1:0> R/W-x/u R/W-x/u U-0 GxASDLA<1:0> — R/W-0/0 R/W-0/0 R/W-0/0 GxIS<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-6 GxASDLB<1:0>: CWGx Shutdown State for CWGxB When an auto shutdown
PIC16(L)F1503 REGISTER 25-3: CWGxCON2: CWG CONTROL REGISTER 2 R/W-0/0 R/W-0/0 G1ASE G1ARSEN U-0 — U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — G1ASDC2 G1ASDC1 G1ASDFLT G1ASDCLC2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 G1ASE: Auto-Shutdown Event Status bit 1 = An auto-shu
PIC16(L)F1503 REGISTER 25-4: U-0 CWGxDBR: COMPLEMENTARY WAVEFORM GENERATOR (CWGx) RISING DEAD-BAND COUNT REGISTER U-0 — R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u CWGxDBR<5:0> — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 CWGxDBR<
PIC16(L)F1503 TABLE 25-1: Name ANSELA CWG1CON0 CWG1CON1 CWG1CON2 CWG1DBF SUMMARY OF REGISTERS ASSOCIATED WITH CWG Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — — ANSA4 — ANSA2 ANSA1 ANSA0 103 G1EN G1OEB G1OEA G1POLB G1POLA — — G1CS0 — — G1ASDC2 G1ASDC1 G1ASDLB<1:0> G1ASDLA<1:0> G1IS<1:0> 260 261 G1ASE G1ARSEN — — CWG1DBF<5:0> 263 CWG1DBR<5:0> 263 — — G1ASDFLT G1ASDCLC2 262 CWG1DBR — — TRISA — — TRISA5 TRISA4 —(1) TRISA2 TRISA1
PIC16(L)F1503 NOTES: 2011 Microchip Technology Inc.
PIC16(L)F1503 26.0 IN-CIRCUIT SERIAL PROGRAMMING™ (ICSP™) ICSP™ programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can be done after the assembly process allowing the device to be programmed with the most recent firmware or a custom firmware. Five pins are needed for ICSP™ programming: • ICSPCLK • ICSPDAT • MCLR/VPP • VDD • VSS In Program/Verify mode the Program Memory, User IDs and the Configuration Words are programmed through serial communications.
PIC16(L)F1503 26.2 Low-Voltage Programming Entry Mode FIGURE 26-2: The Low-Voltage Programming Entry mode allows the PIC16(L)F1503 devices to be programmed using VDD only, without high voltage. When the LVP bit of Configuration Words is set to ‘1’, the low-voltage ICSP programming entry is enabled. To disable the Low-Voltage ICSP mode, the LVP bit must be programmed to ‘0’. VDD Entry into the Low-Voltage Programming Entry mode requires the following steps: 1. 2.
PIC16(L)F1503 For additional interface recommendations, refer to your specific device programmer manual prior to PCB design. It is recommended that isolation devices be used to separate the programming pins from other circuitry. The type of isolation is highly dependent on the specific application and may include devices such as resistors, diodes, or even jumpers. See Figure 26-4 for more information.
PIC16(L)F1503 NOTES: 2011 Microchip Technology Inc.
PIC16(L)F1503 27.0 INSTRUCTION SET SUMMARY 27.1 Read-Modify-Write Operations • Byte Oriented • Bit Oriented • Literal and Control Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction, or the destination designator ‘d’. A read operation is performed on a register even if the instruction writes to that register.
PIC16(L)F1503 FIGURE 27-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 OPCODE d f (FILE #) 0 d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 OPCODE b (BIT #) f (FILE #) 0 b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE 8 7 0 k (literal) k = 8-bit immediate value CALL and GOTO instructions only 13 11 10 OPCODE 0 k (literal)
PIC16(L)F1503 TABLE 27-3: PIC16(L)F1503 ENHANCED INSTRUCTION SET Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ADDWFC ANDWF ASRF LSLF LSRF CLRF CLRW COMF DECF INCF IORWF MOVF MOVWF RLF RRF SUBWF SUBWFB SWAPF XORWF f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d f, d Add W and f Add with Carry W and f AND W with f Arithmetic Right Shift Logical Left Shift Logical Right Shift Clea
PIC16(L)F1503 TABLE 27-3: PIC16(L)F1503 ENHANCED INSTRUCTION SET (CONTINUED) Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes CONTROL OPERATIONS 2 2 2 2 2 2 2 2 BRA BRW CALL CALLW GOTO RETFIE RETLW RETURN k – k – k k k – Relative Branch Relative Branch with W Call Subroutine Call Subroutine with W Go to address Return from interrupt Return with literal in W Return from Subroutine CLRWDT NOP OPTION RESET SLEEP TRIS – – – – – f Clear Watchdog Timer No Operation
PIC16(L)F1503 27.2 Instruction Descriptions ADDFSR Add Literal to FSRn ANDLW AND literal with W Syntax: [ label ] ADDFSR FSRn, k Syntax: [ label ] ANDLW Operands: -32 k 31 n [ 0, 1] Operands: 0 k 255 Operation: FSR(n) + k FSR(n) Status Affected: None Description: The signed 6-bit literal ‘k’ is added to the contents of the FSRnH:FSRnL register pair. k Operation: (W) .AND.
PIC16(L)F1503 BCF Bit Clear f Syntax: [ label ] BCF f,b BTFSC Bit Test f, Skip if Clear Syntax: [ label ] BTFSC f,b 0 f 127 0b7 Operands: 0 f 127 0b7 Operands: Operation: 0 (f) Operation: skip if (f) = 0 Status Affected: None Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared. Description: If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed.
PIC16(L)F1503 CALL Call Subroutine CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0 k 2047 Operands: None Operation: (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> Operation: Status Affected: None 00h WDT 0 WDT prescaler, 1 TO 1 PD Description: Call Subroutine. First, return address (PC + 1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH.
PIC16(L)F1503 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f) - 1 (destination); skip if result = 0 Operation: (f) + 1 (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in the W register.
PIC16(L)F1503 LSLF Logical Left Shift f {,d} MOVF Move f Syntax: [ label ] LSLF Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f<7>) C (f<6:0>) dest<7:1> 0 dest<0> Operation: (f) (dest) Status Affected: C, Z Description: The contents of register ‘f’ are shifted one bit to the left through the Carry flag. A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’.
PIC16(L)F1503 MOVIW Move INDFn to W Syntax: [ label ] MOVIW ++FSRn [ label ] MOVIW --FSRn [ label ] MOVIW FSRn++ [ label ] MOVIW FSRn-[ label ] MOVIW k[FSRn] Operands: n [0,1] mm [00,01, 10, 11] -32 k 31 Operation: INDFn W Effective address is determined by • FSR + 1 (preincrement) • FSR - 1 (predecrement) • FSR + k (relative offset) After the Move, the FSR value will be either: • FSR + 1 (all increments) • FSR - 1 (all decrements) • Unchanged Status Affected: MOVLP Move literal to PCLAT
PIC16(L)F1503 MOVWI Move W to INDFn Syntax: [ label ] MOVWI ++FSRn [ label ] MOVWI --FSRn [ label ] MOVWI FSRn++ [ label ] MOVWI FSRn-[ label ] MOVWI k[FSRn] Operands: Operation: Status Affected: n [0,1] mm [00,01, 10, 11] -32 k 31 W INDFn Effective address is determined by • FSR + 1 (preincrement) • FSR - 1 (predecrement) • FSR + k (relative offset) After the Move, the FSR value will be either: • FSR + 1 (all increments) • FSR - 1 (all decrements) Unchanged None Mode Syntax mm Preincre
PIC16(L)F1503 RETFIE Return from Interrupt Syntax: [ label ] RETURN RETFIE k Return from Subroutine Syntax: [ label ] None RETURN Operands: None Operands: Operation: TOS PC, 1 GIE Operation: TOS PC Status Affected: None Status Affected: None Description: Description: Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction.
PIC16(L)F1503 SUBLW Subtract W from literal Syntax: [ label ] RRF Rotate Right f through Carry Syntax: [ label ] Operands: 0 f 127 d [0,1] Operation: See description below Status Affected: C, DC, Z Status Affected: C Description: Description: The contents of register ‘f’ are rotated one bit to the right through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’.
PIC16(L)F1503 SWAPF Swap Nibbles in f XORLW Exclusive OR literal with W Syntax: [ label ] Syntax: [ label ] Operands: 0 f 127 d [0,1] Operation: SWAPF f,d (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) XORLW k Operands: 0 k 255 Operation: (W) .XOR. k W) Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register.
PIC16(L)F1503 28.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings(†) Ambient temperature under bias ....................................................................................................... -40°C to +125°C Storage temperature ........................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS, PIC16F1503 ............................................................................. -0.
PIC16(L)F1503 PIC16F1503 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C FIGURE 28-1: VDD (V) 5.5 2.5 2.3 4 0 10 16 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 28-1 for each Oscillator mode’s supported frequencies. PIC16LF1503 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C VDD (V) FIGURE 28-2: 3.6 2.5 1.
PIC16(L)F1503 28.1 DC Characteristics: PIC16(L)F1503-I/E (Industrial, Extended) PIC16LF1503 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F1503 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param. No. D001 Sym. VDD D001 D002* VDR D002* D002A* VPOR* D002A* D002B* VPORR* D002B* Characteristic Min.
PIC16(L)F1503 FIGURE 28-3: POR AND POR REARM WITH SLOW RISING VDD VDD VPOR VPORR VSS NPOR POR REARM VSS TVLOW(2) Note 1: 2: 3: TPOR(3) When NPOR is low, the device is held in Reset. TPOR 1 s typical. TVLOW 2.7 s typical. 2011 Microchip Technology Inc.
PIC16(L)F1503 28.2 DC Characteristics: PIC16(L)F1503-I/E (Industrial, Extended) PIC16LF1503 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F1503 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Conditions Min. Typ† Max. Units — 25 140 A 1.8 — 45 230 A 3.
PIC16(L)F1503 28.2 DC Characteristics: PIC16(L)F1503-I/E (Industrial, Extended) (Continued) PIC16LF1503 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F1503 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Conditions Min. Typ† Max. Units — 34 210 A 3.
PIC16(L)F1503 28.3 DC Characteristics: PIC16(L)F1503-I/E (Power-Down) PIC16LF1503 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F1503 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Power-down Base Current D022 D022 D023 D023 D023A D023A Conditions Typ† Max.
PIC16(L)F1503 28.3 DC Characteristics: PIC16(L)F1503-I/E (Power-Down) (Continued) PIC16LF1503 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F1503 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No.
PIC16(L)F1503 DC Characteristics: PIC16(L)F1503-I/E (Power-Down) (Continued) PIC16LF1503 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F1503 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Min. Typ† Max. +85°C Max.
PIC16(L)F1503 28.4 DC Characteristics: PIC16(L)F1503-I/E DC CHARACTERISTICS Param No. Sym. VIL Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Min. Typ† Max. Units — — Conditions — 0.8 V 4.5V VDD 5.5V — 0.15 VDD V 1.8V VDD 4.5V — — 0.2 VDD V 2.0V VDD 5.5V — — 0.
PIC16(L)F1503 28.5 Memory Programming Requirements Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C DC CHARACTERISTICS Param No. Sym. Characteristic Min. Typ† Max. Units Conditions Program Memory Programming Specifications D110 VIHH Voltage on MCLR/VPP pin 8.0 — 9.0 V D111 IDDP Supply Current during Programming — — 10 mA 2.7 — VDD max. V D113 VPEW VDD for Bulk Erase VDD for Write or Row Erase VDD min. — VDD max.
PIC16(L)F1503 28.6 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. TH01 TH02 TH03 TH04 TH05 Sym. Characteristic JA Thermal Resistance Junction to Ambient JC TJMAX PD Thermal Resistance Junction to Case Maximum Junction Temperature Power Dissipation PINTERNAL Internal Power Dissipation Typ. Units Conditions 70 C/W 14-pin PDIP package 95.3 C/W 14-pin SOIC package 100 C/W 14-pin TSSOP package 51.
PIC16(L)F1503 28.7 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2.
PIC16(L)F1503 28.8 AC Characteristics: PIC16(L)F1503-I/E FIGURE 28-5: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 CLKIN OS12 OS02 OS11 OS03 CLKOUT (CLKOUT Mode) Note 1: See Table 28-3. TABLE 28-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. OS01 Sym. FOSC Characteristic External CLKIN Frequency(1) Min. Typ† Max. Units Conditions DC — 0.
PIC16(L)F1503 FIGURE 28-6: CLKOUT AND I/O TIMING Cycle Write Fetch Read Execute Q4 Q1 Q2 Q3 FOSC OS12 OS11 OS20 OS21 CLKOUT OS19 OS18 OS16 OS13 OS17 I/O pin (Input) OS14 OS15 I/O pin (Output) New Value Old Value OS18, OS19 TABLE 28-3: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. OS11 OS12 Sym. TosH2ckL Characteristic Min. Typ† Max.
PIC16(L)F1503 FIGURE 28-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out Internal Reset(1) Watchdog Timer Reset(1) 31 34 34 I/O pins Note 1: Asserted low. FIGURE 28-8: BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD VBOR and VHYST VBOR (Device in Brown-out Reset) (Device not in Brown-out Reset) 37 Reset 33(1) (due to BOR) Note 1: 64 ms delay only if PWRTE bit in the Configuration Words is programmed to ‘0’.
PIC16(L)F1503 TABLE 28-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. Sym. Characteristic Min. Typ† Max. Units Conditions 2 5 — — — — s s VDD = 3.3-5V, -40°C to +85°C VDD = 3.3-5V 10 16 27 ms VDD = 3.
PIC16(L)F1503 TABLE 28-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. 40* Sym. TT0H Characteristic T0CKI High Pulse Width Min. No Prescaler TT0L T0CKI Low Pulse Width No Prescaler TT0P T0CKI Period 45* TT1H T1CKI High Synchronous, No Prescaler Time Synchronous, with Prescaler — — ns — — ns 0.5 TCY + 20 — — ns 10 — — ns Greater of: 20 or TCY + 40 N — — ns 0.
PIC16(L)F1503 TABLE 28-7: PIC16(L)F1503 A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. Sym. Characteristic AD130* TAD AD131 TCNV AD132* TACQ Min. Typ† Max. Units Conditions A/D Clock Period 1.0 — 9.0 s TOSC-based A/D Internal FRC Oscillator Period 1.0 1.6 6.
PIC16(L)F1503 FIGURE 28-11: PIC16(L)F1503 A/D CONVERSION TIMING (SLEEP MODE) BSF ADCON0, GO AD134 (TOSC/2 + TCY(1)) 1 TCY AD131 Q4 AD130 A/D CLK 9 A/D Data 8 7 6 OLD_DATA ADRES 3 2 1 0 NEW_DATA ADIF 1 TCY GO DONE Sample AD132 Sampling Stopped Note 1: If the A/D clock source is selected as FRC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2011 Microchip Technology Inc.
PIC16(L)F1503 TABLE 28-8: COMPARATOR SPECIFICATIONS Operating Conditions: 1.8V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated). Param No. Sym. Characteristics Typ. Max. Units — ±7.
PIC16(L)F1503 FIGURE 28-12: SPI MASTER MODE TIMING (CKE = 0, SMP = 0) SSx SP70 SCKx (CKP = 0) SP71 SP72 SP78 SP79 SP79 SP78 SCKx (CKP = 1) SP80 bit 6 - - - - - -1 MSb SDOx LSb SP75, SP76 SDIx MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 28-4 for load conditions.
PIC16(L)F1503 FIGURE 28-14: SPI SLAVE MODE TIMING (CKE = 0) SSx SP70 SCKx (CKP = 0) SP83 SP71 SP72 SP78 SP79 SP79 SP78 SCKx (CKP = 1) SP80 MSb SDOx LSb bit 6 - - - - - -1 SP77 SP75, SP76 SDIx MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 28-4 for load conditions.
PIC16(L)F1503 TABLE 28-10: SPI MODE REQUIREMENTS Param No. Symbol Characteristic Min. Typ† Max. Units Conditions SP70* TSSL2SCH, SSx to SCKx or SCKx input TSSL2SCL TCY — — ns SP71* TSCH SCKx input high time (Slave mode) TCY + 20 — — ns SP72* TSCL SCKx input low time (Slave mode) TCY + 20 — — ns 100 — — ns 100 — — ns 3.0-5.5V — 10 25 ns 1.8-5.
PIC16(L)F1503 FIGURE 28-17: I2C™ BUS DATA TIMING SP103 SCLx SP100 SP90 SP102 SP101 SP106 SP107 SP92 SP91 SDAx In SP110 SP109 SP109 SDAx Out Note: Refer to Figure 28-4 for load conditions. TABLE 28-11: I2C™ BUS START/STOP BITS REQUIREMENTS Param No. Symbol Characteristic SP90* TSU:STA Start condition SP91* THD:STA SP92* TSU:STO SP93 THD:STO Stop condition Typ 4700 — Max.
PIC16(L)F1503 TABLE 28-12: I2C™ BUS DATA REQUIREMENTS Param. No. Symbol SP100* THIGH SP101* TLOW SP102* TR SP103* TF SP106* THD:DAT SP107* TSU:DAT SP109* TAA SP110* SP111 * Note 1: 2: TBUF CB Characteristic Clock high time Min. Max. Units Conditions 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz SSPx module 1.5TCY — — 100 kHz mode 4.7 — s Device must operate at a minimum of 1.
PIC16(L)F1503 NOTES: DS41607A-page 310 Preliminary 2011 Microchip Technology Inc.
PIC16(L)F1503 29.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS Graphs and charts are not available at this time. 2011 Microchip Technology Inc.
PIC16(L)F1503 NOTES: DS41607A-page 312 Preliminary 2011 Microchip Technology Inc.
PIC16(L)F1503 30.0 DEVELOPMENT SUPPORT 30.
PIC16(L)F1503 30.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 30.
PIC16(L)F1503 30.7 MPLAB SIM Software Simulator 30.9 The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC16(L)F1503 30.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 30.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
PIC16(L)F1503 31.0 PACKAGING INFORMATION 31.1 Package Marking Information Example 14-Lead PDIP PIC16F1503 -I/P e3 1110017 XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 14-Lead SOIC (.150”) Example XXXXXXXXXXX XXXXXXXXXXX YYWWNNN PIC16F1503 -I/SL e3 1110017 14-Lead TSSOP Example XXXXXXXX YYWW NNN F1503IST 1110 017 16-Lead QFN (3x3x0.9 mm) Example XXXX XYYW WNNN Legend: XX...
PIC16(L)F1503 TABLE 31-1: 16-LEAD 3x3 QFN (MG) TOP MARKING Part Number PIC16F1503(T)-I/MG Marking MGA PIC16F1503(T)-E/MG MGB PIC16LF1503(T)-I/MG MGC PIC16LF1503(T)-E/MG MGD DS41607A-page 318 Preliminary 2011 Microchip Technology Inc.
PIC16(L)F1503 31.2 Package Details The following sections give the technical details of the packages.
PIC16(L)F1503 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41607A-page 320 Preliminary 2011 Microchip Technology Inc.
PIC16(L)F1503 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011 Microchip Technology Inc.
PIC16(L)F1503 3 % & % ! % 4 " ) ' % 4 $ % % " % %% 255))) & &5 4 DS41607A-page 322 Preliminary 2011 Microchip Technology Inc.
PIC16(L)F1503 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011 Microchip Technology Inc.
PIC16(L)F1503 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41607A-page 324 Preliminary 2011 Microchip Technology Inc.
PIC16(L)F1503 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011 Microchip Technology Inc.
PIC16(L)F1503 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41607A-page 326 Preliminary 2011 Microchip Technology Inc.
PIC16(L)F1503 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011 Microchip Technology Inc.
PIC16(L)F1503 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41607A-page 328 Preliminary 2011 Microchip Technology Inc.
PIC16(L)F1503 APPENDIX A: DATA SHEET REVISION HISTORY Revision A Original release (09/2011). 2011 Microchip Technology Inc.
PIC16(L)F1503 NOTES: DS41607A-page 330 Preliminary 2011 Microchip Technology Inc.
PIC16(L)F1503 INDEX A A/D Specifications.................................................... 301, 302 Absolute Maximum Ratings .............................................. 284 AC Characteristics Industrial and Extended ............................................ 297 Load Conditions ........................................................ 296 ACKSTAT ......................................................................... 199 ACKSTAT Status Flag ......................................................
PIC16(L)F1503 Core Function Register ....................................................... 24 Customer Change Notification Service ............................. 337 Customer Notification Service........................................... 337 Customer Support ............................................................. 337 CWG Auto-shutdown Control ............................................. 257 Clock Source............................................................. 253 Output Control.................
PIC16(L)F1503 SWAPF ..................................................................... 283 XORLW..................................................................... 283 XORWF..................................................................... 283 INTCON Register ................................................................ 66 Internal Oscillator Block INTOSC Specifications.................................................... 297 Internal Sampling Switch (RSS) Impedance ......................
PIC16(L)F1503 Example PWM Frequencies and Resolutions, 8 MHz................................... 220 Operation in Sleep Mode .................................. 220 Setup for Operation using PWMx pins.............. 221 System Clock Frequency Changes................... 220 PWM Period .............................................................. 219 Setup for PWM Operation using PWMx Pins............ 221 PWMxCON Register ......................................................... 222 PWMxDCH Register ...........
PIC16(L)F1503 T T1CON Register ......................................................... 25, 156 T1GCON Register............................................................. 157 T2CON (Timer2) Register ................................................. 162 T2CON Register ................................................................. 25 Temperature Indicator Associated Registers ................................................ 116 Temperature Indicator Module ..........................................
PIC16(L)F1503 NOTES: DS41607A-page 336 Preliminary 2011 Microchip Technology Inc.
PIC16(L)F1503 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC16(L)F1503 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PIC16(L)F1503 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. [X](1) PART NO.
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