Datasheet

PIC16(L)F1454/5/9
DS41639A-page 98 Preliminary  2012 Microchip Technology Inc.
REGISTER 8-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0
OSFIE C2IE C1IE
— BCL1IE USBIE ACTIE —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 OSFIE: Oscillator Fail Interrupt Enable bit
1 = Enables the Oscillator Fail interrupt
0 = Disables the Oscillator Fail interrupt
bit 6 C2IE: Comparator C2 Interrupt Enable bit
1 = Enables the Comparator C2 interrupt
0 = Disables the Comparator C2 interrupt
bit 5 C1IE: Comparator C1 Interrupt Enable bit
1 = Enables the Comparator C1 interrupt
0 = Disables the Comparator C1 interrupt
bit 4 Unimplemented: Read as ‘0’
bit 3 BCL1IE: MSSP Bus Collision Interrupt Enable bit
1 = Enables the MSSP Bus Collision Interrupt
0 = Disables the MSSP Bus Collision Interrupt
bit 2 USBIE: USB Interrupt Enable bit
1 = Enables the USB interrupt
0 = Disables the USB interrupt
bit 1 ACTIE: Active Clock Tuning Interrupt Enable bit
1 = Enables the Active Clock Tuning interrupt
0 = Disables the Active Clock Tuning interrupt
bit 0 Unimplemented: Read as ‘0’
Note: Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.