Datasheet

2012 Microchip Technology Inc. Preliminary DS41639A-page 9
PIC16(L)F145X
TABLE 3: 20-PIN ALLOCATION TABLE (PIC16(L)F1459)
I/O
20-Pin PDIP/SOIC/SSOP
20-Pin QFN
ADC
Reference
Comparator
Timer
CWG
USB
EUSART
PWM
MSSP
Interrupt
Basic
RA0 19 16 D+ IOC ICSPDAT
(3)
RA1 18 15 D- IOC ICSPCLK
(3)
RA2
RA3 4 1 T1G
(2)
SS
(2)
IOC MCLR
VPP
RA4 3 20 AN3 SOSCO
T1G
(1)
IOC OSC2
CLKOUT
CLKR
(1)
RA5 2 19 SOSCI
T1CKI
IOC OSC1
CLKIN
RB4 13 10 AN10 SDA
SDI
IOC
RB5 12 9 AN11 RX
DX
IOC
RB6 11 8 SCL
SCK
IOC
RB7 10 7 TX
CK
IOC
RC0 16 13 AN4 VREF+ C1IN+
C2IN+
ICSPDAT
RC1 15 12 AN5 C1IN1-
C2IN1-
CWGFLT INT ICSPCLK
RC2 14 11 AN6 DACOUT1 C1IN2-
C2IN2-
RC3 7 4 AN7 DACOUT2 C1IN3-
C2IN3-
—— CLKR
(2)
RC4 6 3 C1OUT
C2OUT
CWG1B
RC5 5 2 T0CKI CWG1A
PWM1
RC6 8 5 AN8 PWM2 SS
(1)
RC7 9 6 AN9 SDO
VDD 1 18 VDD
VSS 20 17 VSS
VUSB3V3 17 14 VUSB3V3
Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register.
2: Alternate location for peripheral pin function selected by the APFCON register.
3: LVP support for PIC18(L)F1XK50 legacy designs.