Datasheet

PIC16(L)F1454/5/9
DS41639A-page 84 Preliminary  2012 Microchip Technology Inc.
6.12 Determining the Cause of a Reset
Upon any Reset, multiple bits in the STATUS and
PCON registers are updated to indicate the cause of
the Reset. Tabl e 6- 3 and Table 6-4 show the Reset
conditions of these registers.
TABLE 6-3: RESET STATUS BITS AND THEIR SIGNIFICANCE
TABLE 6-4: RESET CONDITION FOR SPECIAL REGISTERS
(2)
STKOVF STKUNF RWDT RMCLR RI POR BOR TO PD Condition
0 0 1 1 10 x11Power-on Reset
0 0 1 1 10 x0xIllegal, TO
is set on POR
0 0 1 1 10 xx0Illegal, PD is set on POR
0 0 u 1 1u 011Brown-out Reset
u u 0 u uu u0uWDT Reset
u u u u uu u00WDT Wake-up from Sleep
u u u u uu u10Interrupt Wake-up from Sleep
u u u 0 uu uuuMCLR
Reset during normal operation
u u u 0 uu u10MCLR
Reset during Sleep
u u u u 0 u u u u RESET Instruction Executed
1 u u u uu uuuStack Overflow Reset (STVREN = 1)
u 1 u u uu uuuStack Underflow Reset (STVREN = 1)
Condition
Program
Counter
STATUS
Register
PCON
Register
Power-on Reset 0000h ---1 1000 00-- 110x
MCLR
Reset during normal operation 0000h ---u uuuu uu-- 0uuu
MCLR Reset during Sleep 0000h ---1 0uuu uu-- 0uuu
WDT Reset 0000h ---0 uuuu uu-- uuuu
WDT Wake-up from Sleep PC + 1 ---0 0uuu uu-- uuuu
Brown-out Reset 0000h ---1 1uuu 00-- 11u0
Interrupt Wake-up from Sleep PC + 1
(1)
---1 0uuu uu-- uuuu
RESET Instruction Executed 0000h ---u uuuu uu-- u0uu
Stack Overflow Reset (STVREN = 1) 0000h ---u uuuu 1u-- uuuu
Stack Underflow Reset (STVREN = 1) 0000h ---u uuuu u1-- uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit (GIE) is set, the return address is
pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.
2: If a Status bit is not implemented, that bit will be read as ‘0’.